MP2319 MPS | Alldatasheet
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MP2319 3A, 18V, 650kHz, High-Efficiency, Synchronous, Step-Down Converter in 8-Pin TSOT23 MP2319 Rev.1.0 www.MonolithicPower.com 1 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
DESCRIPTION
The MP2319 is a fully-integrated, high- frequency, synchronous , rectified, step -down, switch-mode converter with internal power MOSFETs. The MP2319 offers a very compact solution that achieves 3A of continuous output current with excellent load and line regulation over a wide input range . The MP2319 has synchronous mode operation for higher efficiency over the output current load range. Constant-on-time control operation provides a very fast transient respons e, easy loop design, and very tight output regulation. Full protection features include short-circuit protection (SCP), over-current protection (OCP), under-voltage protection ( UVP), over-voltage protection (OVP), and thermal shutdown. The MP2319 requires a minimal number of readily available, standard, external components and is available in a space -saving, 8-pin, TSOT23 package.
FEATURES
Wide 4.5V to 18V Operating Input Range 3A Output Current 105mΩ/57mΩ Low RDS(ON) Internal Power MOSFETs Output Adjustable from 0.8V EN Shutdown Output Discharge Internal Soft Start High-Efficiency Synchronous Mode Operation Fixed 650kHz Switching Frequency EN and Power Good for Power Sequencing Over-Current Protection (OCP) and Hiccup Thermal Shutdown Auto-Retry Over-Voltage Protection (OVP) Available in a TSOT23-8 Package
APPLICATIONS
Security Cameras Portable Devices, xDSL Devices Digital Set-Top Boxes Flat-Panel Televisions and Monitors General Purposes All MPS parts are lead -free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MP2319 IN EN VCC PG GND FB SW BST VIN EN 0.1µF 30k 9.53k 2.2µH 22µFx2 0.1µFC1 22µF 3.3V/3A VOUT 10Ω PG 4.5V-18V
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 2 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking MP2319GJ TSOT23-8 See Below * For Tape & Reel, add suffix –Z (e.g. MP2319GJ–Z) TOP MARKING APV: Product code of MP2319GJ Y: Year code PACKAGE REFERENCE TOP VIEW MP2319 FB SW GND IN BST EN MP FB SW GND IN BST EN PG VCC 4 5 TSOT23-8
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 3 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Continuous power dissipation (TA = +25°C) (2) Recommended Operating Conditions (3) Thermal Resistance (4) θJA θJC NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J (MAX), the junction -to- ambient thermal resistance θ JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 4 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C(5), unless otherwise noted. Typical value is based on the average value when TJ = 25°C. Parameter Symbol Condition Min Typ Max Units Supply Current Supply current (shutdown) IIN VEN = 0V 1.2 5 µA Supply current (quiescent) Iq VEN = 2V, VFB = 0.9V 270 350 µA MOSFET HS switch on resistance HSRDS(ON) VBST - SW = 5V 105 mΩ LS switch on resistance LSRDS(ON) VCC = 5V 57 mΩ Switch leakage SWLKG VEN = 0V, VSW = 12V/0V 1 µA Current Limit and ZCD Valley current limit ILIMIT_VY Duty = 40% 2.8 3.5 A ZCD IZCD 50 mA Switching Frequency and Minimum On/Off Timer Switching frequency Fs 510 650 790 kHz Minimum on time(6) TOn MIN 55 ns Minimum off time(6) TOff MIN 90 ns Reference and Soft Start Feedback voltage VFB TJ = 25°C 792 800 808 mV Feedback voltage VFB TJ = -40°C to +125°C 788 800 812 mV Feedback current IFB VFB = 820mV 10 50 nA Soft-start period tSS VOUT = 10% to 90% 0.8 ms Enable (EN) and UVLO EN rising threshold VEN RISING 1.22 1.285 1.35 V EN falling hysteresis VEN _Hys 140 mV EN pull-down resistor REN_PD 1.1 MΩ VIN under-voltage lockout threshold rising INUVVth 3.4 3.85 4.3 V VIN under-voltage lockout threshold hysteresis INUVHYS 670 mV VCC VCC regulator VCC 5 V VCC load regulation ICC = 5mA 3 % OVP OVP rising threshold VOVP1_RISE 1.18 1.22 1.26 VREF OVP falling threshold VOVP_FALL 1.025 1.065 1.105 VREF
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 5 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (continued) VIN = 12V, TJ = -40°C to +125°C(5), unless otherwise noted. Typical value is based on the average value when TJ = 25°C. Parameter Symbol Condition Min Typ Max Units Power Good Power good UV rising threshold PGvth_Hi 0.875 0.915 0.955 VFB Power good UV falling threshold PGvth_Lo 0.77 0.81 0.85 VFB Power good OV rising threshold PGvth_Hi_OV 1.025 1.065 1.105 VFB Power good OV falling threshold PGvth_Lo_OV 1.18 1.22 1.26 VFB Power good low to high delay PGTd 56 µs Power good high to low delay PGTd 40 µs Power good sink current capability VPG Sink 4mA 0.4 V Power good leakage current IPG_LEAK VPG = 5V 2.5 10 μA Thermal Protection Thermal shutdown(6) TSD 150 °C Thermal hysteresis(6) TSD_HYS 20 °C NOTES: 5) Not tested in production. Guaranteed by over-temperature correlation. 6) Guaranteed by design and characterization test.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 6 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VOUT = 3.3V, L = 2.2µH, TA = 25°C, unless otherwise noted.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 7 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 2.2µH, TA = 25°C, unless otherwise noted.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 8 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 2.2µH, TA = 25°C, unless otherwise noted.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 9 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, L = 2.2µH, TA = 25°C, unless otherwise noted.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 10 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. PIN FUNCTIONS Package Pin # Name Description 1 PG Power good output. The output of PG is an open drain that goes high if the output voltage is within a nominal output window. 2 IN Supply voltage. The MP2319 operates from a 4.5V to 18V input rail. C1 is needed to decouple the input rail. Connect IN using wide PCB traces. 3 SW Switch output. Connect SW using wide PCB traces. 4 GND System ground. GND is the reference ground of the regulated output voltage. GND requires careful consideration during PCB layout. Connect GND with copper traces and vias.
5 BST
Bootstrap. Connect a capacitor between SW and BS to form a floating supply across the high-side switch driver . Place a 10Ω resistor between the SW and BST cap to reduce SW voltage spikes. 6 EN Enable. Set EN = 1 to enable the MP2319. When floating, EN is pulled down to GND by an internal 1.1MΩ resistor, and the MP2319 is disabled. 7 VCC Internal bias supply. Decouple VCC with a 0.1µF to 0.22µF capacitor. The capacitor should not exceed 0.22µF. The VCC capacitor should be placed close to VCC and GND. 8 FB Feedback. FB sets the output voltage when connected to the tap of an external resistor divider that is connected between the output and GND.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 11 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. BLOCK DIAGRAM VCC EN Reference 5V LDO FB Error Amplifier PWM Comparator PG Ramp On Timer HS Driver LS Driver SW Logic Control BST REG BST VIN GND Valley Current Limit & ZCD HSG HSG LSG LSG ZCD OV Detect Comparator UV Detect Comparator xLIM OV_TH UV_TH OV_TH UV_TH Figure 1: Functional Block Diagram
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 13 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Light-load operation is also called skip mode because the HS -FET does not turn on as frequently as it does in heavy-load conditions. The frequency at which the HS -FET turns on is a function of the output current . A s the output current increases, the time period that the current modulator regulates becomes shorter, and the HS -FET turns on more frequently. The switching frequency increases in turn. The output current reaches critical levels when the current modulator time is zero, and can be determined with Equation (1): IN OUT OUT OUT SW IN (V V ) VI 2 L F V (1) The device reverts to PWM mode once the output current exceeds the critical level. Afterward, the switching frequency remains fairly constant over the output current range. Enable (EN) EN is a digital control pin that turns the regulator on and off. Drive EN high to turn on the regulator ; drive EN low to turn off the regulator. When floating, EN is pulled down to GND by an internal 1.1MΩ resistor. EN can be connected directly to VIN. EN supports an 18V input range. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The MP2319 UVLO comparator monitors the output voltage of the internal regulator (VCC). The U VLO rising threshold is about 3.85V, while its falling threshold is 3.18V consistently. Internal Soft Start (SS) Soft start (SS) prevents the converter output voltage from overshooting during start -up. When the chip starts up, the internal circuitry generates a soft -start voltage (SS) that ramps up from 0V to 1.2V. When SS is lower than REF, SS overrides REF so the error amplifier uses SS as the reference. When SS exceeds REF, the error amplifier uses REF as the reference. The SS time is set to 0.8ms internally. Power Good (PG) Indicator The MP2319 uses a power good (PG) output to indicate whether the output voltage of the module is ready or not. PG is an open -drain output. Connect PG to VCC or another voltage source through a pull -up resistor (e.g. : 100kΩ). When input voltage is applied, PG is pulled down to GND before the internal VSS > 1V. After VSS > 1V, when VFB is above 91.5% of VREF, PG is pulled high after a 56µs delay. During normal operation, PG is pulled low when VFB drops below 81% of VREF after a 40µs delay. When UVLO or OTP occurs, PG is pulled low immediately. When over-current (OC) occurs, PG is pulled low when V FB drops below 81% of VREF after a 40µs delay. PG is pulled low to indicate output over -voltage when VFB rises above 122% of VREF after a 40µs delay. If VFB falls below 105% after over -voltage protection (OVP), PG is pulled high after a 56µs delay. Over-Current Protection (OCP) and Short - Circuit Protection (SCP) The MP2319 has a valley limit control. During the LS-FET on state, the inductor current is monitored. When the sensed inductor curre nt reaches the valley current limit, the LS limit comparator (shown in Figure 1) turns over, and the MP2319 enters over -current protection (OCP) mode. The HS-FET waits until the inductor cur rent falls below the valley current limit before turning on again. Meanwhile, the output voltage drops until V FB is below the under-voltage (UV) threshold , typically 50% below the reference. Once UV is triggered, the MP2319 enters hiccup mode to restart the part periodically. During OCP, the device attempts to recover from the over-current fault with hiccup mode . The MP2319 disables the output power stage, discharges the soft-start cap, and then tries to soft-start automatically. If the over -current condition still remains after the soft-start ends, the MP2319 repeats this operation cycle until the over-current condition is removed, and then the output rises back to regulation level s. OCP is a non-latch protection.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev. 1.0 www.MonolithicPower.com 14 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Over-Voltage Protection (OVP) The MP2319 monitors the resistor-divided feedback voltage to detect over -voltage (OV). When the feedback voltage rises higher t han 122% of the target voltage, the controller enters a dynamic regulation period. During this period, the LS-FET is on until the LS current drops to -2.5A. This discharges the output to keep it within the normal range. If the OV still remains, the LS-FET turns on again after a 400ns delay. The MP2319 exits this regulation period when the feedback voltage is decreased below 106.5% of the reference voltage. Under-Voltage Lockout (UVLO) The MP2319 has under -voltage lock out protection (UVLO). When the input voltage is higher than the UVLO rising threshold voltage, the MP2319 powers up. The MP2319 shuts off when the input voltage is lower than the UVLO falling threshold voltage. UVLO is a non-latch protection. Pre-Bias Start-Up The MP2319 has been designed for monotonic start-up into pre -biased loads. If the outp ut is pre-biased to a certain voltage during start -up, the BST voltage is refreshed and charged, and the voltage on the soft -start capacitor is charged as well. If the BST voltage exceeds its rising threshold voltage , and the soft-start capacitor voltage exceeds the sensed output voltage at FB, the part begins working normally. Output Discharge The MP2319 has a discharge function that provides an active discharge path for the external output capacitor. The function is active when the part is in the EN off state. When EN is off, the HS-FET turns off, and the LS-FET turns on to discharge VOUT. When the LS-FET current reaches -1A, the LS-FET turns off. After a 400ns delay, the LS-FET turns on again. This behavior repeats until FB low occurs. Thermal Shutdown Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die temperature exceeds 150°C, the entire chip shuts down . When the temperature falls below its lower threshold (typically 130°C), the chip is enabled again. Floating Driver and Bootstrap Charging An external bootstrap capacitor powers the floating power MOSFET driver. This floating driver has its own UVLO protection with a rising threshold of 2.2V and a hysteresis of 150mV. VIN regulates the bootstrap capacitor voltage through D1, M 1, R4, C4, L1, and C2 internally (see Figure 5). If VIN - VSW exceeds 5V, U2 regulates M1 to maintain a 5V BST voltage across C4. Figure 5: Internal Bootstrap Charger Start-Up and Shutdown Circuit If both VIN and EN exceed their respe ctive thresholds, the chip starts up. The reference block starts first, generating stable reference voltages and currents, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuits. Three events can shut down the chip: EN low, VIN low, and thermal shutdown. The shutdown procedure starts by blocking the signaling path initially to avoid any fault triggering. The COMP voltage (VCOMP) and the internal supply rail are then pulled down. The floating d river is not subject to this shutdown command.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev.1.0 www.MonolithicPower.com 15 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltage The external resistor divider is used to set the output voltage (see the Typical Application on page 1). Refer to Table 1 to choose R1. R2 can then be calculated with Equation (2): OUT V 0.8V (2) The feedback circuit is shown in Figure 6. MP2319 FB VOUT R3 C6 Figure 6: Feedback Network Table 1 lists the recommended resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT (V) R1 (kΩ) R2 (kΩ) R3 (kΩ) C6 (pF) 1 30 120 1 100 1.2 30 60.4 1 100 1.8 30 24 1 100 2.5 30 14 1 100 3.3 30 9.53 1 100 5 30 5.76 1 100 Selecting the Inductor The inductor is necessary to supply constant current to the output load while being driven by the switched input voltage. A n inductor with a larger value results in less ripple current and a lower output ripple voltage. However, the larger-value inductor also has a larger physical footprint, higher series resistance, and lower saturation current. A good rule for determining the inductance value is to design the peak -to- peak ripple current in the inductor to be in the range of 30% to 40% of the maximum output current. The peak in ductor current should be below the maximum switch current limit. The inductance value can be calculated with Equation (3): OUT OUT SW L IN Where ∆IL is the peak -to-peak inductor ripple current. The inductor should not saturate under the maximum inductor peak current, which can be calculated with Equation (4): OUT OUT LP OUT SW IN VVI I (1 ) 2F L V (4) Selecting the Input Capacitor The input current to the step -down converter is discontinuous and ther efore requires a capacitor to supply AC current to the step-down converter while maintaining the DC input voltage. Ceramic capacitors are recommended for best performance and should be placed as close to VIN as possible. Capacitors with X5R and X7R ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. The capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. The input ripple current can be estimated with Equation (5): OUT OUT CIN OUT IN IN VVI I (1 ) VV (5) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (6): OUT CIN II 2 (6) For simplification, choose an input ca pacitor with an RMS current rating greater than half of the maximum load current. The input capacitance value determines the input voltage ripple of the converter. If there is an input voltage ripple requirement in the system, choose the input capacitor th at meets the specification.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev. 1.0 www.MonolithicPower.com 16 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. The input voltage ripple can be estimated with Equation (7): OUT OUT OUT IN SW IN IN IN (7) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (8): OUT IN SW IN Selecting the Output Capacitor The output capacitor is required to maintain the DC output voltage. Ceramic or POSCAP capacitors are recommended. The output voltage ripple can be estimated with Equation (9): OUT OUT OUT ESR SW IN SW OUT (9) For ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated with Equation (10): OUT OUT OUT 2 SW OUT IN (10) For POSCAP capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated with Equation (11): OUT OUT OUT ESR SW IN Besides the output ripple, a larger output capacitor can also achieve a better load transient response . Maximum output capacitor limitations should be considered i n design applications, also. If the output capacitor value is too high, the output voltage cannot reach the design value during the soft -start time and fails to regulate. The maximum output capacitor value (Co_max) can be limited approximately with Equation (20): O _MAX LIM_ AVG OUT ss OUTC (I I ) T / V (20) Where ILIM_AVG is the average start -up current during the soft-start period, and Tss is the soft - start time. PCB Layout Guidelines Efficient layout of the switching power suppli es is critical for proper function and stable operation. Poor layout design can result in poor line or load regulation and stability issues. To achieve better performances, it is recommended to use two-layer boards. Figure 7 s hows the top and bottom layers. For best results, refer to Figure 7 and follow the guidelines below. 1) Place the high current paths (GND, IN , and SW) very close to the device wi th short, direct, and wide traces. 2) Keep the input capacitor as close to IN and GND as possible. 3) Place the external feedback resistors next to FB. 4) Keep the switching node (SW) short and away from the feedback network. L 1 C 2 C 2A C 1 R6R7 R3 R1 Vin GND Vout SW GND SW BST EN / SYNC VCC GND GND C1B C1A VOUT_SENSE Figure 7: Sample Board Layout
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER MP2319 Rev. 1.0 www.MonolithicPower.com 17 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. Design Example Table 2 shows a design example when ceramic capacitors are applied. Table 2: Design Example VIN 12V VOUT 3.3V IOUT 3A The detailed application schematic s are shown in Figure 8 through Figure 13 . The typical performance and waveforms are shown in the Typical Characteristics section. For more devices applications, please refer to the related evaluation board datasheet.
MP2319 – 18V, 3A, SYNCHRONOUS, STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any app lication. MPS will not assume any legal responsibility for any said applications. MP2319 Rev. 1.0 www.MonolithicPower.com 20 6/29/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved.
PACKAGE INFORMATION
PACKAGE OUTLINE DRAWING FOR 8L TSOT23 MF-PO-D-0105 revision 3.0 FRONT VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-193, VARIATION BA. 6) DRAWING IS NOT TO SCALE. 7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) TOP VIEW RECOMMENDED LAND PATTERN SEATING PLANE SIDE VIEW DETAIL ''A'' SEE DETAIL ''A'' IAAAA PIN 1 ID See note 7 EXAMPLE TOP MARK