MP2125 MPS | Alldatasheet

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Dual 1.5A, 1.2MHz Synchronous Step-Down Converter MP2125 Rev. 1.0 www.MonolithicPower.com 1 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. The Future of Analog IC Technology

DESCRIPTION

The MP2125 is a fully integrated dual PWM step-down converter with built-in internal power MOSFETs. It is ideal for powering portable equipment that runs from a single cell Lithium- Ion (Li+) Battery, with an input range from 2.7V to 6V. The MP2125 can provide up to 1.5A of load current with output voltage as low as 0.8V for each output. It can also operate at 100% duty cycle for low dropout applications. With peak current mode control and internal compensation, the MP2125 is stable with ceramic capacitors and small inductors. Fault condition protection includes cycle-by- cycle current limiting and thermal shutdown. MP2125 is available in the small 14-pin 3mmx4mm QFN package.

FEATURES

  • 2.7V-6V Input Operation Range
  • Each Output Adjustable from 0.8V to VIN
  • 1uA Shutdown Current
  • Up to 92% Efficiency
  • 100% Duty Cycle for Low Dropout

Applications

  • Fixed 1.2MHz Frequency
  • Stable with Low ESR Output Ceramic Capacitors
  • Cycle-by-Cycle Over Current Protection
  • Thermal Shutdown
  • Short Circuit Protection
  • Available in 14-pin 3mmx4mm QFN package
  • Solid State Disk
  • DVD+/-RW Drivers
  • Smart Phones
  • PDAs
  • Digital Cameras
  • Portable Instruments “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION MP2125 FB1 FB2 EN1 GND2 GND1 VIN1 SW1 SW2 PVIN1 EN2PVIN2 VIN2 N/C Vin1 2.7V-6V Vin2 2.7V-6V EN1 EN2 1.8V/1.5A 1.8V/1.5A Vout1 Rt Rt Vout2 N/C Efficiency Curve EFFICIENCY (%) 100 OUTPUT CURRENT (A) Vin=3VVin=5V Vin=6V

MP2125 – DUAL 1.5A, 1.2MHZ SYNCHRONOURS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 2 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking Free Air Temperature (TA) MP2125DL QFN14 (3mm x 4mm) 2125 –40°C to +85°C For Tape & Reel, add suffix –Z (e.g. MP2125DL–Z). For RoHS compliant packaging, add suffix –LF (e.g. MP2125DL–LF–Z) PACKAGE REFERENCE MP2125 TOP VIEW FB1 GND1 SW1 VIN2 N/C EN2 PVIN2 EN1 FB2 VIN1 PVIN1 N/C SW2 GND2 ABSOLUTE MAXIMUM RATINGS (1) Continuous Power Dissipation (TA = +25°C) (2) Recommended Operating Conditions (3) Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J(MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D(MAX)=(TJ(MAX)- TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

MP2125 – DUAL 1.5A, 1.2MHZ SYNCHRONOUS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 3 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. ELECTRICAL CHARACTERISTICS (5) VIN = VEN = 3.6V, TA = +25°C, unless otherwise noted. Parameters Condition Min Typ Max Units Supply Current V EN= VIN, VFB = 0.9V 600 750 μA Shutdown Current V EN= 0V, VIN = 6V 0.01 1 μA Thermal Shutdown Trip Threshold Hysteresis = 20°C 150 °C EN Trip Threshold -40°C ≤ TA ≤ +85°C 0.3 1.0 1.5 V EN Input Current V EN = 0V 0.1 1.0 μA EN Input Current V EN = 6V 6 μA IN Undervoltage Lockout Threshold Rising Edge 2.15 2.40 2.65 V IN Undervoltage Lockout Hysteresis 160 mV FB Input Bias Current V FB = 0.8V -50 -2 +50 nA SW PFET On Resistance I SW = 100mA 0.25 Ω SW NFET On Resistance I SW = -100mA 0.2 Ω SW Leakage Current VEN=0V; VIN=6V VSW_=0V -1 0.1 1 μA SW Leakage Current VEN=0V; VIN=6V VSW_=6V -5 1.5 5 μA SW PFET Peak Current Limit Duty Cycle=100% 3.0 A Switching Frequency 1.0 1.2 1.4 MHz Notes: 5) Production test at +25°C. Specific ations over the temperature range are guaranteed by design and characterization PIN FUNCTIONS Pin # Name Description

1 FB1 Feedback input voltage for channel 1

2 GND1 Ground pin 1

3 SW1 Switch node to the inductor for channel 1

4 N/C Not connect

5 PVIN2 Channel 2 input supply pin for power FET

6 VIN2 Channel 2 input supply pin for controller

7 EN2 Enable input for channel 2, “High” enables channel 2. EN2 is pulled to GND with 1Meg internal resistor

8 FB2 Feedback input voltage for channel 2

9 GND2 Ground pin 2

10 SW2 Switch node to the inductor for channel 2

11 N/C Not connect

12 PVIN1 Channel 1 input supply pin for power FET

13 VIN1 Channel 1 input supply pin for controller

14 EN1 Enable input for channel 1, “High” enables channel 1. EN1 is pulled to GND with 1Meg internal resistor

MP2125 – DUAL 1.5A, 1.2MHZ SYNCHRONOUS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 4 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 5V, VOUT = 1.8V, L=3.3uH, TA = +25ºC, one channel, unless otherwise noted. Load Regulation VIN=3V EenableSupply Current vs. Input Voltage VEN=3V 2.5 3 3.5 4 4.5 5 5.5 6 Case Temperature R isevs. Output Current IOUT1=IOUT2 OUTPUT CURRENT (A) DUTY CYCLE (%) Peak Current vs. Duty Cycle LINE REGULATION (%) LOAD REGULATION (%) INPUT VOLTAGE (V) Line Regulation PEAK CURRENT(A) Efficiency Curve EFFICIENCY (%) 100 OUTPUT CURRENT (A) OUTPUT CURRENT (A) VIN=3VVIN=5V VIN=6V 400 450 500 550 600 650 700 750 INPUT VOLTAGE(V) -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 2.5 3 3.5 4 4.5 5 5.5 6 IOUT=0.75A IOUT=1.5A IOUT=0A 2.5 3.5 4.5 40 50 60 70 80 90 100 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 LOAD REGULATION (%) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 LOAD REGULATION (%) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 Load Regulation VIN=5V OUTPUT CURRENT (A) Load Regulation VIN=6V OUTPUT CURRENT (A)

MP2125 – DUAL 1.5A, 1.2MHZ SYNCHRONOUS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 5 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 5V, VOUT = 1.8V, L=3.3uH, TA = +25ºC, one channel, unless otherwise noted. VIN 20mV/div Short Entry Short Recovery Power Up without Load SW 5V/div VOUT 1V/div VIN 5V/div EN 5V/div IINDUCTOR 2A/div SW 5V/div VOUT 1V/div VIN 5V/div IINDUCTOR 2A/div SW 5V/div VOUT 1V/div IINDUCTOR 2A/div SW 5V/div VOUT 1V/div VIN 5V/div IINDUCTOR 2A/div SW 5V/div VOUT 1V/div VIN 5V/div IINDUCTOR 2A/div EN 5V/div SW 5V/div VOUT 1V/div IINDUCTOR 2A/div SW 2V/div SW 2V/div VOUT 10mV/div IINDUCTOR 2A/div VOUT 50mV/div IOUT 500mA/div

MP2125 – DUAL 1.5A, 1.2MHZ SYNCHRONOUS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 6 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. FUNCTIONAL BLOCK DIAGRAM Main Switch (PCH) Synchronous Rectifier (NCH ) 0.04 PWM Control Logic Current Sense Amp Feedback Error Amp PWMSlope Comp ICS 1.2MHz Oscillator OSC Bias Voltage Reference 0.8V EN1 FB 1 SW1 EAO IAMP 10X PWMCMP EAMP PVIN1 VIN1 To controller blocks 17pF CCRZ 1.2M Figure 1 -Functional Block Diagram (1/2 of the MP2125)

MP2125 – DUAL 1.5A, 1.2MHZ SYNCHRONOUS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 7 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. OPERATION The MP2125 is a dual channel, fixed frequency, current mode step-down converter, optimized for low voltage, Li-Ion battery powered applications where high efficiency and small size are critical. MP2125 integrates two high side PFET main switches and two low side synchronous rectifiers. It always operates in continuous conduction mode, simplifies the control scheme and eliminates the random spectrum noise due to discontinuous conduction mode. The steady state duty cycle D for this mode can be calculated as: %100V V%100fTD IN OUT OSCON ×≈××= Where TON is the main switch on time and fOSC is the oscillator frequency (1.2MHz typ.). Current Mode PWM Control Slope compensated current mode PWM control provides stable switching and cycle-by-cycle current limiting for superior load and line response as well as protection of the internal main switches and synchronous rectifiers. The MP2125 switches at a constant frequency (1.2MHz) and modulates the inductor peak current to regulate the output voltage. Specifically, for each cycle the PWM controller forces the inductor peak current to an internal reference level derived from the feedback error voltage. At normal operation for each channel, the main switch is turned on at each rise edge of the internal oscillator, and remains on for a certain period of time to ramp up the inductor current. As soon as the inductor current reaches the reference level, the main switch is turned off and immediately the synchronous rectifier will be turned on to provide the inductor current. The synchronous rectifier will stay on until the next oscillator cycle. Dropout Operation The MP2125 allows the main switch to remain on for more than one switching cycle to increase the duty cycle when the input voltage is dropping close to the output voltage. When the duty cycle reaches 100%, the main switch is held on continuously to deliver current to the output up to the PFET current limit. In this case, the output voltage becomes the input voltage minus the voltage drop across the main switch and the inductor. Maximum Load Current The MP2125 can operate down to 2.7V input voltage; however the maximum load current decreases at lower input due to a large IR drop on the main switch and synchronous rectifier. The slope compensation signal reduces the peak inductor current as a function of the duty cycle to prevent sub-harmonic oscillations at duty cycles greater than 50%. Conversely, the current limit increases as the duty cycle decreases. Short Circuit Protection When the output is shorted to ground, the oscillator frequency is reduced to prevent the inductor current from increasing beyond the PFET current limit. The PFET current limit is also reduced to lower the short circuit current. The frequency and current limit will return to the normal values once the short circuit condition is removed and the feedback voltage approaches 0.8V.

MP2125 – DUAL 1.5A, 1.2MHZ SYNCHRONOUS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 8 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.

APPLICATION INFORMATION

The MP2125 has two channels: channel 1 and channel 2. The following formulates are used for components selection of both channels. Output Voltage Setting The external resistor divider sets the output voltage. OUT Rt is recommended when output voltage is high, as the Figure 2 shows. FB Rt VOUT Figure 2―Feedback Network Table 1 lists the recommended resistor value for common output voltages. Table 1—Resistor Selection vs. Output Voltage Setting VOUT/ V Rt/ kΩ R1/ kΩ R2/ kΩ L1/ μH C2/ μF 1.2 300 4.99 10 2.2 22 1.8V 243 4.99 4.02 3.3 22 2.5V 100 121 57.6 3.3 22 3.3V 100 121 39 3.3 22 Inductor Selection A 1μH to 10μH inductor with DC current rating at least 25% higher than the maximum load current is recommended for most applications. For best efficiency, the inductor DC resistance shall be <200mΩ. See Table 2 for recommended inductors and manufacturers. For most designs, the inductance value can be derived from the following equation: OSCLIN OUTINOUT fIV VVVL ×Δ× −×= Where ΔIL is inductor ripple current. Choose inductor ripple current approximately 30% of the maximum load current, 1.5A. The maximum inductor peak current is: III L LOAD)MAX(L Δ+= Table 2—Suggested Inductors Manufacturer Part Number Inductance (μH) Dimensions LxWxH (mm3) Toko D63CB#A916 CY-3R3M 3.3 6.3X6.2X3.5 Cooper SD25-3R3 3.3 5.2X5.2X2.5 TDK SLF7045T- 3R3M2R5-PF 3.3 7X7X4.5 Input Capacitor CIN Selection The input capacitor reduces the surge current drawn from the input and switching noise from the device. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 10 μF capacitor is sufficient. Output Capacitor C OUT Selection The output capacitor keeps output voltage ripple small and ensures regulation loop stable. The output capacitor impedance shall be low at the switching frequency. Ceramic capacitors with X5R or X7R dielectrics are recommended. For forced PWM mode operation, the output ripple ΔV OUT is approximately: OUT IN OUT OUT ESR IN OSC OSC OUT V( V V ) 11V( R ) Vf L 8 f C For most applications, a 22 μF capacitor is sufficient. Thermal Dissipation Power dissipation shall be considered when operates MP2125 at maximum 1.5A output current. If the junction temperature rises above 150°C, MP2125 will be shut down by internal thermal protection circuitry. The junction-to-ambient thermal resistance of the 14-pin QFN (3mm x 4mm) R ΘJA is 50 °C/W. The maximum allowable power dissipation is about 1.6W when MP2125 is operating in a 70 °C ambient temperature environment: W6.1 W/C50 C70C150PD o oo MAX =−=

MP2125 – DUAL 1.5A, 1.2MHZ SYN CHRONOURS STEP-DOWN CONVERTER MP2125 Rev. 1.0 www.MonolithicPower.com 9 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. PCB Layout PCB layout is very important to achieve stable operation. Please follow these guidelines and take Figure3 for references. The high current paths (GND, IN and SW) should be placed very close to the device with short, direct and wide traces. Input capacitors should be placed as close as possible to the respective IN and GND pins. The external feedback resistors shall be placed next to the FB pins. Keep the switching nodes SW short and away from the feedback network. FB1 PVIN1 PVIN2 EN1 N/C SW2 VIN2 GND1 N/C EN2 GND2 FB2 VIN1 SW1 C3 VIN1 VOUT1 GND VIN2 VOUT2 GND Top Layer Bottom Layer Figure 3 -PCB Layout

MP2125 – DUAL 1.5A, 1.2MHZ SYN CHRONOURS STEP-DOWN CONVERTER NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2125 Rev. 1.0 www.MonolithicPower.com 10 12/24/2013 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN14 (3mm x 4mm) SIDE VIEW TOP VIEW 114 8 7 BOTTOM VIEW 2.90 3.10 1.60 1.80 3.90 4.10 3.20 3.40 0.50 BSC 0.18 0.30 0.80 1.00 0.00 0.05

0.20 REF

1.70 0.50 0.25 RECOMMENDED LAND PATTERN

2.90 NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VGED-3. 5) DRAWING IS NOT TO SCALE. PIN 1 ID SEE DETAIL A 3.30 0.70 PIN 1 ID OPTION B R0.20 TYP. PIN 1 ID OPTION A 0.30x45º TYP. DETAIL A 0.30 0.50 PIN 1 ID INDEX AREA