MP2005DD

MP2005 MPS | Alldatasheet

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Technical content

800mA High PSRR, ULDO Linear Regulator MP2005 Rev. 0.92 www.MonolithicPower.com 1 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. The Future of Analog IC Technology

DESCRIPTION

The MP2005 is a micropower, ultra low-dropout LDO linear regulator. It has a 1.0V to 5.5V input voltage range and can regulate the output voltage from as low as 0.5V. The MP2005 can supply up to 800mA of load current with a typical dropout voltage of 90mV. It requires a bias supply (2.7V to 5.5V) separate from V IN to run the internal reference and LDO drive circuitry. The output current comes directly from the input voltage supply for high efficiency regulation. The 0.5V internal reference voltage allows the output to be programmed to a wide range of voltages (0.5V to 4V). A low bias current of 100µA makes the MP2005 ideal for use in battery-powered applications. The bias supply V BIAS can be directly applied from the battery while V IN is powered from the high efficiency buck regulator (or other secondary supply). This reduces output noise and the size of the decoupling capacitor. Other features of MP2005 include thermal overload and current limit protection, stability with ultra low ESR ceramic capacitors as low as 1μF, and fast transient response. The MP2005 is available in a 8-pin QFN (2mm x 3mm) package.

FEATURES

• Wide 1.0V to 5.5V Input Voltage Range
• Stable with 1 μF Ceramic Capacitor
• Ultra-Low Dropout (ULDO) voltage: 90mV@800mA
• 2% Accurate Output Voltage
• Adjustable Output Range of 0.5V to 4V
• High PSRR o 65dB at 1KHz o 48dB at 1MHz
• Better Than 0.0005%/mA Load Regulation
• Stable With Low-ESR Output Capacitors
• Low 100 μA Ground Current
• Internal Thermal Protection
• Current Limit Protection
• 1µA Typical Quiescent Current at Shutdown

APPLICATIONS

• Low Current Regulators
• Low Power Handheld Devices
• Battery Powered Systems
• Cellular Phones
• Portable Electronic Equipment
• Post Regulation for Switching Power Supplies
• Power Supplies “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 2 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved.

ORDERING INFORMATION

Part Number* Package Top Marking Free Air Temperature (TA) MP2005DD QFN8 (2mm x 3mm) N3 –40°C to +85°C * For Tape & Reel, add suffix –Z (e.g. MP2005DD–Z) For RoHS compliant packaging, add suffix –LF (e.g. MP2005DD–LF–Z) PACKAGE REFERENCE TOP VIEW IN BIAS NC GND OUT FB NC EN EXPOSED PAD ON BACKSIDE CONNECT TO GND ABSOLUTE MAXIMUM RATINGS (1) Continuous Power Dissipation (T A = +25°C) (2) Recommended Operating Conditions (3) Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J(MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)- TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 3 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition Min Typ Max Units VIN Operating Voltage 1.0 5.5 V VBIAS Operating Voltage 2.7 5.5 V VIN Operating Current V OUT = 1.2V 4 10 μA VBIAS Operating Current I OUT = 10µA, VOUT = 1.2V 100 150 μA Dropout Voltage I OUT = 800mA, VBIAS = 3.6V 70 90 mV VIN Line Regulation IOUT = 1mA, VIN = 1.0V to 5.5V VBIAS = 3.6V VOUT = 0.5V 0.002 %/V VBIAS Line Regulation IOUT = 100mA, VBIAS = 2.7V to 5.5V VOUT = 0.5V VIN = 1.5V 0.04 %/V Load Regulation I OUT = 1mA to 800mA 0.0005 %/mA PSRR VIN > VOUT + 0.5V, C2 = 10μF, VIN(AC) = 100mV, f = 1MHz 48 dB EN Input High Voltage 1.3 V EN Input Low Voltage 0.8 V EN Input Bias Current V EN = 1.2V –1 +1 μA Thermal Protection 155 °C Thermal Protection Hysteresis 30 °C GND Current I LOAD = 500mA 110 150 μA PIN FUNCTIONS Pin # Name Description 1 IN Power Source Input. Bypass IN to GND with a 1µF or greater capacitor. 2 BIAS Bias Voltage. Bypass to GND with a 1 μF capacitor (or greater) 3, 6 NC No Connect. 4 GND Ground. 5 EN Enable Input. Drive EN high to turn on the MP2005, drive EN low to turn it off. For automatic startup, connect EN to Bias. 7 FB Feedback Input. Connect a resistive voltage divider from OUT to FB to set the output voltage. OUT feedback threshold is 0.5V. 8 OUT Regulator Output. OUT is the output of the linear regulator. Bypass OUT to GND with a 1µF or greater capacitor.

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 4 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS C1=C3=2.2uF, C2=4.7uF, VEN=VBIAS=3.6V, TA=25ºC, unless otherwise noted 1.000 1.001 1.002 1.003 1.004 1.005 200 400 800 1000600 0 200 400 800 1000 600 0 200 400 800 1000 600 LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA) Load Regulation Load Regulation Load Regulation 3.0 4.23.6 3.20 3.25 3.30 3.35 3.40 5.44.8 6.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V ) INPUT VOLTAGE (V) Line Regulation Line Regulation Line Regulation PSRR(dB) PSRR vs. VIN DROPOUT VOLTAGE (mV) PSRR (dB) 100 120 800200 1000400 600 0.1 1000 1 1000010 100 1.0 2.0 1.000 1.002 1.004 1.006 1.008 1.010 2.45 2.47 2.49 2.51 2.53 2.55 3.0 4.0 5.0 6.0 -10 2.1 2.2 2.3 2.4 2.6 2.5 1.2 LOAD CURRENT (mA) FREQUENCY (KHz) INPUT VOLTAGE (V) Voltage Dropout PSRR vs. Frequency VIN=2.5V VBIAS=4.5V VIN=1.5 V VOUT=1.2V IOUT=0.1A VIN=1.5 V VOUT=1.2V IOUT=0.1A f=1MHz VBIAS=3.5V IOUT=50mA IOUT=100mA VBIAS=4.5V IOUT=100mA IOUT=100mA VBIAS=5V 3.28 3.29 3.30 3.31 3.33 3.32 VBIAS=3.5 V VIN=3V VIN=2.5V VBIAS=4.5 V VIN=1.5V VIN=3.6V VBIAS=5 V

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 5 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) C1=C3=2.2uF, C2=4.7uF, VEN=VBIAS=3.6V, TA=25ºC, unless otherwise noted DROPOUT VOLTAGE (mV) -40 FEEDBACK VOLTAGE (mV) 500 501 502 503 504 505 OUTPUT VOLTAGE (mV) 1.200 1.202 1.204 1.206 1.208 1.210 60-15 85 10 35 -40 60 -15 85 10 35 -40 60 -15 85 10 35 Dropout Voltage vs. Temperature Feedback Voltage vs. Temperature Output Voltage vs. Temperature VOUT=1.2V IOUT=0.3A VOUT=1.2V VIN=1.5V IOUT=0.3A VIN=1.0V IOUT=1mA 10 100 1000 10000 100000 OUTPUT NOISE (nV/ Hz )200 400 600 800 1000 1200 FREQUENCY (Hz) Output Noise vs. Frequency VOUT=3.3V VIN=VBIAS=5.4V IOUT=10mA

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 6 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS (continued) C1=C3=2.2uF, C2=4.7uF, VEN=VBIAS=3.6V, VIN=3.6V, TA=25ºC, unless otherwise noted

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 7 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. BLOCK DIAGRAM REFERENCE BIAS EN GND IN OUT FB 0.5V FILTER AND SOFT-START OCP Figure 1—Block Diagram of Super Low Dropout Regulator

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 8 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved.

APPLICATION INFORMATION

Setting the Output Voltage The MP2005 has an adjustable output voltage, set by using a resistive voltage divider from the output voltage to FB pin. The voltage divider divides the output voltage down to the feedback voltage by the ratio: 2R1R 2RVV OUTFB += Where V FB is the feedback threshold voltage (VFB = 0.5V), and VOUT is the output voltage. Thus the output voltage is: 2R1R5.0VOUT +×= R2 can be as high as 100kΩ, but a typical value is 10kΩ. Using that value, R1 is determined by: ⎛ −×= FB FBOUT V VV2R1R For example, for a 1.8V output voltage, R2 is 10kΩ, and R1 is 26k Ω. You can select a standard 26kΩ (±1%) resistor for R1. The following table lists the selected R1 for various output voltages. Table 1— Adjustable Output Voltages R1 Values VOUT (V) R1 (k Ω) R2 (k Ω) 1.25 15 1.5 20 1.8 26 2 30 2.5 40 2.8 46 3 50 3.3 56 4 70 Bias Input The bias input is designed for low drop application. The bias pin must be at least 2.7V, and at least 1.5V higher than the output. If V IN supply voltage meets these requirements, the bias pin can be tied to VIN. Feed Forward Capacitor For stability, it needs a 10nF capacitor parallel with R1. The ceramic type capacitor, will provide the best performance.

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR MP2005 Rev. 0.92 www.MonolithicPower.com 9 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. PCB Layout Guide PCB layout is very important to achieve good regulation, ripple rejection, transient response and thermal performance. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take Figure 2 for reference. 1) Input and output bypass ceramic capacitors are suggested to be put close to the IN Pin and OUT Pin respectively. 2) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 3) Connect IN, OUT and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. C1 C2C3 R3 R1 VIN VOUT VBIAS EN Top Layer Bottom Layer Figure 2—PCB Layout

MP2005 – 800mA, HIGH PSRR,ULDO LINEAR REGULATOR NOTICE: The information in this document is subject to change wi thout notice. Please contact M PS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights ar e not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2005 Rev. 0.92 www.MonolithicPower.com 10 5/5/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved.

PACKAGE INFORMATION

QFN8 (2mm x 3mm)