MP2004 MPS | Alldatasheet

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Dual, Low Noise, High PSRR 200mA Linear Regulator MP2004 Rev. 0.92 www.MonolithicPower.com 1 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. The Future of Analog IC Technology

DESCRIPTION

The MP2004 is a dual-channel, low noise, low dropout and high PSRR linear regulator. The output voltage of MP2004 ranges from 1.2V to 5V and 1% accuracy by operating from a +2.5V to +6.0V input. The MP2004 can supply up to 200mA of load current at each channel. The MP2004 uses an internal PMOS as the pass element, which consumes 114 μA supply current (both LDOs on) at no load condition. The EN1 and EN2 pins control each output respectively. When both channels shutdown simultaneously, the chip will be turned off and consume nearly zero operation current which is suitable for battery-power devices. The MP2004 features current limiting and over temperature protection. It is available in a small 6-pin TSOT23 package.

FEATURES

  • Two LDOs in a TSOT23-6 Package
  • Up to 200mA Output Current (Per Channel
  • Two Enable Pins Control Each Output
  • 69dB PSRR (100Hz)
  • 95 μVRMS Low Noise Output
  • 110mV Dropout at 100mA Load
  • Very Fast Transient Responses with Small Output Capacitor
  • Current Limiting and Thermal Protection

APPLICATIONS

  • Cellular Phones
  • Laptop PCs
  • Hand-held Equipment
  • Netbook Computing “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION EN2 EN1 OUT2 OUT1 IN GND OUT2 OUT1 EN1 EN2 MP2004 CIN COUT2 COUT1 IN

MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR MP2004 Rev. 0.92 www.MonolithicPower.com 2 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. ORDERING INFORMATION* Part Number V OUT1 VOUT2 Package Temperature Top Marking MP2004DJ-JG-LF-Z 2.5V 1.8V 2B MP2004DJ-ZS-LF-Z 5.0V 3.3V 2L MP2004DJ-PN-LF-Z 3.0V 2.85V 3L MP2004DJ-DD-LF-Z 1.85V 1.85V 4L MP2004DJ-SJ-LF-Z 3.3V 2.5V 5L MP2004DJ-MG-LF-Z 2.8V 1.8V TSOT23-6 -40°C to +85°C * Other output voltage versions between 1.2V and 5.0V are available in 100mV increments. Contact factory for availability. ORDERING GUIDE MP2004DJ- -LF-Z VOUT2 VOUT1 Package Type J: TSOT23-6 For RoHS Compliant Packaging, add suffix - LF (e.g. MP2004DJ- -LF); For Tape and Reel, add suffix -Z (e.g. MP2004DJ- - LF-Z). OUTPUT VOLTAGE SELECTOR GUIDE* Code V OUT Code V OUT C 1.2 T 2.65 B 1.3 L 2.7 F 1.5 M 2.8 W 1.6 N 2.85 G 1.8 V 2.9 D 1.85 P 3.0 Y 1.9 Q 3.1 H 2.0 X 3.15 E 2.1 R 3.2 J 2.5 S 3.3 K 2.6 Z 5.0 * Code in Bold are standard versions. For other output voltages between 1.2V and 5.0V contact factory for availability. Minimum order quantity on non-standard versions is 25,000 units. PACKAGE REFERENCE OUT1 TOP VIEW IN EN1 EN2GND 123 456 OUT2

MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR MP2004 Rev. 0.92 www.MonolithicPower.com 3 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. ABSOLUTE MAXIMUM RATINGS (1) Continuous Power Dissipation (TA = +25°C)(2) Operation Temperature Range ... -40°C to 85°C Recommended Operating Conditions (3) Junction Temperature Range . –40°C to +125°C Thermal Resistance (4) θJA θJC Notes: 1) Exceeding these ratings may cause permanent damage to the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature T J(MAX), the junction-to- ambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)- TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside its operating conditions. 4) Measured on JESD51-7 4-layer board.

MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR MP2004 Rev. 0.92 www.MonolithicPower.com 4 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS

VIN=3.6V, VOUT1=2.5V, VOUT2=1.8V, CIN=COUT1=COUT2=2.2uF, EN1=EN2=VIN, Typical Value at TA=25°C for each LDO unless otherwise noted. Notes: 5) Load Regulation= 100(%)V VV OUT(NOM) ]OUT[I]OUT[I OUT(MIN)OUT(MAX) 6) Dropout Voltage is defined as the input to output different ial when the output voltage drops 100mV below its nominal value. 7) Line Regulation= )100(%/VV]V[V VV OUT(NOM)IN(MIN)IN(MAX) ]OUT[V]OUT[V IN(MIN)IN(MAX) ××− PIN FUNCTIONS Pin # Name Description

1 VOUT2 Channel 2 Output Voltage

2 GND Common Ground

3 EN2 Channel 2 Enable (Active High). Do Not Float This Pin. 4 EN1 Channel 1 Enable (Active High). Do Not Float This Pin.

5 VIN Supply Input Pin

6 VOUT1 Channel 1 Output Voltage

Parameter Symbol Condition Min Typ Max Units Output Voltage Accuracy (Load regulation)(5) ΔVOUT I LOAD = 1mA to 200mA -1 +1 % Maximum Output Current I MAX Continuous 200 mA Current Limit I LIM RLoad=1Ω 450 mA Quiescent Current I Q No Load 114 uA IOUT1 = 100mA 110 mV Dropout Voltage (6) V DROP IOUT1 = 200mA 250 mV Line Regulation(7) ∆VLINE VIN =(VOUT+0.4V or 2.5V) to 6V, IOUT=1mA -0.05 +0.05 %/V EN Input High Threshold V IH V IN = 2.5V to 6.0V 1.6 V EN Input Low Threshold V IL V IN = 2.5V to 6.0V 0.45 V EN Input Bias Current I SD EN= V IN =6.5V 300 nA Shutdown Supply Current I GSD EN1 = EN2 = GND 0.03 1 uA Thermal Shutdown Temperature T SD 140 °C Thermal Shutdown Hysteresis ΔTSD 10 °C Output Voltage Noise 10Hz to 100kHz, COUT=2.2μF, ILOAD=1mA 95 μVRMS Output PSRR 100Hz, COUT = 2.2μF, ILOAD = 100mA 69 dB

MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR MP2004 Rev. 0.92 www.MonolithicPower.com 5 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. TYPICAL PERFORMANCE CHARACTERISTICS VIN=3.6V, VOUT1=2.5V, VOUT2=1.8V, CIN=COUT1=COUT2=2.2uF, EN1=EN2=VIN, Typical Value at TA=25°C for Both Channel Enabled. 100 120 100 1000 10000 100000 1000000 FREQUENCY(Hz) Channel-to-Channel Isolation vs. Frequency -40 -20 0 20 40 60 85 Quiescent Current vs. Temperature 200 150 100 Dropout Voltage vs. Temperature -40 -20 0 20 40 60 85 Out Voltage Accuracy vs. Temperature 10 100 1000 10000 100000 1000000 FREQUENCY(Hz) Power Supply Rejection Ratio vs. Frequency VOUT 10mV/div VIN 1V/div VOUT 10mV/div ILOAD 50mA/div VOUT 1V/div VEN 5V/div 200 220 240 260 280 300 -40 -20 0 20 40 60 85 ILOAD=200mA -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25

MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR MP2004 Rev. 0.92 www.MonolithicPower.com 6 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. BLOCK DIAGRAM Figure1—Functional Block Diagram OPERATION The MP2004 integrates two low noise, low dropout, low quiescent current and high PSRR linear regulators. It is intended for use in devices that require very low voltage, low quiescent current power such as wireless LAN, battery- powered equipment and hand-held equipment. The MP2004 uses internal PMOSs as the pass elements and features internal thermal shutdown and an internal current limit circuit. Dropout Voltage Dropout voltage is the minimum input to output differential voltage required for the regulator to maintain an output voltage within 100mV of its nominal value. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage of MP2004 is very low. Shutdown The MP2004 can be switched ON or OFF by a logic input at the EN pin. A high voltage at this pin will turn the device on. When the EN pin is low, the regulator output is off. The EN pin should be tied to VIN to keep the regulator output always on if the application does not require the shutdown feature. Do not float the EN pin. Current Limit The MP2004 includes two independent current limit structures which monitor and control each PMOS’s gate voltage limiting the guaranteed maximum output current to 200mA. Thermal Protection Thermal protection turns off the PMOS when the junction temperature exceeds +140ºC, allowing the IC to cool. When the IC’s junction temperature drops by 10ºC, the PMOS will be turned on again. Thermal protection limits total power dissipation in the MP2004. For reliable operation, junction temperature should be limited to 125 ºC maximum. Load-Transient Considerations The output response of load-transient consists of a DC shift and transient response. Because of the excellent load regulation of MP2004, the DC shift is very small. The output voltage transient depends on the output capacitor’s value and the ESR. Increasing the capacitance and decreasing the ESR will improve the transient response. Typical output voltage transient spike of MP2004 for a step change in the load current from 0mA to 80mA is tens mV.

MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR MP2004 Rev. 0.92 www.MonolithicPower.com 8 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved. PCB Layout Guide PCB layout is very important to achieve good regulation, ripple rejection, transient response and thermal performance. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take Figure 5 for reference. 1) Input and output bypass ceramic capacitors are suggested to be put close to the IN Pin and OUT Pin respectively. 2) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 3) Connect IN, OUT and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. IN R1 R2 EN1 EN2 OUT1 OUT2 GND OUT1 MP2004 COUT2 COUT1 IN EN1 EN2 CIN OUT2 OUT2 EN2 GND EN1 IN

6 OUT1

Figure 5—PCB Layout

MP2004-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR NOTICE: The information in this document is subject to change wi thout notice. Users should warra nt and guarantee that third party Intellectual Property rights are not infringed upon w hen integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2004 Rev. 0.92 www.MonolithicPower.com 9 4/6/2010 MPS Proprietary Information. Unaut horized Photocopy and Duplication Prohibited. © 2010 MPS. All Rights Reserved.

PACKAGE INFORMATION

0.30 0.50 SEATING PLANE

0.95 BSC

0.84 0.90 1.00 MAX 0.00 0.10 TOP VIEW FRONT VIEW SIDE VIEW RECOMMENDED LAND PATTERN 2.80 3.00 1.50 1.70 2.60 3.00 1 3 0.09 0.20 NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-193, VARIATION AB. 6) DRAWING IS NOT TO SCALE. 7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK) 0.30 0.50 0o-8o

0.25 BSC

2.60 TYP 1.20 TYP 0.95 BSC 0.60 TYP SEE DETAIL "A" DETAIL “A” AAAAPIN 1 See Note 7 EXAMPLE TOP MARK