MMSF7N03ZR2

MMSF7N03Z ONSEMI | Alldatasheet

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Publication Order Number: MMSF7N03Z/D © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 2 MMSF7N03Z Power MOSFET

7 Amps, 30 Volts

N−Channel SO−8 EZFETs/C0116 are an advanced series of Power MOSFETs which contain monolithic back−to−back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low R DS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain−to−source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc −dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives.

• Zener Protected Gates Provide Electrostatic Discharge Protection
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Designed to withstand 200V Machine Model and 2000V Human Body Model
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Mounting Information for SO−8 Package Provided

7 AMPERES

30 VOLTS

RDS(on) = 30 m/C0087 Device Package Shipping

ORDERING INFORMATION

MMSF7N03ZR2 SO −8 2500 Tape & Reel SO−8 CASE 751 STYLE 12 http://onsemi.com N−Channel LYWW MARKING DIAGRAM D S G 7N03Z 7N03Z = Device Code L = Location Code Y = Year WW = Work Week Source 1 Top View Source Source Gate Drain Drain Drain Drain PIN ASSIGNMENT

http://onsemi.com MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 30 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc Gate−to−Source Voltage − Continuous VGS ± 15 Vdc Drain Current − Continuous @ TA = 25°C (Note 1) − Continuous @ TA = 70°C (Note 1) − Pulsed Drain Current (Note 3) ID ID IDM 7.5 5.6 Adc Apk Total Power Dissipation @ TA = 25°C (Note 1) Linear Derating Factor (Note 1) PD 2.5 Watts mW/°C Total Power Dissipation @ TA = 25°C (Note 2) Linear Derating Factor (Note 2) PD 1.6 Watts mW/°C Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 Ω) EAS 450 mJ Thermal Resistance − Junction to Ambient (Note 1) − Junction to Ambient (Note 2) RθJA 50 °C/W 1. When mounted on 1 ″ square FR−4 or G−10 board (VGS = 10 V, @ 10 Seconds) 2. When mounted on 1 ″ square FR−4 or G−10 board (VGS = 10 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature.

http://onsemi.com ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Cpk ≥ 2.0) (Notes 4 & 6) (VGS = 0 Vdc, ID = 250 μAdc) Temperature Coefficient (Positive) V(BR)DSS Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 0.03 0.15 2.0 μAdc Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0) IGSS − 1.3 5.0 μAdc ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (Cpk ≥ 2.0) (Notes 4 & 6) (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) VGS(th) 1.0 2.0 5.5 3.0 Vdc mV/°C Static Drain−to−Source On−Resistance (Cpk ≥ 2.0) (Notes 4 & 6) (VGS = 10 Vdc, ID = 7.5 Adc) (VGS = 4.5 Vdc, ID = 3.8 Adc) RDS(on) mΩ Forward Transconductance (VDS = 3.0 Vdc, ID = 3.8 Adc) (Note 4) gFS 4.0 9.5 − Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 750 1500 pF Output Capacitance Coss − 340 680 Transfer Capacitance Crss − 45 90 SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time (VDS = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc, RG = 6 Ω) (Note 4) td(on) − 40 80 ns Rise Time tr − 90 180 Turn−Off Delay Time td(off) − 470 940 Fall Time tf − 170 340 Turn−On Delay Time (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc, RG = 6 Ω) (Note 4) td(on) − 120 240 ns Rise Time tr − 350 700 Turn−Off Delay Time td(off) − 430 860 Fall Time tf − 140 280 Gate Charge (VDS = 24 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (Note 4) QT − 34 48 nC Q1 − 3.5 − Q2 − 9.5 − Q3 − 6.5 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 4) (IS = 7.5 Adc, VGS = 0 Vdc) (Note 4) (IS = 7.5 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 0.83 0.67 1.6 Vdc Reverse Recovery Time (IS = 7.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) (Note 4) trr − 110 − ns ta − 22 − tb − 90 − Reverse Recovery Storage Charge QRR − 0.17 − μC 4. Pulse Test: Pulse Width ≤300 μs, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Reflects typical values. Cpk = Max limit − Typ 3 x SIGMA

be charged by current from the generator. and Q2 and VGSP are read from the gate charge curve. on−state when calculating td(off). is difficult to measure and, consequently, is not specified. maintain a value of unity regardless of the switching speed. however, snubbing reduces switching losses. Figure 7. Capacitance Variation

http://onsemi.com INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self −align when subjected to a solder reflow process. mm inches 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 SO−8 POWER DISSIPATION The power dissipation of the SO −8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T J(max), the maximum rated junction temperature of the die, R θJA, the thermal resistance from the device junction to ambient; and the operating temperature, T A. Using the values provided on the data sheet for the SO −8 package, P D can be calculated as follows: PD = TJ(max) − TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature T A of 25 °C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. PD = 150°C − 25°C 50°C/W = 2.5 Watts The 50 °C/W for the SO −8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad /C0116. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

• Always preheat the device.
• The delta temperature between the preheat and soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed 260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during cooling. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

efficiently, then distributes this energy to the components. be up to 30 degrees cooler than the adjacent solder joints.

40 TO 80 SECONDS

Figure 16. Typical Solder Heating Profile

http://onsemi.com PACKAGE DIMENSIONS SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 SO−8 CASE 751−07 ISSUE V STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MMSF7N03Z/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC). Thermal Clad is a registered trademark of the Bergquist Company.