MMSF3350 ONSEMI | Alldatasheet

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© Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 3

1 Publication Order Number:

WaveFET™ HDTMOS™ Single N−Channel Field Effect Transistor Power Surface Mount Products WaveFET devices are an advanced series of power MOSFETs which utilize ON Semiconductor’s latest MOSFET technology process to achieve the lowest possible on−resistance per silicon area. They are capable of withstanding high energy in the avalanche and commutation modes and the drain −to−source diode has a very low reverse recovery time. WaveFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc −dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.

  • Characterized Over a Wide Range of Power Ratings
  • Ultralow RDS(on) Provides Higher Efficiency and Extends Battery Life in Portable Applications
  • Logic Level Gate Drive − Can Be Driven by Logic ICs
  • Diode Is Characterized for Use In Bridge Circuits
  • Diode Exhibits High Speed, With Soft Recovery
  • IDSS Specified at Elevated Temperature
  • Avalanche Energy Specified
  • Miniature SO−8 Surface Mount Package − Saves Board Space http://onsemi.com SO−8 CASE 751 Style 12 SINGLE TMOS POWER MOSFET

30 VOLTS

RDS(on) = 11 m/C0087 MARKING DIAGRAM D G S XXXXXX ALYW XXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week

http://onsemi.com MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 30 Vdc Drain−to−Gate Voltage VDGR 30 Vdc Gate−to−Source Voltage VGS ±20 Vdc Gate−to−Source Operating Voltage VGS ±16 Vdc Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, L = 20 mH, IL(pk) = 10 A, VDS = 30 Vdc) EAS 1000 mJ POWER RATINGS (TJ = 25°C unless otherwise specified) Parameter Symbol Value Unit Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tp ≤ 10 /C0109s) Mounted on 1 inch square FR−4 or G10 board VGS = 10 Vdc t ≤ 10 seconds ID ID IDM 9.2 Adc Adc Adc Continuous Source Current (Diode Conduction) IS 3.6 Adc Total Power Dissipation @ TA = 25°C Linear Derating Factor PD 2.7 22.2 Watts mW/°C Thermal Resistance − Junction−to−Ambient R/C0113JA 46 °C/W Parameter Symbol Value Unit Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tp ≤ 10 /C0109s) Mounted on 1 inch square FR−4 or G10 board VGS = 10 Vdc Steady State ID ID IDM 9.4 6.7 Adc Adc Adc Continuous Source Current (Diode Conduction) IS 2.0 Adc Total Power Dissipation @ TA = 25°C Linear Derating Factor PD 1.5 11.8 Watts mW/°C Thermal Resistance − Junction−to−Ambient R/C0113JA 85 °C/W Parameter Symbol Value Unit Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tp ≤ 10 /C0109s) Mounted on minimum recommended FR−4 or G10 board VGS = 10 Vdc t ≤ 10 seconds ID ID IDM 7.4 Adc Adc Adc Continuous Source Current (Diode Conduction) IS 2.4 Adc Total Power Dissipation @ TA = 25°C Linear Derating Factor PD 1.8 14.3 Watts mW/°C Thermal Resistance − Junction−to−Ambient R/C0113JA 70 °C/W Parameter Symbol Value Unit Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tp ≤ 10 /C0109s) Mounted on minimum recommended FR−4 or G10 board VGS = 10 Vdc Steady State ID ID IDM 7.4 5.2 Adc Adc Adc Continuous Source Current (Diode Conduction) IS 1.2 Adc Total Power Dissipation @ TA = 25°C Linear Derating Factor PD 0.9 7.1 Watts mW/°C Thermal Resistance − Junction−to−Ambient R/C0113JA 140 °C/W

http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 /C0109Adc) Temperature Coefficient (Positive) V(BR)DSS Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 0.003 0.4 1.0 /C0109Adc Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS − 2.0 100 nAdc ON CHARACTERISTICS(1) Gate Threshold Voltage (VDS = VGS, ID = 250 /C0109Adc) Threshold Temperature Coefficient (Negative) VGS(th) 1.0 2.0 4.6 Vdc mV/°C Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) RDS(on) 9.4 14.4 m/C0087 Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) gFS 12 17 − Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 1680 − pF Output Capacitance Coss − 540 − Transfer Capacitance Crss − 185 − SWITCHING CHARACTERISTICS(2) Turn−On Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 4.5 Vdc, RG = 6.0 /C0087) td(on) − 21 40 ns Rise Time tr − 50 90 Turn−Off Delay Time td(off) − 42 80 Fall Time tf − 44 80 Turn−On Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, RG = 6.0 /C0087) td(on) − 12 20 ns Rise Time tr − 15 30 Turn−Off Delay Time td(off) − 60 100 Fall Time tf − 44 80 Gate Charge (VDS = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) QT − 46 60 nC Q1 − 4.5 − Q2 − 12.8 − Q3 − 9.8 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (1) (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 0.76 0.58 1.0 Vdc Reverse Recovery Time (IS = 3.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A//C0109s) trr − 41 − ns ta − 21 − tb − 20 − Reverse Recovery Stored Charge QRR − 0.049 − /C0109C 1. Pulse Test: Pulse Width ≤300 /C0109s, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperatures.

be charged by current from the generator. and Q2 and VGSP are read from the gate charge curve. on−state when calculating td(off). is difficult to measure and, consequently, is not specified. maintain a value of unity regardless of the switching speed. however, snubbing reduces switching losses. Figure 7. Capacitance Variation

Figure 14. Thermal Response − Various Duty Cycles Figure 15. Thermal Response − Various Figure 16. Single Pulse Power Figure 17. Diode Reverse Recovery Waveform OZ. CU 0.06, THICK SINGLE SIDED).

1 INCH PAD,

http://onsemi.com INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self−align when subjected to a solder reflow process. 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 SO−8 POWER DISSIPATION The power dissipation of the SO −8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T J(max), the maximum rated junction temperature of the die, R/C0113JA, the thermal resistance from the device junction to ambient; and the operating temperature, T A. Using the values provided on the data sheet for the SO−8 package, PD can be calculated as follows: PD = TJ(max) − TA R/C0113JA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.7 Watts. PD = 150°C − 25°C 46°C/W = 2.7 Watts The 46 °C/W for the SO −8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.7 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad ™. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

  • Always preheat the device.
  • The delta temperature between the preheat and soldering should be 100°C or less.*
  • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
  • The soldering temperature and time shall not exceed 260°C for more than 10 seconds.
  • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.
  • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
  • Mechanical stress or shock should not be applied during cooling. *Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

make up a heating “profile” for that particular circuit board. soldering a surface mount device to a printed circuit board. profiles are based on a high density and a low density board. efficiently, then distributes this energy to the components. be up to 30 degrees cooler than the adjacent solder joints.

40 TO 80 SECONDS

Figure 18. Typical Solder Heating Profile

http://onsemi.com PACKAGE DIMENSIONS SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDAARD IS 751−07 A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN SOIC−8 NB CASE 751−07 ISSUE AA ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MMSF3350/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative WaveFET is a trademarks of Semiconductor Components Industries, LLC (SCILLC). HDTMOS is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC). Thermal Clad is a registered trademark of the Bergquist Company.