MMPF0200F0AEP

MMPF0200 NXP | Alldatasheet

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Document Number: MMPF0200 Rev. 6.0, 8/2016 NXP Semiconductors Data Sheet: Advance Information * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © 2016 NXP B.V. 12 channel configurable power management integrated circuit The PF0200 Power Management Integrated Circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With up to four buck converters, one boost regulator, six linear regulators, RTC supply, and coin-cell charger, the PF0200 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip One Time Programmable (OTP) memory, the PF0200 is available in pre- programmed standard versions, or non-programmed to support custom programming. The PF0200 is especially suited to the i.MX 6SoloLite, i.MX 6Solo and i.MX 6DualLite versions of the i.MX 6 family of devices and is supported by full system level reference designs, and pre-programmed versions of the device. This device is powered by SMARTMOS technology. Features:

• Three to four buck converters, depending on configuration
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output volt age, sequence, and timing
• OTP (One Time Programmable) me mory for device configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event detection
• I 2C control
• Individually programmable ON, OFF, and Standby modes

Figure 1. Simplified application diagram

56 QFN 8X8

Applications

• T a b l e t s
• I P T V
• Industrial Control
• Medical monitoring
• Home automation/ alarm/ energy management ES SUFFIX (WF-TYPE)

i.MX6X I2C Communication I2C Communication PF0200 Control Signals Parallel control/GPIOS LICELL Charger COINCELL Main Supply VGEN1 VGEN2 VGEN4 VGEN6 SWBST SW3A/B SW1A/B SW2 GPS MIPI uPCIe SATA - FLASH NAND - NOR Interfaces Processor Core Voltages Camera VREFDDR DDR Memory DDR MEMORY INTERFACE SD-MMC/ NAND Mem. SATA HDD WAM GPS MIPI HDMI LDVS Display USB Ethernet CAN

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1 Orderable parts

the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 8. Contact your NXP representative for more details. Table 1. Orderable part variations

1. For Tape and Reel add an R2 suffix to the part number.
2. For programming details see Table 8.

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2 Internal block diagram

Figure 2. PF0200 simplified internal block diagram

3 Pin connections

3.1 Pinout diagram

Figure 3. Pinout diagram

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3.2 Pin definitions

Table 2. PF0200 pin definitions Analog Reserved pin. Connect to GND in application. current path and terminate at the output capacitance. 0.1 μF decoupling capacitor as close to the pin as possible. 0.1 μF decoupling capacitor as close to the pin as possible. 12 RSVD2 - - Reserved Reserved for pin to pin compatibility. Connect this pin to VIN. through a board ground plane. 16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor. 18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor. path and terminate at the output capacitance. 26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor.

28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor. path and terminate at the output capacitance. 0.1 μF decoupling capacitor as close to the pin as possible. 0.1 μF decoupling capacitor as close to the pin as possible. path and terminate at the output capacitance. 39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor.

44 SWBSTFB

this trace away from other noisy traces and planes. 0.1 μF decoupling capacitor as close to the pin as possible.

47 VDDOTP I 10 V (3) Digital &

48 GNDREF GND - GND Ground reference for the main band gap regulator. Table 2. PF0200 pin definitions (continued)

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and external ground planes through vias to allow effective thermal dissipation.

1. 10 V Maximum voltage rating during OTP fuse prog ramming. 7.5 V Maximum DC voltage rated otherwise.
2. Unused switching regulators should be c onnected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected

to VIN with a 0.1 μF bypass capacitor.

4 General product characteristics

4.1 Absolute maximum ratings

Table 3. Absolute maximum ratings to the device. The detailed maximum voltage rating per pin can be found in the pin list section.

1. ESD testing is performed in accordance with t he Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model

(CDM), Robotic (CZAP = 4.0 pF).

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4.2 Thermal characteristics

4.2.1 Power dissipation

such that this protection is not tripped under normal conditions. Table 4. Thermal ratings

1. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 5 for

thermal protection features.

1. Pin soldering temperature limit is for 10 seconds maximum du ration. Not designed for immersion soldering. Exceeding these limits may cause a

malfunction or permanent damage to the device.

1. NXP’s Package Reflow capability meets Pb-free requirements fo r JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.

1. Junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

1. The Board uses the JEDEC specifications for th ermal testing (and simulation) JESD51-7 and JESD51-5.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
5. Thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature per JEDEC JESD51-
6. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

4.3 Electrical characteristics

4.3.1 General specifications

Table 5. Thermal protection thresholds Table 6. General PMIC static characteristics component values and full load current range, unless otherwise noted.

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4.3.2 Current consumption

Table 7. Current consumption summary LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.

1. Refer to Figure 4 for Coin Cell mode characteristics over temperature.
2. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
3. For PFM operation, headroom should be 300 mV or greater.
4. Additional current may be drawn in the coin cell mode when R ESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.

RESETBMCU path when VIN is removed. Pull-up RESETBMCU to a rail that is off in the coin cell mode, for non-i.MX 6 applications.

1. From -40 to 85 °C, Applicable to Consumer and Extended Industrial part numbers
2. From -40 to 105 °C, Applicable only to Extended Industrial parts

Figure 4. Coin cell mode current versus temperature

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5 General description

The PF0200 is the Power Management Integrated Circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application processors.

5.1 Features

This section summarizes the PF0200 features.

• Input voltage range to PMIC: 2.8 - 4.5 V
• Buck regulators
• Three to four channel configurable
• SW1A/B, 2.5 A; 0.3 to 1.875 V
• S W 2 , 1 . 5 A; 0.4 to 3.3 V
• SW3A/B, 2.5 A (single phase); 0.4 to 3.3 V
• S W 3 A , 1 . 2 5 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable soft start
• Programmable PWM switching frequency
• Programmable OCP with fault interrupt
• Boost regulator
• SWBST, 5.0 to 5.15 V, 0.6 A, OTG support
• Modes: PFM and Auto
• OCP fault interrupt
• L D O s
• Six user programable LDO
• VGEN1, 0.80 to 1.55 V, 100 mA
• VGEN2, 0.80 to 1.55 V, 250 mA
• VGEN3, 1.8 to 3.3 V, 100 mA
• VGEN4, 1.8 to 3.3 V, 350 mA
• VGEN5, 1.8 to 3.3 V, 100 mA
• VGEN6, 1.8 to 3.3 V, 200 mA
• Soft start
• LDO/Switch supply
• DDR memory reference voltage
• VREFDDR, 0.6 to 0.9 V, 10 mA
• 1 6 MHz internal master clock
• OTP(One time programmable) me mory for device configuration
• User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
• I 2C interface
• User programmable Standby, Sleep, and Off modes

5.2 Functional block diagram

Figure 5. Functional block diagram

5.3 Functional description

5.3.1 Power generation

switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices. for the processor cores and/or other circuitry. powered from VIN, or from a coin cell.

5.3.2 Control logic

configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration.

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5.3.2.1 Interface signals

PWRON is an input signal to the IC that generates a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG bit. Refer to section Turn on events for more details. STANDBY STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section Standby mode for more details. Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide VSNVS, or the PMIC will not reliably enter and exit the STANDBY mode. RESETBMCU RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0200 is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described above will be repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on Extended page 1 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses. SDWNB SDWNB is an open-drain, active low output that notifies the processor of an imminent PMIC shutdown. It is asserted low for one 32 kHz clock cycle before powering down and is then de-asserted in the OFF state. INTB INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is de- asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.

6 Functional block requirements and behaviors

6.1 Start-up

OTP configuration is enabled by connecting VDDOTP to GND. I2C port for prototyping and programming. Once programmed, the NP device will startup with the customer programmed configuration.

6.1.1 Device start-up configuration

Table 8. Start-up configuration

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Figure 6. Default start-up sequence Table 8. Start-up configuration (continued) *VSNVS will start from 1.0 V if LICELL is valid before VIN.

6.1.2 One time programmability (OTP)

algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. The parameters that can be configured by OTP are listed below.

• General: I 2C slave address, PWRON pin configuration, start-up sequence and timing
• Buck regulators: Output voltage, single phase or independent mode configuration, switching frequency, and soft start ramp rate
• Boost regulator and LDOs: Output voltage NOTE: When prototyping or programming fuses, the user must ensure that register settings are consistent with the hardware configuration. This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it will be gated by the buck regulator in the start-up sequence.

6.1.2.1 Start-up sequence and timing

to thirty-one in the start-up sequence. The all zeros code indicates that a regulator is not part of the start-up sequence and will remain off. will terminate at the last programmed regulator. Table 9. Default start-up sequence timing

1. Assumes LICELL voltage is valid before VIN is applied. If LICE LL is not valid before VIN is applied then VSNVS turn-on delay may extend to a
2. Depends on the external signal driving PWRON.
3. Rise time is a function of slew rate of regulators and nominal voltage selected.

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6.1.2.2 PWRON pin configuration

1). As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into Sleep mode. low for greater than or equal to 4.0 seconds, the part will turn off or enter Sleep mode.

6.1.2.3 I 2C address configuration

The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts. (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 13. Table 10. Start-up sequence

00000 Off

00001 SEQ_CLK_SPEED[1:0] * 1

00010 SEQ_CLK_SPEED[1:0] * 2

11111 SEQ_CLK_SPEED[1:0] * 31

Table 11. Start-up sequence clock speed Table 12. PWRON configuration

0 PWRON pin HIGH = ON

1 PWRON pin pulled LOW momentarily = ON

Table 13. I2C address configuration

6.1.2.4 Soft start ramp rate

The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in Dynamic voltage scaling.

6.1.3 OTP prototyping

• If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
• I f V D D O T P = 0 . 0 V, TBB_POR = 0 and FUSE_POR_XOR = 1, the values are loaded from the fuses. It is required to set all the FUSE_PORx bits to load the fuses.
• I f V D D O T P = 0 . 0 V, TBB_POR = 0 and FUSE_POR_XOR = 0, the TBBOTP registers remain initialized at zero. The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP registers maintained and not loaded from a different source. The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 1 and there is a valid turn-on event.

6.1.4 Reading OTP fuses

6.1.5 Programming OTP fuses

six fuses, each that can be programmed. Table 13. I2C address configuration (continued)

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• VIN < UVDET
• All regulators are in SLEEP mode
• All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
• PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 25 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.

6.2.1 Clock adjustment

changing the factory trim values of the 16MHz clock, the user may add an offset as small as ±3.0% of the nominal frequency.

6.3 Bias and references block description

6.3.1 Internal core voltage references

valid supply and/or valid coin cell. Table 16 shows the main characteristics of the core circuitry. Table 14. Source of start-up sequence Table 15. 16 MHz clock specifications component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

1. 2.0 MHz clock is derived from the 16 MHz clock.

6.3.1.1 External components

6.3.2 VREFDDR voltage reference

voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low-frequency pole. This divider then utilizes a voltage follower to drive the load. Figure 7. VREFDDR block diagram Table 16. Core voltages electrical specifications(28) component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted. Table 17. External components for core voltages

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6.3.2.1 VREFDDR control register

The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 18. Table 18. Register VREFDDCRTL - ADDR 0x6A Table 19. VREFDDR external components(29)

1. Use X5R or X7R capacitors.
2. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output.

Table 20. VREFDDR electrical characteristics 1.5 V, and 25 °C, unless otherwise noted.

6.4 Power generation

6.4.1 Modes of operation

diagram of the PF0200, along with the conditions to enter and exit from each state.

1. When VREFDDR is off there is a quiescent current of 1.5 μA typical.

Table 20. VREFDDR electrical characteristics (continued) 1.5 V, and 25 °C, unless otherwise noted.

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Figure 8. State diagram Coin Cell mode and the interrupt signal, INTB, is only active in Sleep, Standby, and ON states.

6.4.1.1 ON mode

The PF0200 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.

6.4.1.2 OFF mode

asserted, LOW, in this mode.

6.4.1.3 Standby mode

• Depending on STANDBY pin configuration, Stan dby is entered when the STANDBY pin is asserted. This is typically used for low- power mode of operation.
• When STANDBY is de-asserted, Standby mode is exited. PWRON = 0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) PWRON=1 & VIN > UVDET (PWRON_CFG =0) Or PWRON= 0 < 4.0 sec & VIN > UVDET (PWRON_CFG=1) ON PWRON = 0 Any SWxOMODE bits=1 (PWRON_CFG=0) Or PWRON=0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) PWRON=1 & VIN > UVDET (PWRON_CFG = 0) Or PWRON= 0 < 4.0 sec & VIN > UVDET (PWRON_CFG=1) PWRON = 0 All SWxOMODE bits= 0 (PWRON_CFG = 0) Or PWRON = 0 held >= 4.0 sec All SWxOMODE bits= 0 & PWRONRSTEN = 1 (PWRON_CFG = 1) OFF Sleep Coin Cell VIN < UVDET VIN > UVDET Thermal shudown Standby STANDBY asserted VIN < UVDET Thermal shutdown Thermal shutdown STANDBY de-asserted PWRON = 0 Any SWxOMODE bits=1 (PWRON_CFG=0) Or PWRON=0 held >= 4.0 sec Any SWxOMODE bits=1 & PWRONRSTEN = 1 (PWRON_CFG=1) PWRON = 0 All SWxOMODE bits= 0 (PWRON_CFG = 0) Or PWRON = 0 held >= 4.0 sec All SWxOMODE bits= 0 & PWRONRSTEN = 1 (PWRON_CFG = 1) VIN < UVDET VIN < UVDET

of going in and out of such deep sleep modes (DSM). referred to as active high throughout this document. STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event.

6.4.1.4 Sleep mode

• Depending on PWRON pin configuration, Sleep mode is enter ed when PWRON is de-asserted and SWxOMODE bit is set.
• To exit Sleep mode, assert the PWRON pin. In the Sleep mode, the regulator will use the set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 23 shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event.

Table 21. Standby Pin and polarity control

1. STANDBY = 0: System is not in Standby, STANDBY = 1: System is in Standby
2. The state of the STANDBY pin only has influence in On mode.
3. Bit 6 in Power Control Register (ADDR - 0x1B)

Table 22. STANDBY delay - initiated response

00 No Delay

01 One 32 k period (default)

10 Two 32 k periods

11 Three 32 k periods

1. Bits [5:4] in Power Control Register (ADDR - 0x1B)

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6.4.1.5 Coin cell mode

state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. system will be re-initialized with all I2C bits including those that reset on COINPORB, are restored to their default states.

6.4.2 State machine flow summary

Table 24 provides a summary matrix of the PF0200 flow diagram to show the conditions needed to transition from one state to another. Table 23. Regulator mode control

1. For sleep mode, an activated switching regulator, should use the off

SWxOFF[6:0] for SW2 and SW3A/B. Table 24. State machine flow summary

6.4.2.1 Turn on events

• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set.
• If PWRON_CFG = 1, V IN > UVDET and PWRON transitions from high to low, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set. The sense bit will show the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press. The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode.

6.4.2.2 Turn off events

1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.

Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine will transition to the Coin Cell mode. Table 25. PWRON hardware debounce bit settings

1. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.

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6.4.3 Power tree

by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR. system’s voltage and current requirements, therefore a proper input voltage should be selected for the regulators. Table 26. Power tree summary

1. Current rating per independent phase, when SW3A/B is set in single phase, current capability is up to

Table 27. UVDET threshold

Figure 9. PF0200 typical power map

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6.4.4 Buck regulators

Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.

6.4.4.1 Current limit

condition persists for more than 8.0 ms, a fault interrupt is generated.

6.4.4.2 General control

variation. Available switching modes for buck regulators are presented in Table 28. mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Table 29 summarizes the Buck regulator programmability for Normal and Standby modes. options are the same for Normal and Standby modes for each regulator. Table 28. Switching mode description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS In this mode, the regulator moves automatically betw een pulse skipping mode and PWM mode depending on load conditions. Table 29. Regulator mode control

0000 Off Off

0001 PWM Off

0010 Reserved Reserved

0011 PFM Off

0100 APS Off

0101 PWM PWM

0110 PWM APS

0111 Reserved Reserved

1000 APS APS

1001 Reserved Reserved

1010 Reserved Reserved

1011 Reserved Reserved

1100 APS PFM

1101 PWM PFM

1110 Reserved Reserved

1111 Reserved Reserved

programmed in its voltage register. SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state. from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings. as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B. To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.

1. Normal operation: The output voltage is selected by I2C bits SW1AB[5:0] for SW1A/B and SWx[6:0] for SW2 and SW3A/B. A

voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 32 and Table 33.

1. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state

SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively.

1. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state

SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively. Table 30, Table 31, Table 32, and Table 33 summarize the set point control and DVS time stepping applied to all regulators. Table 30. DVS control logic for SW1A/B

0 SW1AB[5:0]

1 SW1ABSTBY[5:0]

Table 31. DVS control logic for SW2 and SW3A/B

0 SWx[6:0]

1 SWxSTBY[6:0]

Table 32. DVS speed selection for SW1A/B

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PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the overcurrent condition on the regulator should be masked. Figure 10. Voltage stepping with DVS 4.0 MHz, 180 ° are the same in terms of phasing. Table 35 shows the optimum phasing when using more than one switching frequency. Table 33. DVS speed selection for SW2 and SW3A/B Table 34. Regulator phase clock selection

of power stages that are enabled. Table 35. Optimum phasing

1.0 MHz

2.0 MHz

4.0 MHz

Table 36. Regulator frequency configuration

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6.4.4.3 SW1A/B

SW1A/B is a 2.5 A single phase regulator. The SW1ALX and SW1BLX pins should be connected together on the board. SW1_CONFIG[1:0] = 01 is the only configuration supported. by using only one inductor for SW1A/B. Figure 11 shows the physical connection for SW1A/B in single phase. Figure 11. SW1A/B single phase block diagram Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register. Table 38. SW1 configuration

00 Reserved

01 A/B Single Phase

10 Reserved

11 Reserved

Table 37. Programmable current configuration (continued)

programmed for Normal, Standby, and Sleep mode by setting the SW1AB[5:0], SW1ABSTBY[5:0], and SW1ABOFF[5:0] bits respectively. Table 39 shows the output voltage coding for SW1A/B. Note: Output voltages of 0.6 V and below are not supported. provided in Table 41 through Table 45. Table 39. SW1A/B output voltage configuration

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Table 40. SW1A/B register summary Table 41. Register SW1ABVOLT - ADDR 0x20 Table 42. Register SW1ABSTBY - ADDR 0x21 Table 43. Register SW1ABOFF - ADDR 0x22 Table 44. Register SW1ABMODE - ADDR 0x23 SW1ABMODE 3:0 R/W 0x80 Sets the SW1AB switching operation mode. See Table 29 for all possible configurations.

Table 45. Register SW1ABCONF - ADDR 0x24 Table 46. SW1A/B external component recommendations

1. Use X5R or X7R capacitors.

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Table 47. SW1A/B electrical characteristics = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], typical external component values, fSW1AB = 2.0 MHz, unless otherwise noted.

• PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 2.5 A 0.625 V ≤ VSW1AB ≤ 1.450 V 1.475 V ≤ VSW1AB ≤ 1.875 V
• PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 150 mA 0.625 V < VSW1AB < 0.675 V 0.7 V < VSW1AB < 0.85 V 0.875 V < VSW1AB < 1.875 V -25 -3.0% -65 -45 -3.0% 3.0% 3.0% mV (40) ISW1AB Rated Output Load Current, 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V – – 2500 mA (41) ISW1ABLIM Current Limiter Peak Current Detection
• SW1A/B Single Phase (current through inductor) SW1ABILIM = 0 SW1ABILIM = 1 4.5 3.3 6.5 4.9 8.5 6.4 A (41) VSW1ABOSH Start-up Overshoot ISW1AB = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V –– 6 6 m V tONSW1AB Turn-on Time Enable to 90% of end value ISW1AB = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V – – 500 µs fSW1AB Switching Frequency SW1ABFREQ[1:0] = 00 SW1ABFREQ[1:0] = 01 SW1ABFREQ[1:0] = 10 1.0 2.0 4.0 MHz ηSW1AB Efficiency (Single Phase)
• V IN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 500 mA APS, PWM, 1.2 V, 750 mA APS, PWM, 1.2 V, 1250 mA APS, PWM, 1.2 V, 2500 mA ΔVSW1AB Output Ripple – 10 – mV VSW1ABLIR Line Regulation (APS, PWM) – – 20 mV VSW1ABLOR DC Load Regulation (APS, PWM) – – 20 mV VSW1ABLOTR Transient Load Regulation
• Transient load = 0 to 1.25 A, di/dt = 100 mA/ μs Overshoot Undershoot mV

Figure 12. SW1AB efficiency waveforms

1. Accuracy specification is incl usive of load and line regulation.
2. Current rating of SW1AB supports the Power Virus mode of operation of the i.MX6X processor.

Table 47. SW1A/B electrical characteristics (continued) = 1.2 V, ISW1AB = 100 mA, SW1AB_PWRSTG[2:0] = [111], typical external component values, fSW1AB = 2.0 MHz, unless otherwise noted.

42 NXP Semiconductors

6.4.4.4 SW2

bits. Figure 13 shows the block diagram and the external component connections for SW2 regulator. Figure 13. SW2 block diagram with 50 mV increments, as determined by bits SW2[5:0]. range, and the lower range be used for voltages from 0.400 to 1.975 V. and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] will be copied into bits SW2STBY[6], and SW2OFF[6] bits. SW2. Note: Output voltages of 0.6 V and below are not supported. Table 48. SW2 output voltage configuration

Table 48. SW2 output voltage configuration (continued)

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provided in Tables 50 to Table 54.

1. For voltages less than 2.0 V, only use set points 0 to 63

Table 49. SW2 register summary Table 50. Register SW2VOLT - ADDR 0x35 mode. See Table 48 for all possible configurations. for all possible configurations.

Table 51. Register SW2STBY - ADDR 0x36 SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during Standby mode. See Table 48 for all possible configurations. Table 48 for all possible configurations. Table 52. Register SW2OFF - ADDR 0x37 Table 48 for all possible configurations. for all possible configurations. Table 53. Register SW2MODE - ADDR 0x38 SW2MODE 3:0 R/W 0x80 Sets the SW2 switching operation mode. See Table 28 for all possible configurations. Table 54. Register SW2CONF - ADDR 0x39 SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. SW2PHASE 5:4 R/W 0x00 SW2 Phase clock selection. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection.

46 NXP Semiconductors

Table 55. SW2 external component recommendations

1. Use X5R or X7R capacitors.

Table 56. SW2 electrical characteristics

• PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW2 < 1.5 A 0.625 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V
• PFM, 2.8 V < V IN < 4.5 V, 0 < ISW2 ≤ 50 mA 0.625 V < VSW2 < 0.675 V 0.7 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV (45) ISW2 Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V – – 1500 mA (46) ISW2LIM Current Limiter Peak Current Detection
• Current through Inductor SW2ILIM = 0 SW2ILIM = 1 2.1 1.57 3.0 2.25 3.9 2.93 A VSW2OSH Start-up Overshoot ISW2 = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V –– 6 6 m V tONSW2 Turn-on Time Enable to 90% of end value ISW2 = 0.0 mA DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V – – 550 µs fSW2 Switching Frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 1.0 2.0 4.0 MHz

• V IN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH PFM, 3.15 V, 1.0 mA PFM, 3.15 V, 50 mA APS, PWM, 3.15 V, 400 mA APS, PWM, 3.15 V, 600 mA APS, PWM, 3.15 V, 1000 mA APS, PWM, 3.15 V, 1500 mA Switch mode supply SW2 (continued) ΔVSW2 Output Ripple – 10 – mV VSW2LIR Line Regulation (APS, PWM) – – 20 mV VSW2LOR DC Load Regulation (APS, PWM) – – 20 mV VSW2LOTR Transient Load Regulation
• Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ μs Overshoot Undershoot mV ISW2Q Quiescent Current PFM Mode APS Mode (Low output voltage settings) APS Mode (High output voltage settings) 145 305 µA RONSW2P SW2 P-MOSFET RDSON at VIN = VINSW2 = 3.3 V – 190 209 m Ω RONSW2N SW2 N-MOSFET RDSON at VIN = VINSW2 = 3.3 V – 212 255 m Ω ISW2PQ SW2 P-MOSFET Leakage Current VIN = VINSW2 = 4.5 V –– 1 2 µ A ISW2NQ SW2 N-MOSFET Leakage Current VIN = VINSW2 = 4.5 V –– 4 . 0 µ A RSW2DIS Discharge Resistance – 600 – Ω Notes 44. When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V. 45. Accuracy specification is incl usive of load and line regulation. 46. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).

Table 56. SW2 electrical characteristics (continued)

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Figure 14. SW2 efficiency waveforms

6.4.4.5 SW3A/B

Table 29 show the actual configuration options for the SW3xMODE[3:0] bits.

• A single phase
• Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 57 shows the options for the SW3CFG[1:0] bits. SW3A/B single phase In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 15. This configuration reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.

Table 57. SW3 Configuration

00 A/B Single Phase

11 A/B Independent

Figure 15. SW3A/B single phase block diagram

50 NXP Semiconductors

Figure 16. SW3A/B independent output block diagram 3.300 V with 50 mV increments, as determined by bits SW3x[5:0]. and that that the lower range be used for voltages from 0.400 to 1.975 V. voltage coding valid for SW3x. Note: Output voltages of 0.6 V and below are not supported.

Table 58. SW3A/B output voltage configuration

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1. For voltages less than 2.0 V, only use set points 0 to 63.

Table 58. SW3A/B output voltage configuration (continued)

on Tables 60 through Table 69. Table 59. SW3AB register summary Table 60. Register SW3AVOLT - ADDR 0x3C for all possible configurations. Table 61. Register SW3ASTBY - ADDR 0x3D

54 NXP Semiconductors

Table 62. Register SW3AOFF - ADDR 0x3E on bit SW3A[6] during OTP or TBB configuration. for all possible configurations. Table 63. Register SW3AMODE - ADDR 0x3F phase) switching operation mode. for all possible configurations. (Single phase) when in Sleep mode. Table 64. Register SW3ACONF - ADDR 0x40 SW3APHASE 5:4 R/W 0x00 SW3A Phase clock selection. See Table 34. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 33. Table 65. Register SW3BVOLT - ADDR 0x43 all possible configurations.

Table 66. Register SW3BSTBY - ADDR 0x44 Table 67. Register SW3BOFF - ADDR 0x45 Table 68. Register SW3BMODE - ADDR 0x46 Table 69. Register SW3BCONF - ADDR 0x47 SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 36. SW3BPHASE 5:4 R/W 0x00 SW3B Phase clock selection. See Table 34. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 33.

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Table 70. SW3A/B external component requirements

1. Use X5R or X7R capacitors.

Table 71. SW3A/B electrical characteristics SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

• PWM, APS 2.8 V < V IN < 4.5 V, 0 < ISW3x < ISW3xMAX 0.625 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V
• PFM , steady state (2.8 V < V IN < 4.5 V, 0 < ISW3x < 50 mA) 0.625 V < VSW3x < 0.675 V 0.7 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV (50) ISW3x Rated Output Load Current (51)
• 2.8 V < V IN < 4.5 V, 0.625 V < VSW3x < 3.3 V PWM, APS mode single phase PWM, APS mode independent (per phase) 2500 1250 mA

• Single phase (Current through inductor) SW3xILIM = 0 SW3xILIM = 1
• Independent mode (Current through inductor per phase) SW3xILIM = 0 SW3xILIM = 1 3.5 2.7 1.8 1.3 5.0 3.8 2.5 1.9 6.5 4.9 3.3 2.5 A V SW3xOSH Start-up Overshoot ISW3x = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V –– 6 6 m V tONSW3x Turn-on Time Enable to 90% of end value I SW3x = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V – – 500 µs fSW3x Switching Frequency SW3xFREQ[1:0] = 00 SW3xFREQ[1:0] = 01 SW3xFREQ[1:0] = 10 1.0 2.0 4.0 MHz ηSW3AB Efficiency (Single Phase)
• f SW3 = 2.0 MHz, LSW3x 1.0 μH PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA ΔVSW3x Output Ripple – 10 – mV VSW3xLIR Line Regulation (APS, PWM) – – 20 mV VSW3xLOR DC Load Regulation (APS, PWM) – – 20 mV VSW3xLOTR Transient Load Regulation
• Transient Load = 0.0 mA to I SW3x/2, di/dt = 100 mA/μs Overshoot Undershoot mV ISW3xQ Quiescent Current PFM Mode (Single Phase) APS Mode (Single Phase) PFM Mode (Independent mode) APS Mode (SW3A Independent mode) APS Mode (SW3B Independent mode) 300 250 150 µA R ONSW3AP SW3A P-MOSFET RDSON at VIN = VINSW3A = 3.3 V – 215 245 mΩ RONSW3AN SW3A N-MOSFET RDSON at VIN = VINSW3A = 3.3 V – 258 326 mΩ ISW3APQ SW3A P-MOSFET Leakage Current VIN = VINSW3A = 4.5 V –– 7 . 5 µ A

Table 71. SW3A/B electrical characteristics (continued) SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

58 NXP Semiconductors

Figure 17. SW3AB single phase efficiency waveforms

6.4.5 Boost regulator

integrated on-chip. Figure 18 shows the block diagram and component connection for the boost regulator.

1. When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V.
2. Accuracy specification is in clusive of load and line regulation.
3. The higher output voltages available depend on the voltage dr op in the conduction path as given by the following equation:

(VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance). SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

Figure 18. Boost regulator architecture

6.4.5.1 SWBST setup and control

if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros. Table 72. Register SWBSTCTL - ADDR 0x66

1. In Auto mode, the controller automatically swit ches between PFM and APS modes depending on the load current.

The SWBST regulator starts up by default in the Auto mode, if SWBST is part of the startup sequence.

60 NXP Semiconductors

6.4.5.2 SWBST external components

6.4.5.3 SWBST specifications

Table 73. SWBST external component requirements

1. Use X5R or X7R capacitors.

Table 74. SWBST electrical specifications characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.

6.4.6 LDO regulators description

references block description section for further information on the internal reference voltages. recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. Figure 19. General LDO block diagram Table 74. SWBST electrical specifications (continued) characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.

62 NXP Semiconductors

6.4.6.1 Transient response waveforms

line and load response refers to the overshoot, or undershoot only, excluding the DC shift. Figure 20. Transient waveforms

6.4.6.2 Short-circuit protection

will be generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 75 for SCP behavior configuration.

6.4.6.3 LDO regulator control

according to Table 76 for VGEN1 and VGEN2; and uses the voltage set point on Table 77 for VGEN3 through VGEN6. Table 75. Short-circuit behavior

0 Current limit

1 Shutdown

Table 76. VGEN1, VGEN2 output voltage configuration

64 NXP Semiconductors

presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output. Table 77. VGEN3/ 4/ 5/ 6 output voltage configuration Table 78. LDO control

1. STANDBY refers to a Standby event as described earlier.

Table 79. Register VGEN1CTL - ADDR 0x6C VGEN1 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 76 for all possible configurations. Table 80. Register VGEN2CTL - ADDR 0x6D VGEN2 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 76 for all possible configurations. Table 81. Register VGEN3CTL - ADDR 0x6E VGEN3 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 77 for all possible configurations.

66 NXP Semiconductors

Table 82. Register VGEN4CTL - ADDR 0x6F VGEN4 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 77 for all possible configurations. Table 83. Register VGEN5CTL - ADDR 0x70 VGEN5 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 77 for all possible configurations. Table 84. Register VGEN6CTL - ADDR 0x71 VGEN6 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 77 for all possible configurations.

6.4.6.4 External components

Table 85 lists the typical component values for the general purpose LDO regulators.

6.4.6.5 LDO specifications

Table 85. LDO external components

1. Use X5R/X7R ce ramic capacitors.

Table 86. VGEN1 electrical characteristics

68 NXP Semiconductors

• I GEN1 = 75 mA, 20 Hz to 20 kHz VGEN1[3:0] = 0000 - 1101 VGEN1[3:0] = 1110, 1111 dB (57) NOISEVGEN1 Output Noise Density VIN1 = 1.75 V, IGEN1 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -108 -118 -124 -100 -108 -112 dBV/ √Hz SLWRVGEN1 Turn-on Slew Rate
• 10% to 90% of end value
• 1.75 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA VGEN1[3:0] = 0000 to 0111 VGEN1[3:0] = 1000 to 1111 12.5 16.5 mV/μs GEN1tON Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN1 = 0.0 mA 60 – 500 μs GEN1tOFF Turn-Off Time Disable to 10% of initial value, VIN1 = 1.75 V IGEN1 = 0.0 mA –– 1 0 m s GEN1OSHT Start-Up Overshoot VGEN1LOTR Transient Load Response
• V IN1 = 1.75 V, 3.4 V IGEN1 = 10 to 100 mA in 1.0 μs. Peak of overshoot or undershoot of VGEN1 with respect to final value
• Refer to Figure 20 –– 3 . 0 % VGEN1LITR Transient Line Response
• I GEN1 = 75 mA VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN1[3:0] = 0000 to 1101 VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for VGEN1[3:0] = 1110, 1111
• Refer to Figure 20 –5 . 0 8 . 0 m V Notes 57. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test.

Table 86. VGEN1 electrical characteristics (continued)

Table 87. VGEN2 electrical characteristics 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.

• I GEN2 = 187.5 mA, 20 Hz to 20 kHz VGEN2[3:0] = 0000 - 1101 VGEN2[3:0] = 1110, 1111 dB (58) NOISEVGEN2 Output Noise Density
• V IN1 = 1.75 V, IGEN2 = 187.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -108 -118 -124 -100 -108 -112 dBV/√Hz SLWRVGEN2 Turn-On Slew Rate
• 10% to 90% of end value
• 1 . 7 5 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA VGEN2[3:0] = 0000 to 0111 VGEN2[3:0] = 1000 to 1111 12.5 16.5 mV/μs GEN2tON Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN2 = 0.0 mA 60 – 500 μs GEN2tOFF Turn-Off Time Disable to 10% of initial value, VIN1 = 1.75 V IGEN2 = 0.0 mA –– 1 0 m s

70 NXP Semiconductors

1. The PSRR of the regulators is measured with the perturbing sig nal at the input of the regulator. The power management IC is supplied separately

region of the regulator under test. Table 87. VGEN2 electrical characteristics (continued) 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.

Table 88. VGEN3 electrical characteristics

• I GEN3 = 75 mA, 20 Hz to 20 kHz VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V dB (60) NOISEVGEN3 Output Noise Density
• V IN2 = VIN2MIN, IGEN3 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWRVGEN3 Turn-on Slew Rate
• 10% to 90% of end value
• V I N 2MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA VGEN3[3:0] = 0000 to 0011 VGEN3[3:0] = 0100 to 0111 VGEN3[3:0] = 1000 to 1011 VGEN3[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV /μs GEN3tON Turn-on Time Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V IGEN3 = 0.0 mA 60 – 500 μs

72 NXP Semiconductors

1. When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper

regulation due to the dropout voltage generated through the internal LDO transistor.

1. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately

region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage. Table 89. VGEN4 electrical characteristics Table 88. VGEN3 electrical characteristics (continued)

• I GEN4 = 262.5 mA, 20 Hz to 20 kHz VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V dB (62) NOISEVGEN4 Output Noise Density
• V IN2 = VIN2MIN, IGEN4 = 262.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/ √Hz SLWRVGEN4 Turn-on Slew Rate
• 10% to 90% of end value
• V I N 2 MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA VGEN4[3:0] = 0000 to 0011 VGEN4[3:0] = 0100 to 0111 VGEN4[3:0] = 1000 to 1011 VGEN4[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV /μs GEN4tON Turn-on Time Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V IGEN4 = 0.0 mA 60 – 500 μs GEN4tOFF Turn-off Time Disable to 10% of initial value, VIN2 = VIN2MIN IGEN4 = 0.0 mA –– 1 0 m s GEN4OSHT Start-up Overshoot VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA –1 . 0 2 . 0 % VGEN4LOTR Transient Load Response VIN2 = VIN2MIN, 3.6 V IGEN4 = 35 to 350 mA in 1.0 μs Peak of overshoot or undershoot of VGEN4 with respect to final value. Refer to Figure 20 –– 3 . 0 %

Table 89. VGEN4 electrical characteristics (continued)

74 NXP Semiconductors

1. When the LDO Output voltage is set above 2.6 V the minimum al lowed input voltage need to be at least the output voltage plus 0.25 V for proper

regulation due to the dropout voltage generated through the internal LDO transistor.

1. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately

region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage. Table 90. VGEN5 electrical characteristics

4.5 V (63)

• I GEN5 = 75 mA, 20 Hz to 20 kHz VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V dB (64) NOISEVGEN5 Output Noise Density
• V IN3 = VIN3MIN, IGEN5 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWRVGEN5 Turn-on Slew Rate
• 10% to 90% of end value
• V I N 3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA VGEN5[3:0] = 0000 to 0011 VGEN5[3:0] = 0100 to 0111 VGEN5[3:0] = 1000 to 1011 VGEN5[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV /μs GEN5tON Turn-on Time Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V IGEN5 = 0.0 mA 60 – 500 μs GEN5tOFF Turn-off Time Disable to 10% of initial value, VIN3 = VIN3MIN IGEN5 = 0.0 mA –– 1 0 m s GEN5OSHT Start-up Overshoot VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA –1 . 0 2 . 0 % VGEN5LOTR Transient Load Response VIN3 = VIN3MIN, 4.5 V IGEN5 = 10 to 100 mA in 1.0 μs Peak of overshoot or undershoot of VGEN5 with respect to final value. Refer to Figure 20 –– 3 . 0 % VGEN5LITR Transient Line Response IGEN5 = 75 mA VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN5[3:0] = 0000 to 0111 VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for VGEN5[3:0] = 1000 to 1111 Refer to Figure 20 -5 . 0 8 . 0 m V Notes 63. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 64. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.

Table 90. VGEN5 electrical characteristics (continued)

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Table 91. VGEN6 electrical characteristics

4.5 V (65)

• I GEN6 = 150 mA, 20 Hz to 20 kHz VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V dB (66) NOISEVGEN6 Output Noise Density
• V IN3 = VIN3MIN, IGEN6 = 150 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWRVGEN6 Turn-On Slew Rate
• 10% to 90% of end value
• V I N 3MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA VGEN6[3:0] = 0000 to 0011 VGEN6[3:0] = 0100 to 0111 VGEN6[3:0] = 1000 to 1011 VGEN6[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV /μs GEN6tON Turn-on Time Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V IGEN6 = 0.0 mA 60 – 500 μs

6.4.7 VSNVS LDO/switch

switch, which is 40 mV at a rated maximum load current of 400 μA. providing certain conditions are met as described in Table 92.

1. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper

regulation due to the dropout voltage generated through the internal LDO transistor.

1. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately

region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage. Table 91. VGEN6 electrical characteristics (continued)

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Figure 21. VSNVS supply switch architecture Table 92 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system. The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 93. Table 92. VSNVS modes of operation Table 93. Register VSNVSCTL - ADDR 0x6B

1. Only valid when a valid input voltage is present.

Table 94. VSNVS External Components

2.25 V (VTL0) -

Table 95. VSNVS electrical characteristics 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.

• 5 . 0 μA < ISNVS < 400 μA (OFF) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
• 5 . 0 μA < ISNVS < 400 μA (ON) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
• 5 .0 μA < ISNVS < 400 μA (Coin Cell mode) 2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110 1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101] -5.0% -8.0% -5.0% -4.0% VCOIN-0.04 -8.0% 3.0 1.0 - 1.8 3.0 1.0 - 1.8 1.0 - 1.8 7.0% 7.0% 5.0% 4.0% VCOIN 7.0% V VSNVSDROP Dropout Voltage VIN = VCOIN = 2.85 V, VSNVSVOLT[2:0] = 110, ISNVS = 400 μA –– 5 0 m V ISNVSLIM Current Limit VIN > VTH1, VSNVSVOLT[2:0] = 110 VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101 VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 1100 500 480 6750 6750 4500 μA VTH0 VIN Threshold (Coin Cell Powered to VIN Powered) VIN going high with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.25 2.40 2.55 V VTL0 VIN Threshold (VIN Powered to Coin Cell Powered) VIN going low with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.20 2.35 2.50 V VHYST1 VIN Threshold Hysteresis for VTH1-VTL1 5.0 – – mV VHYST0 VIN Threshold Hysteresis for VTH0-VTL0 5.0 – – mV VSNVSCROSS Output Voltage During Crossover VSNVSVOLT[2:0] = 110 VCOIN > 2.9 V Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA 2.70 – – V (68) Notes 68. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause any malfunction. The i.MX 6’s RTC continues to operate through the transition, and as a worst case it may switch to the internal RC oscillator for a few clock cycles before switching back to the external crystal oscillator.

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6.4.7.1 Coin cell battery backup

threshold (VTL1 and VTL0), contact-bounced, or removed, the coin cell maintained logic will be powered by the voltage applied to LICELL. should be placed from LICELL to ground under all circumstances.

3.1 V (UVDETL)< V

1. For 1.8 V I SNVS limited to 100 μA for VCOIN < 2.1 V
2. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tR1 time.
3. From coin cell insertion to VSNVS =1.0 V, the delay time is typically 400 ms.
4. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside the

back to the external crystal oscillator. Table 95. VSNVS electrical characteristics (continued) 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.

Table 96. Coin cell charger voltage

1. Coin cell voltages selected based on the type of LICELL used on the system.

Table 97. Register COINCTL - ADDR 0x1A Coin cell charger output voltage selection. Table 98. Coin cell charger external components Table 99. Coin cell charger specifications

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6.5 Control interface I 2C block description

the resources of the IC can be controlled. The registers also provide status information about how the IC is operating. of 4.8 kohm. PWRON must be logic high for I2C communication to work robustly.

6.5.1 I2C device ID

address; these bits take affect right away.

6.5.2 I 2C operation

will be sent out unless a STOP command or NACK is received prior to completion. transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction. Figure 22. I2C write example Figure 23. I2C read example

6.5.3 Interrupt handling

clears an existing interrupt bit, the INTB pin will remain low. will go low after unmasking. read only, and not latched or clearable. asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

6.5.4 Interrupt bit summary

Table 100. Interrupt, mask and sense bits

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A full description of all interrupt, mask, and sense registers is provided in Tables 101 to 112.

1. Debounce timing for the falling edge c an be extended with PWRONDBNC[1:0].

Table 101. Register INTSTAT0 - ADDR 0x05 Table 102. Register INTMASK0 - ADDR 0x06 Table 100. Interrupt, mask and sense bits (continued)

Table 103. Register INTSENSE0 - ADDR 0x07 Table 104. Register INTSTAT1 - ADDR 0x08 Table 105. Register INTMASK1 - ADDR 0x09

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Table 106. Register INTSENSE1 - ADDR 0x0A Table 107. Register INTSTAT3 - ADDR 0x0E Table 108. Register INTMASK3 - ADDR 0x0F Table 109. Register INTSENSE3 - ADDR 0x10

Table 110. Register INTSTAT4 - ADDR 0x11 Table 111. Register INTMASK4 - ADDR 0x12 Table 112. Register INTSENSE4 - ADDR 0x13

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6.5.5 Specific registers

The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 113 to 115.

6.5.5.2 Embedded memory

Table 113. Register DEVICEID - ADDR 0x00 DEVICEID 3:0 R 0x01 Die version. Table 114. Register SILICON REV- ADDR 0x03

1. Default value depends on the silicon revision.

Table 115. Register FABID - ADDR 0x04 Table 116. Register MEMA ADDR 0x1C Table 117. Register MEMB ADDR 0x1D

6.5.6 Register bitmap

at address 0x7F. To access the Functional page from one of the extended pages, no write to the page register is necessary. Registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will have no effect.

• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear Reset: Reset signals are color coded based on the following legend. Default: The value after reset, as noted in the Default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read / Write bits that are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits that may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts.

Table 118. Register MEMC ADDR 0x1E Table 119. Register MEMD ADDR 0x1F

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6.5.6.1 Register map

Table 120. Functional page

00 DeviceID R 8'b0001_0001

03 SILICONREVID R 8'b0001_0000

04 FABID R 8'b0000_0000

05 INTSTAT0 RW1C 8'b0000_0000

06 INTMASK0 R/W 8'b0011_1111

07 INTSENSE0 R 8'b00xx_xxxx

08 INTSTAT1 RW1C 8'b0000_0000

09 INTMASK1 R/W 8'b0111_1111

10 INTSENSE3 R 8'b0000_000x

11 INTSTAT4 RW1C 8'b0000_0000

12 INTMASK4 R/W 8'b0011_1111

13 INTSENSE4 R 8'b00xx_xxxx

20 SW1ABVOLT R/W/M 8'b00xx_xxxx

21 SW1ABSTBY R/W 8'b00xx_xxxx

22 SW1ABOFF R/W 8'b00xx_xxxx

23 SW1ABMODE R/W 8'b0000_1000

24 SW1ABCONF R/W 8'bxx00_xx00

35 SW2VOLT R/W 8'b0xxx_xxxx

36 SW2STBY R/W 8'b0xxx_xxxx

37 SW2OFF R/W 8'b0xxx_xxxx

38 SW2MODE R/W 8'b0000_1000

39 SW2CONF R/W 8'bxx01_xx00

Table 120. Functional page (continued)

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40 SW3ACONF R/W 8'bxx10_xx00

43 SW3BVOLT R/W 8'b0xxx_xxxx

44 SW3BSTBY R/W 8'b0xxx_xxxx

45 SW3BOFF R/W 8'b0xxx_xxxx

46 SW3BMODE R/W 8'b0000_1000

47 SW3BCONF R/W 8'bxx10_xx00

66 SWBSTCTL R/W 8'b0xx0_10xx

70 VGEN5CTL R/W 8'b000x_xxxx

71 VGEN6CTL R/W 8'b000x_xxxx

Table 121. Extended page 1

80 OTP FUSE READ

84 OTP LOAD MASK R/W 8'b0000_0000

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Table 121. Extended page 1 (continued)

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1. In PF0200 It is required to set all of the FU SE_PORx bits to be able to load the fuses.

Table 122. Extended page 2

81 SW1AB PWRSTG R/W 8'b1111_1111

84 SW2 PWRSTG R 8'b1111_1111

85 SW3A PWRSTG R 8'b1111_1111

86 SW3B PWRSTG R 8'b1111_1111

87 PWRCTRL R 8'b0111_1111

88 PWRCTRL OTP

90 IO DRV R/W 8'b00xx_xxxx

Table 122. Extended page 2 (continued)

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1. Do not write in reserved registers.

7 Typical applications

7.1 Introduction

references and additional components such as filters, refer to the individual sections.

7.1.1 Application diagram

Figure 24. PF0200 typical application schematic

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7.1.2 Bill of materials

Table 123. Bill of materials (78)

1 Power management IC PF0200 Freescale

1.0 A 1 20 V SOD-123FL MBR120VLSFT1G ON Semiconductor Schottky Diode

Table 123. Bill of materials (78) (continued)

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7.2 PF0200 layout guidelines

7.2.1 General board recommendations

1. It is recommended to use an eight layer board stack-up arranged as follows:

• High current signal
• G N D
• Signal
• Power
• Power
• Signal
• G N D
• High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUT ING (high-current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.

7.2.2 Component placement

7.2.3 General routing requirements

1. Some recommended things to keep in mind for manufacturability:

• Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
• Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils Internal references, VCOREDIG, VCOREREF, VCORE 1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VCOREDIG 1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VCORE 0.22 μF 1 10 V X5R 0402 GRM155R61A224KE19D Murata VCOREREF Coin cell 0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet LICELL Miscellaneous 0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet VDDIO 1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VIN 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER PWRON 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER RESETBMCU 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER SDWN 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER INTB Notes 78. Freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.

1. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power,
2. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power

planes shield these traces).

1. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node

(i.e. SW1ALX, SW1BLX, SW2LX, SW3ALX, SW3BLX, and SWBSTLX).

1. Make sure that all components related to a specific block are referenced to the corresponding ground.

7.2.4 Parallel routing requirements

• CLK is the fastest signal of the syst em, so it must be given special care.
• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.

Figure 25. Recommended shielding for critical signals

• These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
• Care must be taken with these signals no t to contaminate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

7.2.5 Switching regulator layout recommendations

1. Per design, the switching regulators in PF0200 are designed to operate with only one input bulk capacitor. However, it is

should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.

1. Make high-current ripple traces low-inductance (short, high W/L ratio).
2. Make high-current traces wide or copper islands.

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Figure 26. Generic buck regulator architecture Figure 27. Recommended layout for buck regulators

7.3 Thermal information

7.3.1 Rating data

The thermal rating data of the packages has been simulated with the results listed in Table 4. 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.

7.3.2 Estimation of junction temperature

An estimation of the chip junction temperature TJ can be obtained from the equation: TJ = TA + (RθJA x PD) with: TA = Ambient temperature for the package in °C RθJA = Junction to ambient thermal resistance in °C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RθJB x PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See Functional block requirements and behaviors for more details on thermal management.

106 NXP Semiconductors

8 Packaging

8.1 Packaging dimensions

Table 124. Package drawing information

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110 NXP Semiconductors

112 NXP Semiconductors

REVISION HISTORY

9 Revision History

Revision Date Description of Changes 3.0 2/2014 • Initial release 4.0 5/2014

• Corrected VDDOTP maximum rating
• Corrected SWBSTFB maximum rating
• Added note to clarify SWBST default operation in Auto mode
• Changed VSNVS current limit
• Noted that voltage settings 0.6 V and below are not supported
• VSNVS Turn On Delay (t D1) spec corrected from 15 ms to 5.0 ms 5.0 7/2014 • Updated VTL1, VTH1 and VSNVSCROSS threshold specifications
• Updated per GPCN 16369 6.0 3/2015 • Added new part number MMPF0200F6AEP to the Orderable Parts table
• Added alternative capacitors in Bill of Materials 8/2016 • Updated to NXP document form and style

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Document Number: MMPF0200 Rev. 6.0