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Technical content

processors, memory, and system peripherals, in a wide range of applications.

  • Four to six buck converters, depending on configuration
  • Single/Dual phase/ parallel options
  • DDR termination tracking mode option
  • Boost regulator to 5.0 V output
  • Six general purpose linear regulators
  • Programmable output vo ltage, sequence, and timing
  • OTP (one time programmable) memory for device configuration
  • Coin cell charger and RTC supply
  • DDR termination reference voltage
  • Power control logic with processor interface and event detection
  • I 2C control
  • Individually programmable ON, OFF, and standby modes

Figure 1. Simplified application diagram

  • Tablets
  • I P T V
  • eReaders
  • Set top boxes
  • Industrial control
  • Medical monitoring
  • Home automation/ alarm/ energy management EP SUFFIX (E-TYPE) 98ASA00405D

56 QFN 8X8

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1 Orderable parts

associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 10. Table 1. Orderable Part Variations

  1. For tape and reel, add an R2 suffix to the part number.
  2. For programming details see Table 10. The available OTP options are not restricted to the listed reference designs. They can be used in any

application where the listed voltage and sequence details are acceptable.

  1. For designs using the i.MX 6SoloLite, it is recommended to us e the F3 OTP option instead of the F1 OTP option and F4 OTP option instead of
  2. SW2 can support an output current rating of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix) when SW2ILIM=0

1.1 PF0100 version differences

Table 2. Differences between PF0100 and PF0100A has to be 1 for fuses to be loaded during startup. FUSE_PORx bits during OTP programming. FUSE_POR3 bits during OTP programming. Table 3. Ambient temperature range

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2 Internal block diagram

Figure 2. Simplified internal block diagram

3 Pin connections

3.1 Pinout diagram

Figure 3. Pinout diagram

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3.2 Pin definitions

Table 4. PF0100 pin definitions Analog Reserved pin. Connect to GND in application. high current path and terminate at the output capacitance. and a 0.1 μF decoupling capacitor as close to the pin as possible. and a 0.1 μF decoupling capacitor as close to the pin as possible. and a 0.1 μF decoupling capacitor as close to the pin as possible. high current path and terminate at the output capacitance. GNDREF through a board ground plane. GNDREF, via board ground plane. 16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor. 18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor. current path and terminate at the output capacitance. a 0.1 μF decoupling capacitor as close to the pin as possible. current path and terminate at the output capacitance. 26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor.

as close to the pin as possible. current path and terminate at the output capacitance. and a 0.1 μF decoupling capacitor as close to the pin as possible. and a 0.1 μF decoupling capacitor as close to the pin as possible. current path and terminate at the output capacitance. 39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor. load. Keep this trace away from other noisy traces and planes. and a 0.1 μF decoupling capacitor as close to the pin as possible.

47 VDDOTP I 10 V (5) Digital and

48 GNDREF GND - GND Ground reference for the main band gap regulator.

  1. 10 V Maximum voltage rating during OTP fuse progra mming. 7.5 V Maximum DC voltage rated otherwise.
  2. Unused switching regulators should be connected as follow: Pi ns SWxLX and SWxFB should be unconnected and Pin SWxIN should be

connected to VIN with a 0.1 μF bypass capacitor. Table 4. PF0100 pin definitions (continued)

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4 General product characteristics

4.1 Absolute maximum ratings

Table 5. Absolute maximum ratings to the device. The detailed maximum voltage rating per pin can be found in the pin list section.

  1. ESD testing is performed in accor dance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),

4.2 Thermal characteristics

4.2.1 Power dissipation

protection is not tripped under normal conditions. Table 6. Thermal ratings

  • PF0100
  • PF0100A
  • PF0100AN -40 -40 -40 105 T J Operating junction temperature range -40 125 °C (8) TST Storage temperature range -65 150 °C TPPRT Peak package reflow temperature – Note 10 °C (9)(10) QFN56 thermal resistance and package dissipation ratings RθJA Junction to ambient
  • Natural convection
  • Four layer board (2s2p)
  • Eight layer board (2s6p) °C/W (11)(12)(13) RθJMA Junction to ambient (@200 ft/min)
  • Four layer board (2s2p) – 22 °C/W (11)(13) RθJB Junction to board – 10 °C/W (14) RΘJCBOTTOM Junction to case bottom – 1.2 °C/W (15) ΨJT Junction to package top
  • Natural convection – 2.0 °C/W (16) Notes 8. Do not operate beyond 125 °C for extended periods of time. O peration above 150 °C may cause permanent damage to the IC. See Table 7 for thermal protection features. 9. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 10. NXP’s Package Reflow capability meets Pb-f ree requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics. 11. Junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 12. The Board uses the JEDEC specif ications for thermal testing (and simulation) JESD51-7 and JESD51-5. 13. Per JEDEC JESD51-6 with the board horizontal. 14. Thermal resistance between the die and th e printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 15. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 16. Thermal characterization parameter indi cating the temperature difference between package top and the junction temperature per JEDEC JESD51- 2. When Greek letter (Ψ) are not available, the thermal characterization parameter is written as Psi-JT.

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4.3 Electrical characteristics

4.3.1 General specifications

Table 7. Thermal protection thresholds Table 8. General PMIC static characteristics.

4.3.2 Current consumption

Table 9. Current consumption summary 25 °C, unless otherwise noted.

  1. Refer to Figure 4 for coin cell mode characteristics over temperature.
  2. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
  3. For PFM operation, headroom should be 300 mV or greater.
  4. From -40 °C to 105 °C, applicable only to extended industrial parts.
  5. From -40 °C to 85 °C, applicable to consumer , industrial and extended industrial part numbers.
  6. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBM CU to VIN.

RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail off in the coin cell mode.

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Figure 4. Coin cell mode current vs temperature

5 General description

The PF0100 is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application processors.

5.1 Features

This section summarizes the PF0100 features.

  • Input voltage range to PMIC: 2.8 V - 4.5 V
  • Buck regulators
  • Four to six channel configurable
  • SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V
  • SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V
  • SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V
  • SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V
  • S W 4 , 1 . 0 A; 0.4 V to 3.3 V
  • SW4, VTT mode provide DDR termination at 50% of SW3A
  • Dynamic voltage scaling
  • Modes: PWM, PFM, APS
  • Programmable output voltage
  • Programmable current limit
  • Programmable soft start
  • Programmable PWM switching frequency
  • Programmable OCP with fault interrupt
  • Boost regulator
  • SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support
  • Modes: PFM and auto
  • OCP fault interrupt
  • L D O s
  • Six user programable LDO
  • VGEN1, 0.80 V to 1.55 V, 100 mA
  • VGEN2, 0.80 V to 1.55 V, 250 mA
  • V G E N 3 , 1 . 8 V to 3.3 V, 100 mA
  • V G E N 4 , 1 . 8 V to 3.3 V, 350 mA
  • V G E N 5 , 1 . 8 V to 3.3 V, 100 mA
  • V G E N 6 , 1 . 8 V to 3.3 V, 200 mA
  • Soft start
  • LDO/switch supply
  • DDR memory reference voltage
  • VREFDDR, 0.6 V to 0.9 V, 10 mA
  • 1 6 MHz internal master clock
  • OTP(one time programmable) memory for device configuration
  • User programmable start-up sequence and timing
  • Battery backed memory incl uding coin cell charger
  • I 2C interface
  • User programmable standby, sleep, and off modes Notes 24. SW2 capable of 2.5 A in NP, F9, and FA Industrial versions only (ANES suffix)

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5.2 Functional block diagram

Figure 5. Functional block diagram

5.3 Functional description

5.3.1 Power generation

switch/LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices. the processor cores and/or other circuitry. powered from VIN, or from a coin cell.

5.3.2 Control logic

configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration.

5.3.2.1 Interface signals

5.3.2.1.1 PWRON

PWRON is an input signal to the IC generating a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG

5.3.2.1.2 STANDBY

STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits sta ndby page 29 for more details. Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode.

5.3.2.1.3 RESETBMCU

RESETBMCU is an open drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 ms to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during start-up. At anytime, if a f ault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100 is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persist s, the sequence described above is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on Table 137 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses.

5.3.2.1.4 SDWNB

SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock cycle before powering down and is then de-asserted in the OFF state.

5.3.2.1.5 INTB

INTB is an open drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.

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6 Functional block requirements and behaviors

6.1 Start-up

OTP configuration is enabled by connecting VDDOTP to GND. I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration.

6.1.1 Device start-up configuration

Table 10. Start-up configuration

  1. For designs using the i.MX 6SoloLite , it is recommended to use the F3 OTP option instead of the F1 OTP option

and F4 OTP option instead of the F2 OTP option. Table 10. Start-up configuration (continued)

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Figure 6. Default start-up sequence Table 11. Default start-up sequence timing

  • SEQ_CLK_SPEED[1:0] = 00 –2 . 0– ms
  • SEQ_CLK_SPEED[1:0] = 01 –2 . 5– (28)
  • SEQ_CLK_SPEED[1:0] = 10 –4 . 0–
  • SEQ_CLK_SPEED[1:0] = 11 –7 . 0– tR3 Rise time of regulators – 0.2 – ms (29) *VSNVS starts from 1.0 V if LICELL is valid before VIN. UVDET LICELL VIN VSNVS PWRON SW1A/B SW1C SW2 VGEN2 SW3A/B SW4 VREFDDR VGEN4 VGEN5 VGEN6 RESETBMCU td1 td3 td4 td4 tr1 tr3 tr3 tr3 td5 tr4 tr2td2

6.1.2 One time programmability (OTP)

code(ECC) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. The parameters which can be configured by OTP are listed below.

  • General: I 2C slave address, PWRON pin configuration, start-up sequence and timing
  • Buck regulators: Output voltage, dual/singl e phase or independent mode configuration, switching frequency, and soft start ramp rate
  • Boost regulator and LDOs: Output voltage NOTE: When prototyping or programming fuses, th e user must ensure register settings are consistent with the hardware configuration. This is most important for the buck regulators, where the quant ity, size, and value of the inductors depend on the configuratio n (single/ dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it is gated by the buck regulator in the start-up sequence.

6.1.2.1 Start-up sequence and timing

Table 12. The delay between each position is equal; ho wever, four delay options are available. See Table 13. The start-up sequence terminates at the last programmed regulator.

  • SEQ_CLK_SPEED[1:0] = 00 –0 . 5– ms
  • SEQ_CLK_SPEED[1:0] = 01 –1 . 0–
  • SEQ_CLK_SPEED[1:0] = 10 –2 . 0–
  • SEQ_CLK_SPEED[1:0] = 11 –4 . 0– tR4 Rise time of RESETBMCU – 0.2 – ms tD5 Turn-on delay of RESETBMCU – 2.0 – ms Notes 26. Assumes LICELL voltage is valid before VIN is applied. If LICE LL is not valid before VIN is applied then VSNVS turn-on delay may extend to a maximum of 24 ms. 27. Depends on the external signal driving PWRON. 28. Default configuration. 29. Rise time is a function of slew rate of regulators and nominal voltage selected.

Table 11. Default start-up sequence timing (continued)

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6.1.2.2 PWRON pin configuration

switch is held low for greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.

6.1.2.3 I 2C address configuration

The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I 2C address to avoid bus conflicts. (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 15. Table 12. Start-up sequence

00000 Off

00001 SEQ_CLK_SPEED[1:0] * 1

00010 SEQ_CLK_SPEED[1:0] * 2

11111 SEQ_CLK_SPEED[1:0] * 31

Table 13. Start-up sequence clock speed Table 14. PWRON configuration

0 PWRON pin HIGH = ON

1 PWRON pin pulled LOW momentarily = ON

Table 15. I2C address configuration

6.1.2.4 Soft start ramp rate

6.1.3 OTP prototyping

are referred to as the TBBOTP registers. The portion of the register map concerned with OTP is shown in Table 137 and Table 138. depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR_XOR bits. Refer to Table 16.

  • If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
  • I f V D D O T P = 0 . 0 V, TBB_POR = 0 and FUSE_POR_XOR = 1, the values are loaded from the fuses. In the MMPF0100, FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In the MMPF0100A, the XOR function is removed. It is required to set all of the FUSE_PORx bits to be able to load the fuses.
  • I f V D D O T P = 0 . 0 V, TBB_POR = 0 and FUSE_POR_XOR = 0, the TBBOTP registers remain initialized at zero. The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP registers maintained and not loaded from a different source. The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 V to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. To power on with the contents of the TBBOTP registers, the following condit ions must exist; VIN is valid, VDDOTP = 0 .0 V, TBB_POR = 1 and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping.

6.1.4 Reading OTP fuses

6.1.5 Programming OTP fuses

VDDOTP pin, bypassed with 10 to 20 μF of capacitance. For more details on programming the OTP fuses, see application note AN4536. Table 15. I2C address configuration (continued)

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  • VIN < UVDET
  • All regulators are in sleep mode
  • All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
  • During start-up, VIN > UVDET
  • PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 27 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.

6.2.1 Clock adjustment

your NXP representative for detailed information on this feature.

6.3 Bias and references block description

6.3.1 Internal core voltage references

valid supply and/or valid coin cell. Table 18 shows the main characteristics of the core circuitry. Table 16. Source of start-up sequence Table 17. 16 MHz clock specifications characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

  1. 2.0 MHz clock is deriv ed from the 16 MHz clock.

6.3.1.1 External components

6.3.2 VREFDDR voltage reference

voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then utilizes a voltage follower to drive the load. Figure 7. VREFDDR block diagram Table 18. Core voltages electrical specifications(32) characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

  • ON mode
  • Coin cell mode and OFF 1.5 1.3 V (31) VCORE (analog core supply) VCORE Output voltage
  • ON mode and charging
  • OFF and coin cell mode 2.775 0.0 V (31) VCOREREF (bandgap / regulator reference) VCOREREF Output voltage – 1.2 – V (31) VCOREREFTACC Temperature drift – 0.25 – % Notes 32. For information only.

Table 19. External components for core voltages

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6.3.2.1 VREFDDR control register

The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 20.

6.3.2.1.1 External components

6.3.2.1.2 VREFDDR specifications

Table 20. Register VREFDDCRTL - ADDR 0x6A

  • 0 = VREFDDR Disabled
  • 1 = VREFDDR Enabled UNUSED 7:5 – 0x00 UNUSED

Table 21. VREFDDR external components(33)

  1. Use X5R or X7R capacitors.
  2. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output.

Table 22. VREFDDR electrical characteristics

  • IREFDDR when VREFDDR is forced to VINREFDDR/4 10.5 15 25 mA IREFDDRQ Quiescent Current – 8.0 – μA (35) Active mode – DC VREFDDR Output voltage
  • 1.2 V < VINREFDDR < 1.8 V
  • 0.0 mA < IREFDDR < 10 mA –V INREFDDR/2 – V VREFDDRTOL Output voltage tolerance (TA = -40 °C to 85 °C)
  • 1.2 V < VINREFDDR < 1.8 V
  • 0.6 mA ≤ IREFDDR ≤ 10 mA –1.0 – 1.0 % VREFDDRTOL Output voltage tolerance (TA = -40 °C to 105 °C), applicable only to the extended industrial version
  • 1.2 V < VINREFDDR < 1.8 V
  • 0.6 mA ≤ IREFDDR ≤ 10 mA –1.2 – 1.2 % VREFDDRLOR Load regulation
  • 1.0 mA < IREFDDR < 10 mA
  • 1.2 V < VINREFDDR < 1.8 V –0 . 4 0– m V / m A
  • Enable to 90% of end value
  • V INREFDDR = 1.2 V, 1.8 V
  • IREFDDR = 0.0 mA – – 100 μs tOFFREFDDR Turn-off time
  • Disable to 10% of initial value
  • V INREFDDR = 1.2 V, 1.8 V
  • IREFDDR = 0.0 mA –– 1 0 m s VREFDDROSH Start-up overshoot
  • VINREFDDR = 1.2 V, 1.8 V
  • IREFDDR = 0.0 mA –1 . 0 6 . 0 % VREFDDRTLR Transient load response
  • VINREFDDR = 1.2 V, 1.8 V –5 . 0– m V Notes 35. When VREFDDR is off there is a quiescent current of 1.5 μA typical.

Table 22. VREFDDR electrical characteristics (continued)

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6.4 Power generation

6.4.1 Modes of operation

diagram of the PF0100, along with the conditions to enter and exit from each state. Figure 8. State diagram coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and on states.

6.4.1.1 ON mode

The PF0100 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.

6.4.1.2 OFF mode

asserted, low, in this mode.

6.4.1.3 Standby mode

  • Depending on STANDBY pin configuration, standby is entered when the STANDBY pin is asserted. This is typically used for low- power mode of operation.
  • When STANDBY is de-asserted, standby mode is exited. A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the over all platform current by lowering the regulator output voltage, chang ing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in standby is pre-programmed through the I2C interface. Note that the STANDBY pin is programmable for active high or ac tive low polarity, and decoding of a standby event takes into ac count the programmed input polarity as shown in Table 23. When the PF0100 is powered up first, regulator settings for the standby mode are mirrored from the regulator settings for the on mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY generally is referred to as active high throughout this document. Since STANDBY pin activity is driven asynchronously to the system , a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a standby event. This allows the processor and peripherals some time after a standby instruction has been re ceived to terminate processes to facilitate s eamless entering into standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 24, STBYDLY delays the standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the standby event.

6.4.1.4 Sleep mode

  • Depending on PWRON pin configuration, sleep mode is enter ed when PWRON is de-asserted and SWxOMODE bit is set.
  • To exit sleep mode, assert the PWRON pin. In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/ B, and SW4. The activated regulators maintains settings for this mode and voltage until the next turn-on event. Table 25 shows the control bits in sleep mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event.

Table 23. Standby pin and polarity control

  1. STANDBY = 0: System is not in standby , STANDBY = 1: System is in standby
  2. The state of the STANDBY pin only has influence in on mode.
  3. Bit 6 in power control register (ADDR - 0x1B)

Table 24. STANDBY delay - initiated response

00 No delay

01 One 32 k period (default)

10 Two 32 k periods

11 Three 32 k periods

  1. Bits [5:4] in power cont rol register (ADDR - 0x1B)

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6.4.1.5 Coin cell mode

state. Transition to the off state requires VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. is re-initialized with all I2C bits including those reset on COINPORB, which are restored to their default states.

6.4.2 State machine flow summary

Table 26 provides a summary matrix of the PF0100 flow diagram to show the conditions needed to transition from one state to another. Table 25. Regulator mode control

  1. For sleep mode, an activated switch ing regulator, should use the off

SWxOFF[6:0] for SW2, SW3A/B, and SW4. Table 26. State machine flow summary

6.4.2.1 Turn on events

From off and sleep modes, the PMIC is powered on by a turn-on event. The type of turn-on event depends on the configuration of PWRON. PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1.

  • If PWRON_CFG = 0, the PWRON signal is high and V IN > UVDET, the PMIC turns on; the interrupt and sense bits, PWRONI and PWRONS respectively, is set.
  • If PWRON_CFG = 1, V IN > UVDET and PWRON transitions from high to low, the PMIC turns on; the interrupt and sense bits, PWRONI and PWRONS respectively, sets. The sense bit shows the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch debounced through a programmable debouncer, PWRONDBNC[1:0], to av oid a response to a very short (i.e., unintentional) key press . The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce ti ming can be extended with PWRONDBNC[1:0] as defined in Table 27. The interrupt is cleared by software, or when cycling through the OFF mode.

6.4.2.2 Turn off events

6.4.2.2.1 PWRON pin

  1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
  2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.

Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

6.4.2.2.2 Thermal protection

section for more detailed information.

6.4.2.2.3 Undervoltage detection

When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin cell mode. Table 27. PWRON hardware debounce bit settings

  1. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.

32 NXP Semiconductors

6.4.3 Power tree

by any rail supplying voltage to DDR memories; the typical applic ation recommends the use of SW3 as the input supply for VREFDD R. and current requirements, therefore a proper input voltage should be selected for the regulators. Table 28. Power tree summary

  1. Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up
  2. SW2 capable of 2500 mA in NP, F9, and FA Industrial versions only (ANES suffix)

Table 29. UVDET threshold

Figure 9. PF0100 typical power map

34 NXP Semiconductors

6.4.4 Buck regulators

Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.

6.4.4.1 Current limit

condition persists for more than 8.0 ms, a fault interrupt is generated.

6.4.4.2 General control

variation. Available switching modes for buck regulators are presented in Table 30. mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Table 31 summarizes the buck regulator programmability for normal and standby modes. Table 30. Switching mode description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is alwa ys in PFM mode, which is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. depending on load conditions. Table 31. Regulator mode control

0000 Off Off

0001 PWM Off

0010 Reserved Reserved

0011 PFM Off

0100 APS Off

0101 PWM PWM

0110 PWM APS

0111 Reserved Reserved

1000 APS APS

1001 Reserved Reserved

1010 Reserved Reserved

1011 Reserved Reserved

1100 APS PFM

1101 PWM PFM

1110 Reserved Reserved

1111 Reserved Reserved

regulator, the output voltage options are the same for normal and standby modes. programmed in its voltage register. regulator returns to its default on state output voltage and switch mode settings. programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.

6.4.4.2.1 Dynamic voltage scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.

  1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4.

A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 34 and Table 35.

  1. Standby mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state

SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively.

  1. Sleep mode: The output voltage can be higher or lower than in nor mal operation, but is typically selected to be the lowest state

SWxDVSSPEED[1:0] I2C bits shown in Table 34 and Table 35, respectively. Table 32, Table 33, Table 34, and Table 35 summarize the set point control and DVS time stepping applied to all regulators. Table 32. DVS control logic for SW1A/B/C

0 SW1x[5:0]

1 SW1xSTBY[5:0]

Table 33. DVS control logic for SW2, SW3A/B, and SW4

0 SWx[6:0]

1 SWxSTBY[6:0]

Table 34. DVS speed selection for SW1A/B/C

36 NXP Semiconductors

PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. DVS period the overcurrent condition on the regulator should be masked. Figure 10. Voltage stepping with DVS

6.4.4.2.2 Regulator phase clock

are the same in terms of phasing. Table 37 shows the optimum phasing when using more than one switching frequency. Table 35. DVS speed selection for SW2, SW3A/B, and SW4 Table 36. Regulator phase clock selection

6.4.4.2.3 Programmable maximum current

Table 37. Optimum phasing

1.0 MHz

2.0 MHz

4.0 MHz

Table 38. Regulator frequency configuration

11 Reserved

Table 39. Programmable current configuration

38 NXP Semiconductors

6.4.4.3 SW1A/B/C

  • SW1A/B/C single phase with one inductor
  • SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor
  • SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Table 137. Extended page 1, page 111, as shown in Table 40.

6.4.4.3.1 SW1A/B/C single phase

respectively. Figure 11 shows the connection for SW1A/B/C in single phase mode. be used. The SW1FB pin should be left floating in this configuration. Table 40. SW1 configuration

00 A/B/C single phase

01 A/B single phase, C independent mode

10 A/B dual phase, C independent mode

Table 39. Programmable current configuration (continued)

Figure 11. SW1A/B/C single phase block diagram

6.4.4.3.2 SW1A/B single phase - SW1C independent mode

connection for SW1A/B in single phase and SW1C as an independent output.

40 NXP Semiconductors

Figure 12. SW1A/B single phase, SW1C independent mode block diagram SW1CLX node operates independently, using the configuration in the SW1CCONF register.

6.4.4.3.3 SW1A/B dual phase - SW1C independent mode

connection for SW1A/B in dual phase and SW1C as an independent output.

Figure 13. SW1A/B dual phase, SW1C independent mode block diagram

6.4.4.3.4 SW1A/B/C setup and control registers

respectively. Table 41 shows the output voltage coding for SW1A/B or SW1C. Note: Voltage set points of 0.6 V and below are not supported.

42 NXP Semiconductors

Table 41. SW1A/B/C output voltage configuration

provided in Table 43 through Table 52. Table 42. SW1A/B/C register summary Table 43. Register SW1ABVOLT - ADDR 0x20 Table 44. Register SW1ABSTBY - ADDR 0x21 Table 45. Register SW1ABOFF - ADDR 0x22

44 NXP Semiconductors

Table 46. Register SW1ABMODE - ADDR 0x23 SW1ABMODE 3:0 R/W 0x08 Sets the SW1AB switching operation mode. See Table 31 for all possible configurations.

  • 0 = OFF
  • 1 = PFM UNUSED 7:6 – 0x00 unused

Table 47. Register SW1ABCONF - ADDR 0x24

  • 0 = High level current limit
  • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW1ABFREQ 3:2 R/W 0x00 SW1A/B switching frequency selector. See Table 38. SW1ABPHASE 5:4 R/W 0x00 SW1A/B phase clock selection. See Table 36. SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection. See Table 34.

Table 48. Register SW1CVOLT - ADDR 0x2E Table 49. Register SW1CSTBY - ADDR 0x2F Table 50. Register SW1COFF - ADDR 0x30

6.4.4.3.5 SW1A/B/C external components

Table 51. Register SW1CMODE - ADDR 0x31 SW1CMODE 3:0 R/W 0x08 Sets the SW1C switching operation mode. See Table 30 for all possible configurations.

  • 0 = OFF
  • 1 = PFM UNUSED 7:6 – 0x00 unused

Table 52. Register SW1CCONF - ADDR 0x32

  • 0 = High level current limit
  • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW1CFREQ 3:2 R/W 0x00 SW1C switching frequency selector. See Table 38. SW1CPHASE 5:4 R/W 0x00 SW1C phase clock selection.See Table 36. SW1CDVSSPEED 7:6 R/W 0x00 SW1C DVS speed selection. See Table 34.

Table 53. SW1A/B/C external component recommendations

  1. Use X5R or X7R capacitors.

46 NXP Semiconductors

6.4.4.3.6 SW1A/B/C specifications

Table 54. SW1A/B/C electrical characteristics characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

  • PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1ABC < 4.5 A
  • 0.625 V ≤ VSW1ABC ≤ 1.450 V
  • 1.475 V ≤ VSW1ABC ≤ 1.875 V
  • PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1ABC < 150 mA
  • 0.625 V < VSW1ABC < 0.675 V
  • 0.7 V < VSW1ABC < 0.85 V
  • 0.875 V < VSW1ABC < 1.875 V -25 -3.0% -65 -45 -3.0% 3.0% 3.0% mV I SW1ABC Rated output load current,
  • 2.8 V < VIN < 4.5 V, 0.625 V < VSW1ABC < 1.875 V – – 4500 mA ISW1ABCLIM Current limiter peak current detection
  • Current through inductor
  • SW1ABILIM = 0
  • SW1ABILIM = 1 7.1 5.3 10.5 7.9 13.7 10.3 A VSW1ABCOSH Start-up overshoot
  • ISW1ABC = 0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V –– 6 6 m V tONSW1ABC Turn-on time
  • Enable to 90% of end value
  • I SW1x = 0 mA
  • DVS clk = 25 mV/4.0 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V – – 500 µs fSW1ABC Switching frequency
  • SW1xFREQ[1:0] = 00
  • SW1xFREQ[1:0] = 01
  • SW1xFREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW1ABC Efficiency
  • V IN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 μH
  • PFM, 0.9 V, 1.0 mA
  • PFM, 1.2 V, 50 mA
  • APS, PWM, 1.2 V, 850 mA
  • APS, PWM, 1.2 V, 1275 mA
  • APS, PWM, 1.2 V, 2125 mA
  • APS, PWM, 1.2 V, 4500 mA ΔV SW1ABC Output ripple – 10 – mV VSW1ABCLIR Line regulation (APS, PWM) – – 20 mV VSW1ABCLOR DC load regulation (APS, PWM) – – 20 mV
  • Transient load = 0 to 2.25 A, di/dt = 100 mA/ μs
  • Overshoot
  • Undershoot mV ISW1ABCQ Quiescent current
  • PFM Mode
  • APS Mode 145 µA R SW1ABCDIS Discharge resistance – 600 – Ω SW1A/B (single/dual phase) VINSW1A VINSW1B Operating input voltage 2.8 – 4.5 V VSW1AB Nominal output voltage – Table 41 –V VSW1ABACC Output voltage accuracy
  • PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 2.5 A
  • 0.625 V ≤ VSW1AB ≤ 1.450 V
  • 1.475 V ≤ VSW1AB ≤ 1.875 V
  • PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 150 mA
  • 0.625 V < VSW1AB < 0.675 V
  • 0.7 V < VSW1AB < 0.85 V
  • 0.875 V < VSW1AB < 1.875 V -25 -3.0% -65 -45 -3.0% 3.0% 3.0% mV I SW1AB Rated output load current,
  • 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V – – 2500 mA (46) ISW1ABLIM Current limiter peak current detection
  • SW1A/B single phase (current through inductor)
  • SW1ABILIM = 0
  • SW1ABILIM = 1
  • SW1A/B dual phase (current through inductor per phase)
  • SW1ABILIM = 0
  • SW1ABILIM = 1 4.5 3.3 2.2 1.6 6.5 4.9 3.2 2.4 8.5 6.4 4.3 3.2 A (46) VSW1ABOSH Start-up overshoot
  • ISW1AB = 0.0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V –– 6 6 m V tONSW1AB Turn-on time
  • Enable to 90% of end value
  • I SW1AB = 0.0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V – – 500 µs fSW1AB Switching frequency
  • SW1ABFREQ[1:0] = 00
  • SW1ABFREQ[1:0] = 01
  • SW1ABFREQ[1:0] = 10 1.0 2.0 4.0 MHz

Table 54. SW1A/B/C electrical characteristics (continued) characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

48 NXP Semiconductors

  • V IN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH
  • PFM, 0.9 V, 1.0 mA
  • PFM, 1.2 V, 50 mA
  • APS, PWM, 1.2 V, 500 mA
  • APS, PWM, 1.2 V, 750 mA
  • APS, PWM, 1.2 V, 1250 mA
  • APS, PWM, 1.2 V, 2500 mA ΔV SW1AB Output ripple – 10 – mV VSW1ABLIR Line regulation (APS, PWM) – – 20 mV VSW1ABLOR DC load regulation (APS, PWM) – – 20 mV VSW1ABLOTR Transient load regulation
  • Transient load = 0 to 1.25 A, di/dt = 100 mA/ μs
  • Overshoot
  • Undershoot mV ISW1ABQ Quiescent current
  • PFM mode
  • APS mode 235 µA R ONSW1AP SW1A P-MOSFET RDS(on)
  • VINSW1A = 3.3 V – 215 245 m Ω RONSW1AN SW1A N-MOSFET RDS(on)
  • VINSW1A = 3.3 V – 258 326 m Ω ISW1APQ SW1A P-MOSFET leakage current
  • VINSW1A = 4.5 V –– 7 . 5 µ A ISW1ANQ SW1A N-MOSFET leakage current
  • VINSW1A = 4.5 V –– 2 . 5 µ A RONSW1BP SW1B P-MOSFET RDS(on)
  • VINSW1B = 3.3 V – 215 245 m Ω RONSW1BN SW1B N-MOSFET RDS(on)
  • VINSW1B = 3.3 V – 258 326 m Ω ISW1BPQ SW1B P-MOSFET leakage current
  • VINSW1B = 4.5 V –– 7 . 5 µ A ISW1BNQ SW1B N-MOSFET leakage current
  • VINSW1B = 4.5 V –– 2 . 5 µ A RSW1ABDIS Discharge resistance – 600 – Ω

characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

  • PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1C < 2.0 A
  • 0.625 V ≤ VSW1C ≤ 1.450 V
  • 1.475 V ≤ VSW1C ≤ 1.875 V
  • PFM, steady state 2.8 V < V IN < 4.5 V, 0 < ISW1C < 50 mA
  • 0.625 V < VSW1C < 0.675 V
  • 0.7 V < VSW1C < 0.85 V
  • 0.875 V < VSW1C < 1.875 V -25 -3.0% -65 -45 -3.0% 3.0% 3.0% mV I SW1C Rated output load current
  • 2.8 V < VIN < 4.5 V, 0.625 V < VSW1C < 1.875 V – – 2000 mA ISW1CLIM Current limiter peak current detection
  • Current through inductor
  • SW1CILIM = 0
  • SW1CILIM = 1 2.6 1.95 4.0 3.0 5.2 3.9 A (45) VSW1COSH Start-up overshoot
  • ISW1C = 0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V –– 6 6 m V tONSW1C Turn-on time
  • Enable to 90% of end value
  • I SW1C = 0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V – – 500 µs fSW1C Switching frequency
  • SW1CFREQ[1:0] = 00
  • SW1CFREQ[1:0] = 01
  • SW1CFREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW1C Efficiency
  • V IN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 μH
  • PFM, 0.9 V, 1.0 mA
  • PFM, 1.2 V, 50 mA
  • APS, PWM, 1.2 V, 400 mA
  • APS, PWM, 1.2 V, 600 mA
  • APS, PWM, 1.2 V, 1000 mA
  • APS, PWM, 1.2 V, 2000 mA ΔV SW1C Output ripple – 10 – mV VSW1CLIR Line regulation (APS, PWM) – – 20 mV VSW1CLOR DC load regulation (APS, PWM) – – 20 mV VSW1CLOTR Transient load regulation
  • Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ μs
  • Overshoot
  • Undershoot mV ISW1CQ Quiescent current
  • PFM mode
  • APS mode 145 µA

characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

50 NXP Semiconductors

Figure 14. SW1AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.375 V; consumer version

  • at VINSW1C = 3.3 V – 184 206 mΩ RONSW1CN SW1C N-MOSFET RDS(on)
  • at VINSW1C = 3.3 V – 211 260 mΩ ISW1CPQ SW1C P-MOSFET leakage current
  • VINSW1C = 4.5 V –– 1 0 . 5 µ A ISW1CNQ SW1C N-MOSFET leakage current
  • VINSW1C = 4.5 V –– 3 . 5 µ A RSW1CDIS Discharge resistance – 600 – Ω Notes 45. Meets 1.89 A current rating for VDDSOC_IN domain on i.MX 6X processor. 46. Current rating of SW1AB supports the power viru s mode of operation of the i.MX 6X processor.

characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

52 NXP Semiconductors

6.4.4.4 SW2

connections for SW2 regulator. Figure 18. SW2 block diagram

6.4.4.4.1 SW2 setup and control registers

set to “0”, the output is limited to the lower output voltages from 0.400 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. increments, as determined by bits SW2[5:0]. and the lower range be used for voltages from 0.400 V to 1.975 V. and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] are copied into bits SW2STBY[6], and SW2OFF[6] bit s. Note: Voltage set points of 0.6 V and below are not supported. Table 55. SW2 output voltage configuration

Table 55. SW2 output voltage configuration (continued)

54 NXP Semiconductors

  1. For voltages less than 2.0 V, only use set points 0 to 63.

Table 56. SW2 register summary Table 57. Register SW2VOLT - ADDR 0x35 mode. See Table 55 for all possible configurations. for all possible configurations.

Table 58. Register SW2STBY - ADDR 0x36 SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during standby mode. See Table 55 for all possible configurations. Table 55 for all possible configurations. Table 59. Register SW2OFF - ADDR 0x37 Table 55 for all possible configurations. Table 55 for all possible configurations. Table 60. Register SW2MODE - ADDR 0x38 SW2MODE 3:0 R/W 0x08 Sets the SW2 switching operation mode. See Table 30 for all possible configurations.

  • 0 = OFF
  • 1 = PFM UNUSED 7:6 – 0x00 unused

Table 61. Register SW2CONF - ADDR 0x39

  • 0 = High level current limit
  • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. See Table 38. SW2PHASE 5:4 R/W 0x00 SW2 phase clock selection. See Table 36. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. See Table 35. Notes 48. SW2ILIM = 0 must be used in NP/F9/FA versions (Industrial only) if 2.5 A output load current is desired

56 NXP Semiconductors

6.4.4.4.2 SW2 external components

6.4.4.4.3 SW2 Specifications

Table 62. SW2 external component recommendations

  1. Use X5R or X7R capacitors.

Table 63. SW2 electrical characteristics characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

  • PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW2 < 2.0 A
  • 0.625 V < VSW2 < 0.85 V
  • 0.875 V < VSW2 < 1.975 V
  • 2.0 V < VSW2 < 3.3 V
  • PFM, 2.8 V < V IN < 4.5 V, 0 < ISW2 ≤ 50 mA
  • 0.625 V < VSW2 < 0.675 V
  • 0.7 V < VSW2 < 0.85 V
  • 0.875 V < VSW2 < 1.975 V
  • 2.0 V < VSW2 < 3.3 V -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV I SW2 Rated output load current
  • 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V
  • 2.8 V < VIN < 4.5 V, 1.2 V < VSW2 < 3.3 V, SW2LIM = 0 2000 2500 mA (51) (52) ISW2LIM Current limiter peak current detection
  • Current through inductor
  • SW2ILIM = 0
  • SW2ILIM = 1 2.8 2.1 4.0 3.0 5.2 3.9 A VSW2OSH Start-up overshoot
  • ISW2 = 0.0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V –– 6 6 m V tONSW2 Turn-on time
  • Enable to 90% of end value
  • I SW2 = 0.0 mA
  • DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V – – 550 µs fSW2 Switching frequency
  • SW2FREQ[1:0] = 00
  • SW2FREQ[1:0] = 01
  • SW2FREQ[1:0] = 10 1.0 2.0 4.0 MHz
  • V IN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
  • PFM, 3.15 V, 1.0 mA
  • PFM, 3.15 V, 50 mA
  • APS, PWM, 3.15 V, 400 mA
  • APS, PWM, 3.15 V, 600 mA
  • APS, PWM, 3.15 V, 1000 mA
  • APS, PWM, 3.15 V, 2000 mA ΔV SW2 Output ripple – 10 – mV VSW2LIR Line regulation (APS, PWM) – – 20 mV VSW2LOR DC load regulation (APS, PWM) – – 20 mV VSW2LOTR Transient load regulation
  • Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ μs
  • Overshoot
  • Undershoot mV ISW2Q Quiescent current
  • PFM mode
  • APS mode (low output voltage settings)
  • APS mode (high output voltage settings) 145 305 µA R ONSW2P SW2 P-MOSFET RDS(on)
  • at VIN = VINSW2 = 3.3 V – 190 209 m Ω RONSW2N SW2 N-MOSFET RDS(on)
  • at VIN = VINSW2 = 3.3 V – 212 255 m Ω ISW2PQ SW2 P-MOSFET leakage current
  • VIN = VINSW2 = 4.5 V –– 1 2 µ A ISW2NQ SW2 N-MOSFET leakage current
  • VIN = VINSW2 = 4.5 V –– 4 . 0 µ A RSW2DIS Discharge resistance – 600 – Ω Notes 50. When output is set to > 2.6 V the output follows the input down when V IN gets near 2.8 V. 51. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance). 52. Applies to NP, F9, and FA Indus trial versions only (ANES suffix)

Table 63. SW2 electrical characteristics (continued) characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

58 NXP Semiconductors

Figure 19. sw2 Efficiency Waveforms: VIN = 4.2 V; VOUT = 3.0 V; consumer version Figure 20. sw2 efficiency waveforms: vin = 4.2 v; vout = 3.0 v; Extended Industrial Version

6.4.4.4.4 SW3A/B

  • A single phase
  • A dual phase
  • Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 64 shows the options for the SW3CFG[1:0] bits. 100 0.1 1 10 100 1000 Eff iciency (% Load Current (mA) PFM 100 10 100 1000 10000 Eff iciency (% Load Current (mA) APS PWM Efficiency (%) Efficiency (%) 100 0.1 1 10 100 1000 Efficiency (% Load Current (mA) PFM 100 10 100 1000 10000 Eff iciency (% Load Current (mA) APS PWM Efficiency (%) Efficiency (%)

6.4.4.4.5 SW3A/B single phase

is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. Figure 21. SW3A/B single phase block diagram Table 64. SW3 configuration

00 A/B single phase

01 A/B single phase

10 A/B dual phase

11 A/B independent

60 NXP Semiconductors

6.4.4.4.6 SW3A/B dual phase

registers of both regulators, SW3A and SW3B, must be identically set. In this configuration, the regulators switch 180 degrees apart. Figure 22. SW3A/B dual phase block diagram

6.4.4.4.7 SW3A - SW3B independent outputs

Figure 23. SW3A/B independent output block diagram

6.4.4.4.8 SW3A/B Setup and Control Registers

with 50 mV increments, as determined by bits SW3x[5:0]. and the lower range be used for voltages from 0.400 V to 1.975 V. Note: Voltage set points of 0.6 V and below are not supported.

62 NXP Semiconductors

Table 65. SW3A/B output voltage configuration

  1. For voltages less than 2.0 V, only use set points 0 to 63.

64 NXP Semiconductors

on Tables 67 through Table 76. Table 66. SW3AB register summary Table 67. Register SW3AVOLT - ADDR 0x3C all possible configurations. (independent) or SW3A/B (single/dual phase). Table 65 for all possible configurations. Table 68. Register SW3ASTBY - ADDR 0x3D

Table 69. Register SW3AOFF - ADDR 0x3E on bit SW3A[6] during OTP or TBB configuration. See Table 65 for all possible configurations. Table 70. Register SW3AMODE - ADDR 0x3F dual phase) switching operation mode. See Table 30 for all possible configurations. (single/dual phase) when in sleep mode.

  • 0 = OFF
  • 1 = PFM UNUSED 7:6 – 0x00 unused

Table 71. Register SW3ACONF - ADDR 0x40

  • 0 = High level current limit
  • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW3AFREQ 3:2 R/W 0x00 SW3A switching frequency selector. See Table 38. SW3APHASE 5:4 R/W 0x00 SW3A phase clock selection. See Table 36. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 35.

Table 72. Register SW3BVOLT - ADDR 0x43 all possible configurations.

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Table 73. Register SW3BSTBY - ADDR 0x44 Table 74. Register SW3BOFF - ADDR 0x45 Table 75. Register SW3BMODE - ADDR 0x46

  • 0 = OFF
  • 1 = PFM UNUSED 7:6 – 0x00 unused

Table 76. Register SW3BCONF - ADDR 0x47

  • 0 = High level Current limit
  • 1 = Low level Current limit UNUSED 1 R/W 0x00 Unused SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 38. SW3BPHASE 5:4 R/W 0x00 SW3B phas e clock selection. See Table 36. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 35.

6.4.4.4.9 SW3A/B external components

6.4.4.4.10 SW3A/B specifications

Table 77. SW3A/B external component requirements

  1. Use X5R or X7R capacitors.

Table 78. SW3A/B electrical characteristics and 25 °C, unless otherwise noted.

  • PWM, APS 2.8 V < V IN < 4.5 V, 0 < ISW3x < ISW3xMAX
  • 0.625 V < VSW3x < 0.85 V
  • 0.875 V < VSW3x < 1.975 V
  • 2.0 V < VSW3x < 3.3 V
  • PFM , steady state (2.8 V < V IN < 4.5 V, 0 < ISW3x < 50 mA)
  • 0.625 V < VSW3x < 0.675 V
  • 0.7 V < VSW3x < 0.85 V
  • 0.875 V < VSW3x < 1.975 V
  • 2.0 V < VSW3x < 3.3 V -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV I SW3x Rated output load current
  • 2.8 V < V IN < 4.5 V, 0.625 V < VSW3x < 3.3 V
  • PWM, APS mode single/dual phase
  • PWM, APS mode independent (per phase) 2500 1250 mA (56)

68 NXP Semiconductors

  • Single phase (curr ent through inductor)
  • SW3xILIM = 0
  • SW3xILIM = 1
  • Independent mode or dual phase (current through inductor per phase)
  • SW3xILIM = 0
  • SW3xILIM = 1 3.5 2.7 1.8 1.3 5.0 3.8 2.5 1.9 6.5 4.9 3.3 2.5 A VSW3xOSH Start-up overshoot
  • ISW3x = 0.0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V –– 6 6 m V tONSW3x Turn-on time
  • Enable to 90% of end value
  • I SW3x = 0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V – – 500 µs fSW3x Switching frequency
  • SW3xFREQ[1:0] = 00
  • SW3xFREQ[1:0] = 01
  • SW3xFREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW3AB Efficiency (single phase)
  • f SW3 = 2.0 MHz, LSW3x 1.0 μH
  • PFM, 1.5 V, 1.0 mA
  • PFM, 1.5 V, 50 mA
  • APS, PWM 1.5 V, 500 mA
  • APS, PWM 1.5 V, 750 mA
  • APS, PWM 1.5 V, 1250 mA
  • APS, PWM 1.5 V, 2500 mA ΔV SW3x Output ripple – 10 – mV VSW3xLIR Line regulation (APS, PWM) – – 20 mV VSW3xLOR DC load regulation (APS, PWM) – – 20 mV VSW3xLOTR Transient load regulation
  • Transient load = 0.0 mA to I SW3x/2, di/dt = 100 mA/μs
  • Overshoot
  • Undershoot mV ISW3xQ Quiescent current
  • PFM mode (single/dual phase)
  • APS mode (single/dual phase)
  • PFM mode (independent mode)
  • APS mode (SW3A independent mode)
  • APS mode (SW3B independent mode) 300 250 150 µA R ONSW3AP SW3A P-MOSFET RDS(on)
  • at VIN = VINSW3A = 3.3 V – 215 245 mΩ RONSW3AN SW3A N-MOSFET RDS(on)
  • at VIN = VINSW3A = 3.3 V – 258 326 mΩ

Table 78. SW3A/B electrical characteristics (continued) and 25 °C, unless otherwise noted.

Figure 24. SW3AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.5 V; consumer version

  • VIN = VINSW3A = 4.5 V –– 7 . 5 µ A ISW3ANQ SW3A N-MOSFET leakage current
  • VIN = VINSW3A = 4.5 V –– 2 . 5 µ A RONSW3BP SW3B P-MOSFET RDS(on)
  • at VIN = VINSW3B = 3.3 V – 215 245 mΩ RONSW3BN SW3B N-MOSFET RDS(on)
  • at VIN = VINSW3B = 3.3 V – 258 326 mΩ ISW3BPQ SW3B P-MOSFET leakage current
  • VIN = VINSW3B = 4.5 V –– 7 . 5 µ A ISW3BPQ SW3B N-MOSFET leakage current
  • VIN = VINSW3B = 4.5 V –– 2 . 5 µ A RSW3xDIS Discharge resistance – 600 – Ω Notes 55. When output is set to > 2.6 V the output follows the input down when V IN gets near 2.8 V. 56. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW3x - VSW3x) = ISW3x* (DCR of inductor +RONSW3xP + PCB trace resistance).

and 25 °C, unless otherwise noted.

70 NXP Semiconductors

Figure 25. SW3AB efficiency waveforms: VIN = 4.2 V; VOUT = 1.5 V; extended industrial version

6.4.4.5 SW4

PFM, APS, and PWM, described on Table 30 and configured by the SW4MODE[3:0] bits, as shown in Table 31. be configured by use of VTT bit in the OTP_SW4_CONFIG register. Figure 26 shows the block diagram and the external component connections for the SW4 regulator. Figure 26. SW4 block diagram

6.4.4.5.1 SW4 setup and control registers

6.1.2 One time programmability (OTP), page 21 for detailed information on OTP configuration. read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP reg isters. to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits. lower range be used for voltages from 0.400 V to 1.975 V.

the output voltage range remains the same on all three operating modes. Table 79 shows the output voltage coding valid for SW4. Note: Voltage set points of 0.6 V and below are not supported, except in the VTT mode. Table 79. SW4 output voltage configuration

72 NXP Semiconductors

  1. For voltages less than 2.0 V, only use set points 0 to 63.

Table 79. SW4 output voltage configuration (continued)

is provided in Tables 81 to Table 85. Table 80. SW4 register summary Table 81. Register SW4VOLT - ADDR 0x4A Sets the operating output voltage range for SW4. Table 79 for all possible configurations. Table 82. Register SW4STBY - ADDR 0x4B Table 83. Register SW4OFF - ADDR 0x4C SW4OFF 5:0 R/W 0x00 Sets the SW4 output voltage during sleep mode. See Table 79 for all possible configurations.

74 NXP Semiconductors

6.4.4.5.2 SW4 external components

Table 84. Register SW4MODE - ADDR 0x4D SW4MODE 3:0 R/W 0x08 Sets the SW4 switching operation mode. See Table 30 for all possible configurations.

  • 0 = OFF
  • 1 = PFM UNUSED 7:6 – 0x00 unused

Table 85. Register SW4CONF - ADDR 0x4E

  • 0 = High level current limit
  • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW4FREQ 3:2 R/W 0x00 SW4 switching frequency selector. See Table 38. SW4PHASE 5:4 R/W 0x00 SW4 phase clock selection. See Table 36. SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 35.

Table 86. SW4 external component requirements

  1. Use X5R or X7R capacitors

6.4.4.5.3 SW4 specifications

Table 87. SW4 electrical characteristics and 25 °C, unless otherwise noted.

  • Normal operation
  • VTT mode Table 79 V SW3AFB/2 V VSW4ACC Output voltage accuracy
  • PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW4 < 1.0 A
  • 0.625 V < VSW4 < 0.85 V
  • 0.875 V < VSW4 < 1.975 V
  • 2.0 V < VSW4 < 3.3 V
  • PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW4 < 50 mA
  • 0.625 V < VSW4 < 0.675 V
  • 0.7 V < VSW4 < 0.85 V
  • 0.875 V < VSW4 < 1.975 V
  • 2.0 V < VSW4 < 3.3 V
  • VTT Mode , 2.8 V < V IN < 4.5 V, 0 < ISW4 < 1.0 A -25 -3.0 -6.0 -65 -45 -3.0 -3.0 -40 3.0 6.0 3.0 3.0 mV mV mV mV I SW4 Rated output load current
  • 2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 3.3 V – – 1000 mA (60) ISW4LIM Current limiter peak current detection Current through inductor
  • SW4ILIM = 0
  • SW4ILIM = 1 1.4 1.0 2.0 1.5 3.0 2.4 A V SW4OSH Start-up overshoot
  • ISW4 = 0.0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V –– 6 6 m V tONSW4 Turn-on time
  • Enable to 90% of end value
  • I SW4 = 0.0 mA
  • DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V – – 500 µs fSW4 Switching frequency
  • SW4FREQ[1:0] = 00
  • SW4FREQ[1:0] = 01
  • SW4FREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW4 Efficiency
  • f SW4 = 2.0 MHz, LSW4 = 1.0 μH
  • PFM, 1.8 V, 1.0 mA
  • PFM, 1.8 V, 50 mA
  • APS, PWM 1.8 V, 200 mA
  • APS, PWM 1.8 V, 500 mA
  • APS, PWM 1.8 V, 1000 mA
  • PWM 0.75 V, 200 mA
  • PWM 0.75 V, 500 mA
  • PWM 0.75 V, 1000 mA ΔV SW4 Output ripple – 10 – mV

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Figure 27. SW4 efficiency waveforms: VIN = 4.2 V; VOUT = 1.8 V; consumer version

  • Transient load = 0.0 mA to 500 mA, di/dt = 100 mA/ μs
  • Overshoot
  • Undershoot mV ISW4Q Quiescent current
  • PFM mode
  • APS mode 145 µA R ONSW4P SW4 P-MOSFET RDS(on)
  • at VIN = VINSW4 = 3.3 V – 236 274 m Ω RONSW4N SW4 N-MOSFET RDS(on)
  • at VIN = VINSW4 = 3.3 V – 293 378 m Ω ISW4PQ SW4 P-MOSFET leakage current
  • VIN = VINSW4 = 4.5 V –– 6 . 0 µ A ISW4NQ SW4 N-MOSFET leakage current
  • VIN = VINSW4 = 4.5 V –– 2 . 0 µ A RSW4DIS Discharge resistance – 600 – Ω Notes 59. When output is set to > 2.6 V the output follows the input down when V IN gets near 2.8 V. 60. The higher output voltages available depend on the voltage dr op in the conduction path as given by the following equation: (VINSW4 - VSW4) = ISW4* (DCR of inductor +RONSW4P + PCB trace resistance).

Table 87. SW4 electrical characteristics (continued) and 25 °C, unless otherwise noted.

Figure 28. SW4 efficiency waveforms: VIN = 4.2 V; VOUT = 1.8 V; extended industrial version

6.4.5 Boost regulator

integrated on-chip. Figure 29 shows the block diagram and component connection for the boost regulator. Figure 29. Boost regulator architecture

78 NXP Semiconductors

6.4.5.1 SWBST setup and control

if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.

6.4.5.2 SWBST external components

Table 88. Register SWBSTCTL - ADDR 0x66

  • 00 = 5.000 V
  • 01 = 5.050 V
  • 10 = 5.100 V
  • 11 = 5.150 V SWBST1MODE 3:2 R 0x02 Set the Switching mode on normal operation
  • 00 = OFF
  • 01 = PFM
  • 10 = Auto (Default) (61)
  • 11 = APS UNUSED 4 – 0x00 unused SWBST1STBYMODE 6:5 R/W 0x02 Set the switching mode on standby
  • 00 = OFF
  • 01 = PFM
  • 10 = Auto (Default) (61)
  • 11 = APS UNUSED 7 – 0x00 unused Notes 61. In auto mode, the controller automatically switches between PFM and APS modes depending on the load current. The SWBST regulator starts up by default in the auto mode if SWBST is part of the startup sequence.

Table 89. SWBST external component requirements

  1. Use X5R or X7R capacitors.

6.4.5.3 SWBST specifications

Table 90. SWBST Electrical Specifications ISWBST = 100 mA, and 25 °C, unless otherwise noted.

  • 2.8 V ≤ VIN ≤ 4.5 V
  • 0 < ISWBST < ISWBSTMAX -4.0 – 3.0 % ΔVSWBST Output ripple
  • 2.8 V ≤ VIN ≤ 4.5 V
  • 0 < ISWBST < ISWBSTMAX, excluding reverse recovery of Schottky diode – – 120 mV Vp-p VSWBSTLOR DC load regulation
  • 0 < ISWBST < ISWBSTMAX –0 . 5 – m V / m A VSWBSTLIR DC line regulation
  • 2.8 V ≤ VIN ≤ 4.5 V, ISWBST = ISWBSTMAX – 50 – mV ISWBST Continuous load current
  • 2.8 V ≤ VIN ≤ 3.0 V
  • 3.0 V ≤ VIN ≤ 4.5 V 500 600 mA ISWBSTQ Quiescent current
  • Auto – 222 289 μA RDSONBST MOSFET on resistance – 206 306 m Ω ISWBSTLIM Peak current limit 1400 2200 3200 mA (63) VSWBSTOSH Start-up overshoot
  • ISWBST = 0.0 mA – – 500 mV VSWBSTTR Transient load response
  • ISWBST from 1.0 mA to 100 mA in 1.0 µs
  • Maximum transient amplitude – – 300 mV VSWBSTTR Transient load response
  • ISWBST from 100 mA to 1.0 mA in 1.0 µs
  • Maximum transient amplitude – – 300 mV tSWBSTTR Transient load response
  • ISWBST from 1.0 mA to 100 mA in 1.0 µs
  • Time to settle 80% of transient – – 500 µs tSWBSTTR Transient load response
  • ISWBST from 100 mA to 1.0 mA in 1.0 µs
  • Time to settle 80% of transient –– 2 0 m s ISWBSTHSQ NMOS Off leakage
  • SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00 –1 . 0 5 . 0 µ A tONSWBST Turn-on time
  • Enable to 90% of VSWBST, ISWBST = 0.0 mA –– 2 . 0 m s fSWBST Switching frequency – 2.0 – MHz ηSWBST Efficiency
  • ISWBST = ISWBSTMAX –8 6–% Notes 63. Only in auto mode.

80 NXP Semiconductors

6.4.6 LDO regulators description

and references block description, page 24 for further information on the internal reference voltages. recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is disabled, the output is discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low. Figure 30. General LDO block diagram

6.4.6.1 Transient response waveforms

and load response refers to the overshoot, or undershoot only, excluding the DC shift. Figure 31. Transient waveforms

6.4.6.2 Short-circuit protection

in an overload condition regardless of the state of the REGSCPEN bit. See Table 91 for SCP behavior configuration.

6.4.6.3 LDO regulator control

according to Table 92 for VGEN1 and VGEN2; and uses the voltage set point on Table 93 for VGEN3 through VGEN6. Table 91. Short-circuit behavior

0 Current limit

1 Shutdown

Table 92. VGEN1, VGEN2 output voltage configuration Table 93. VGEN3/ 4/ 5/ 6 output voltage configuration

82 NXP Semiconductors

presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output. Table 94. LDO control

  1. STANDBY refers to a standby event as described earlier.

Table 95. Register VGEN1CTL - ADDR 0x6C VGEN1 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 92 for all possible configurations.

  • 0 = OFF
  • 1 = ON VGEN1STBY 5 R/W 0x00 Set VGEN1 output state when in standby. Refer to Table 94. VGEN1LPWR 6 R/W 0x00 Enable low-power mode for VGEN1. Refer to Table 94. UNUSED 7 – 0x00 unused

Table 93. VGEN3/ 4/ 5/ 6 output voltage configuration (continued)

Table 96. Register VGEN2CTL - ADDR 0x6D VGEN2 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 92 for all possible configurations.

  • 0 = OFF
  • 1 = ON VGEN2STBY 5 R/W 0x00 Set VGEN2 output state when in standby. Refer to Table 94. VGEN2LPWR 6 R/W 0x00 Enable low-power mode for VGEN2. Refer to Table 94. UNUSED 7 – 0x00 unused

Table 97. Register VGEN3CTL - ADDR 0x6E VGEN3 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 93 for all possible configurations.

  • 0 = OFF
  • 1 = ON VGEN3STBY 5 R/W 0x00 Set VGEN3 output state when in standby. Refer to Table 94. VGEN3LPWR 6 R/W 0x00 Enable low-power mode for VGEN3. Refer to Table 94. UNUSED 7 – 0x00 unused

Table 98. Register VGEN4CTL - ADDR 0x6F VGEN4 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 93 for all possible configurations.

  • 0 = OFF
  • 1 = ON VGEN4STBY 5 R/W 0x00 Set VGEN4 output state when in standby. Refer to Table 94. VGEN4LPWR 6 R/W 0x00 Enable low-power mode for VGEN4. Refer to Table 94. UNUSED 7 – 0x00 unused

84 NXP Semiconductors

6.4.6.4 External components

Table 101 lists the typical component values for the general purpose LDO regulators. Table 99. Register VGEN5CTL - ADDR 0x70 VGEN5 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 93 for all possible configurations.

  • 0 = OFF
  • 1 = ON VGEN5STBY 5 R/W 0x00 Set VGEN5 output state when in standby. Refer to Table 94. VGEN5LPWR 6 R/W 0x00 Enable low-power mode for VGEN5. Refer to Table 94. UNUSED 7 – 0x00 unused

Table 100. Register VGEN6CTL - ADDR 0x71 VGEN6 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 93 for all possible configurations.

  • 0 = OFF
  • 1 = ON VGEN6STBY 5 R/W 0x00 Set VGEN6 output state when in standby. Refer to Table 94. VGEN6LPWR 6 R/W 0x00 Enable low-power mode for VGEN6. Refer to Table 94. UNUSED 7 – 0x00 unused Table 101. LDO external components Regulator Output capacitor (μF)(65) VGEN1 2.2 VGEN2 4.7 VGEN3 2.2 VGEN4 4.7 VGEN5 2.2 VGEN6 2.2 Notes 65. Use X5R/X7R ceramic capacitors.

6.4.6.5 LDO specifications

6.4.6.5.1 VGEN1

Table 102. VGEN1 electrical characteristics IGEN1 = 10 mA, and 25 °C, unless otherwise noted.

  • 1.75 V < VIN1 < 3.4 V
  • 0.0 mA < IGEN1 < 100 mA
  • VGEN1[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN1LOR Load regulation
  • (VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA)
  • For any 1.75 V < VIN1 < 3.4 V –0 . 1 5– m V / m A VGEN1LIR Line regulation
  • (VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V)
  • For any 0.0 mA < IGEN1 < 100 mA –0 . 3 0– m V / m A IGEN1LIM Current limit
  • IGEN1 when VGEN1 is forced to VGEN1NOM/2 122 167 200 mA IGEN1OCP Overcurrent protection threshold
  • IGEN1 required to cause the SCP function to disable LDO when REGSCPEN = 1 115 – 200 mA IGEN1Q Quiescent current
  • No load, change in IVIN and IVIN1
  • When VGEN1 enabled –1 4– μA VGEN1 AC and transient PSRRVGEN1 PSRR
  • I GEN1 = 75 mA, 20 Hz to 20 kHz
  • VGEN1[3:0] = 0000 - 1101
  • VGEN1[3:0] = 1110, 1111 dB (66) NOISEVGEN1 Output noise density
  • VIN1 = 1.75 V, IGEN1 = 75 mA
  • 100 Hz – <1.0 kHz
  • 1.0 kHz – <10 kHz
  • 10 kHz – 1.0 MHz -108 -118 -124 -100 -108 -112 dBV/ √Hz SLWR VGEN1 Turn-on slew rate
  • 10% to 90% of end value
  • 1.75 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA
  • VGEN1[3:0] = 0000 to 0111
  • VGEN1[3:0] = 1000 to 1111 12.5 16.5 mV/μs GEN1tON Turn-on time
  • Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
  • IGEN1 = 0.0 mA 60 – 500 μs

86 NXP Semiconductors

6.4.6.5.2 VGEN2

  • Disable to 10% of initial value, VIN1 = 1.75 V
  • IGEN1 = 0.0 mA –– 1 0 m s GEN1OSHT Start-up overshoot VGEN1LOTR Transient load response
  • V IN1 = 1.75 V, 3.4 V
  • IGEN1 = 10 mA to 100 mA in 1.0 μs. Peak of overshoot or undershoot of VGEN1 with respect to final value
  • Refer to Figure 31 –– 3 . 0 % VGEN1LITR Transient line response
  • I GEN1 = 75 mA
  • VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN1[3:0] = 0000 to 1101
  • VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for VGEN1[3:0] = 1110, 1111
  • Refer to Figure 31 –5 . 0 8 . 0 m V Notes 66. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test.

Table 103. VGEN2 electrical characteristics IGEN2 = 10 mA and 25 °C, unless otherwise noted.

  • 1.75 V < VIN1 < 3.4 V
  • 0.0 mA < IGEN2 < 250 mA
  • VGEN2[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN2LOR Load regulation
  • (VGEN2 at IGEN2 = 250 mA) - (VGEN2 at IGEN2 = 0.0 mA)
  • For any 1.75 V < VIN1 < 3.4 V –0 . 0 5– m V / m A VGEN2LIR Line regulation
  • (VGEN2 at VIN1 = 3.4 V) - (VGEN2 at VIN1 = 1.75 V)
  • For any 0.0 mA < IGEN2 < 250 mA –0 . 5 0– m V / m A

Table 102. VGEN1 electrical characteristics (continued) IGEN1 = 10 mA, and 25 °C, unless otherwise noted.

  • IGEN2 when VGEN2 is forced to VGEN2NOM/2
  • MMPF0100
  • MMPF0100A 333 305 417 417 510 510 mA I GEN2OCP Overcurrent protection threshold
  • IGEN2 required to cause the SCP function to disable LDO when REGSCPEN = 1
  • MMPF0100
  • MMPF0100A 300 290 500 500 mA I GEN2Q Quiescent current
  • No load, change in IVIN and IVIN1
  • When VGEN2 enabled –1 6– μA VGEN2 AC and transient PSRRVGEN2 PSRR
  • I GEN2 = 187.5 mA, 20 Hz to 20 kHz
  • VGEN2[3:0] = 0000 - 1101
  • VGEN2[3:0] = 1110, 1111 dB (67) NOISEVGEN2 Output noise density
  • V IN1 = 1.75 V, IGEN2 = 187.5 mA
  • 100 Hz – <1.0 kHz
  • 1.0 kHz – <10 kHz
  • 10 kHz – 1.0 MHz -108 -118 -124 -100 -108 -112 dBV/√Hz SLWR VGEN2 Turn-on slew rate
  • 10% to 90% of end value
  • 1 . 7 5 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA
  • VGEN2[3:0] = 0000 to 0111
  • VGEN2[3:0] = 1000 to 1111 12.5 16.5 mV/μs GEN2tON Turn-on time
  • Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
  • IGEN2 = 0.0 mA 60 – 500 μs GEN2tOFF Turn-off time
  • Disable to 10% of initial value, VIN1 = 1.75 V
  • IGEN2 = 0.0 mA –– 1 0 m s GEN2OSHT Start-up overshoot VGEN2LOTR Transient load response
  • VIN1 = 1.75 V, 3.4 V
  • IGEN2 = 25 to 250 mA in 1.0 μs
  • Peak of overshoot or undershoot of VGEN2 with respect to final value
  • Refer to Figure 31 –– 3 . 0 %

IGEN2 = 10 mA and 25 °C, unless otherwise noted.

88 NXP Semiconductors

6.4.6.5.3 VGEN3

  • IGEN2 = 187.5 mA
  • VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN2[3:0] = 0000 to 1101
  • VIN1INITIAL = VGEN2+0.3 V to VIN1FINAL = VGEN2+0.8 V for VGEN2[3:0] = 1110, 1111
  • Refer to Figure 31 –5 . 0 8 . 0 m V Notes 67. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test.

Table 104. VGEN3 electrical characteristics IGEN3 = 10 mA, and 25 °C, unless otherwise noted.

  • 1.8 V ≤ VGEN3NOM ≤ 2.5 V
  • 2.6 V ≤ VGEN3NOM ≤ 3.3 V 2.8 VGEN3NO M+ 0.250 3.6 3.6 (68) VGEN3NOM Nominal output voltage – Table 93 –V IGEN3 Operating load current 0.0 – 100 mA VGEN3 DC VGEN3TOL Output voltage tolerance
  • VIN2MIN < VIN2 < 3.6 V
  • 0.0 mA < IGEN3 < 100 mA
  • VGEN3[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN3LOR Load regulation
  • (VGEN3 at IGEN3 = 100 mA) - (VGEN3 at IGEN3 = 0.0 mA)
  • For any VIN2MIN < VIN2 < 3.6 V –0 . 0 7– m V / m A VGEN3LIR Line regulation
  • (VGEN3 at VIN2 = 3.6 V) - (VGEN3 at VIN2MIN )
  • For any 0.0 mA < IGEN3 < 100 mA –0 . 8– m V / m A IGEN3LIM Current limit
  • IGEN3 when VGEN3 is forced to VGEN3NOM/2 127 167 200 mA IGEN3OCP Overcurrent protection threshold
  • IGEN3 required to cause the SCP function to disable LDO when REGSCPEN = 1 1 2 0–2 0 0 m A IGEN3Q Quiescent current
  • No load, Change in IVIN and IVIN2
  • When VGEN3 enabled –1 3– μA

IGEN2 = 10 mA and 25 °C, unless otherwise noted.

  • I GEN3 = 75 mA, 20 Hz to 20 kHz
  • VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
  • VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V dB (69) NOISEVGEN3 Output noise density
  • V IN2 = VIN2MIN, IGEN3 = 75 mA
  • 100 Hz – <1.0 kHz
  • 1.0 kHz – <10 kHz
  • 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN3 Turn-on slew rate
  • 10% to 90% of end value
  • V I N 2MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA
  • VGEN3[3:0] = 0000 to 0011
  • VGEN3[3:0] = 0100 to 0111
  • VGEN3[3:0] = 1000 to 1011
  • VGEN3[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs GEN3 tON Turn-on time
  • Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
  • IGEN3 = 0.0 mA 60 – 500 μs GEN3tOFF Turn-off time
  • Disable to 10% of initial value, VIN2 = VIN2MIN
  • IGEN3 = 0.0 mA –– 1 0 m s GEN3OSHT Start-up overshoot
  • VIN2 = VIN2MIN, 3.6 V, IGEN3 = 0.0 mA –1 . 0 2 . 0 % VGEN3LOTR Transient load response
  • VIN2 = VIN2MIN, 3.6 V
  • IGEN3 = 10 to 100 mA in 1.0μs
  • Peak of overshoot or undershoot of VGEN3 with respect to final value. Refer to Figure 31 –– 3 . 0 % VGEN3LITR Transient line response
  • IGEN3 = 75 mA
  • VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for GEN3[3:0] = 0000 to 0111
  • VIN2INITIAL = VGEN3+0.3 V to VIN2FINAL = VGEN3+0.8 V for VGEN3[3:0] = 1000 to 1010
  • VIN2INITIAL = VGEN3+0.25 V to VIN2FINAL = 3.6 V for VGEN3[3:0] = 1011 to 1111
  • Refer to Figure 31 –5 . 0 8 . 0 m V Notes 68. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper regulation due to the dropout voltage generated through the internal LDO transistor. 69. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.

Table 104. VGEN3 electrical characteristics (continued) IGEN3 = 10 mA, and 25 °C, unless otherwise noted.

90 NXP Semiconductors

6.4.6.5.4 VGEN4

Table 105. VGEN4 electrical characteristics IGEN4 = 10 mA, and 25 °C, unless otherwise noted.

  • 1.8 V ≤ VGEN4NOM ≤ 2.5 V
  • 2.6 V ≤ VGEN4NOM ≤ 3.3 V 2.8 VGEN4NO M+ 0.250 3.6 3.6 (70) VGEN4NOM Nominal output voltage – Table 93 –V IGEN4 Operating load current 0.0 – 350 mA VGEN4 DC VGEN4TOL Output voltage tolerance
  • VIN2MIN < VIN2 < 3.6 V
  • 0.0 mA < IGEN4 < 350 mA
  • VGEN4[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN4LOR Load regulation
  • (VGEN4 at IGEN4 = 350 mA) - (VGEN4 at IGEN4 = 0.0 mA )
  • For any VIN2MIN < VIN2 < 3.6 V – 0.07 – mV/mA VGEN4LIR Line regulation
  • (VGEN4 at 3.6 V) - (VGEN4 at VIN2MIN)
  • For any 0.0 mA < IGEN4 < 350 mA – 0.80 – mV/mA IGEN4LIM Current limit
  • IGEN4 when VGEN4 is forced to VGEN4NOM/2 435 584.5 700 mA IGEN4OCP Overcurrent protection threshold
  • IGEN4 required to cause the SCP function to disable LDO when REGSCPEN = 1 420 – 700 mA IGEN4Q Quiescent current
  • No load, Change in IVIN and IVIN2
  • When VGEN4 enabled –1 3– μA VGEN4 AC and transient PSRRVGEN4 PSRR
  • I GEN4 = 262.5 mA, 20 Hz to 20 kHz
  • VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
  • VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V dB (71) NOISEVGEN4 Output noise density
  • V IN2 = VIN2MIN, IGEN4 = 262.5 mA
  • 100 Hz – <1.0 kHz
  • 1.0 kHz – <10 kHz
  • 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN4 Turn-on slew rate
  • 10% to 90% of end value
  • V I N 2MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA
  • VGEN4[3:0] = 0000 to 0011
  • VGEN4[3:0] = 0100 to 0111
  • VGEN4[3:0] = 1000 to 1011
  • VGEN4[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs

6.4.6.5.5 VGEN5

  • Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
  • IGEN4 = 0.0 mA 60 – 500 μs GEN4tOFF Turn-off time
  • Disable to 10% of initial value, VIN2 = VIN2MIN
  • IGEN4 = 0.0 mA –– 1 0 m s GEN4OSHT Start-up overshoot
  • VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA –1 . 0 2 . 0 % VGEN4LOTR Transient load response
  • VIN2 = VIN2MIN, 3.6 V
  • IGEN4 = 35 to 350 mA in 1.0 μs
  • Peak of overshoot or undershoot of VGEN4 with respect to final value. Refer to Figure 31 –– 3 . 0 % VGEN4LITR Transient line response
  • IGEN4 = 262.5 mA
  • VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for VGEN4[3:0] = 0000 to 0111
  • VIN2INITIAL = VGEN4+0.3 V to VIN2FINAL = VGEN4+0.8 V for VGEN4[3:0] = 1000 to 1010
  • VIN2INITIAL = VGEN4+0.25 V to VIN2FINAL = 3.6 V for VGEN4[3:0] = 1011 to 1111
  • Refer to Figure 31 –5 . 0 8 . 0 m V Notes 70. When the LDO output voltage is set above 2.6 V the minimum allo wed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 71. The PSRR of the regulators is measured wi th the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.

Table 106. VGEN5 electrical characteristics IGEN5 = 10 mA, and 25 °C, unless otherwise noted.

  • 1.8 V ≤ VGEN5NOM ≤ 2.5 V
  • 2.6 V ≤ VGEN5NOM ≤ 3.3 V 2.8 VGEN5NO M+ 0.250 4.5 4.5 (72) VGEN5NOM Nominal output voltage – Table 93 –V IGEN5 Operating load current 0.0 – 100 mA

Table 105. VGEN4 electrical characteristics (continued) IGEN4 = 10 mA, and 25 °C, unless otherwise noted.

92 NXP Semiconductors

  • VIN3MIN < VIN3 < 4.5 V
  • 0.0 mA < IGEN5 < 100 mA
  • VGEN5[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN5LOR Load regulation
  • (VGEN5 at IGEN5 = 100 mA) - (VGEN5 at IGEN5 = 0.0 mA)
  • For any VIN3MIN < VIN3 < 4.5 mV –0 . 1 0– m V / m A VGEN5LIR Line regulation
  • (VGEN5 at VIN3 = 4.5 V) - (VGEN5 at VIN3MIN)
  • For any 0.0 mA < IGEN5 < 100 mA –0 . 5 0– m V / m A IGEN5LIM Current limit
  • IGEN5 when VGEN5 is forced to VGEN5NOM/2 122 167 200 mA IGEN5OCP Overcurrent protection threshold
  • IGEN5 required to cause the SCP function to disable LDO when REGSCPEN = 1 120 – 200 mA IGEN5Q Quiescent current
  • No load, Change in IVIN and IVIN3
  • When VGEN5 enabled –1 3– μA VGEN5 AC and transient PSRRVGEN5 PSRR
  • I GEN5 = 75 mA, 20 Hz to 20 kHz
  • VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
  • VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V dB (73) NOISEVGEN5 Output noise density
  • V IN3 = VIN3MIN, IGEN5 = 75 mA
  • 100 Hz – <1.0 kHz
  • 1.0 kHz – <10 kHz
  • 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN5 Turn-on slew rate
  • 10% to 90% of end value
  • V I N 3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA
  • VGEN5[3:0] = 0000 to 0011
  • VGEN5[3:0] = 0100 to 0111
  • VGEN5[3:0] = 1000 to 1011
  • VGEN5[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs GEN5 tON Turn-on time
  • Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
  • IGEN5 = 0.0 mA 60 – 500 μs GEN5tOFF Turn-off time
  • Disable to 10% of initial value, VIN3 = VIN3MIN
  • IGEN5 = 0.0 mA –– 1 0 m s GEN5OSHT Start-up overshoot
  • VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA –1 . 0 2 . 0 %

Table 106. VGEN5 electrical characteristics (continued) IGEN5 = 10 mA, and 25 °C, unless otherwise noted.

6.4.6.5.6 VGEN6

  • VIN3 = VIN3MIN, 4.5 V
  • IGEN5 = 10 to 100 mA in 1.0 μs
  • Peak of overshoot or undershoot of VGEN5 with respect to final value.
  • Refer to Figure 31 –– 3 . 0 % VGEN5LITR Transient line response
  • IGEN5 = 75 mA
  • VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN5[3:0] = 0000 to 0111
  • VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for VGEN5[3:0] = 1000 to 1111
  • Refer to Figure 31 -5 . 0 8 . 0 m V Notes 72. When the LDO output voltage is set above 2.6 V the minimum allo wed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 73. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.

Table 107. VGEN6 electrical characteristics IGEN6 = 10 mA, and 25 °C, unless otherwise noted.

  • 1.8 V ≤ VGEN6NOM ≤ 2.5 V
  • 2.6 V ≤ VGEN6NOM ≤ 3.3 V 2.8 VGEN6NO M+ 0.250 4.5 4.5 V — (74) VGEN6NOM Nominal output voltage – Table 93 –V IGEN6 Operating load current 0.0 – 200 mA VGEN6 DC VGEN6TOL Output voltage tolerance
  • VIN3MIN < VIN3 < 4.5 V
  • 0.0 mA < IGEN6 < 200 mA
  • VGEN6[3:0] = 0000 to 1111 -3.0 – 3.0 % VGEN6LOR Load regulation
  • (VGEN6 at IGEN6 = 200 mA) - (VGEN6 at IGEN6 = 0.0 mA)
  • For any VIN3MIN < VIN3 < 4.5 V –0 . 1 0– m V / m A VGEN6LIR Line regulation
  • (VGEN6 at VIN3 = 4.5 V) - (VGEN6 at VIN3MIN)
  • For any 0.0 mA < IGEN6 < 200 mA –0 . 5 0– m V / m A IGEN6LIM Current limit
  • IGEN6 when VGEN6 is forced to VGEN6NOM/2
  • MMPF0100
  • MMPF0100A 232 232 333 333 400 475 mA

IGEN5 = 10 mA, and 25 °C, unless otherwise noted.

94 NXP Semiconductors

  • IGEN6 required to cause the SCP function to disable LDO when REGSCPEN = 1
  • MMPF0100
  • MMPF0100A 220 220 400 475 mA I GEN6Q Quiescent current
  • No load, Change in IVIN and IVIN3
  • When VGEN6 enabled –1 3– μA VGEN6 AC and transient PSRRVGEN6 PSRR
  • I GEN6 = 150 mA, 20 Hz to 20 kHz
  • VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
  • VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V dB (75) NOISEVGEN6 Output noise density
  • V IN3 = VIN3MIN, IGEN6 = 150 mA
  • 100 Hz – <1.0 kHz
  • 1.0 kHz – <10 kHz
  • 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN6 Turn-on slew rate
  • 10% to 90% of end value
  • V I N 3MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA
  • VGEN6[3:0] = 0000 to 0011
  • VGEN6[3:0] = 0100 to 0111
  • VGEN6[3:0] = 1000 to 1011
  • VGEN6[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs GEN6 tON Turn-on time
  • Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
  • IGEN6 = 0.0 mA 60 – 500 μs GEN6tOFF Turn-off time
  • Disable to 10% of initial value, VIN3 = VIN3MIN
  • IGEN6 = 0.0 mA –– 1 0 m s GEN6OSHT Start-up overshoot
  • VIN3 = VIN3MIN, 4.5 V, IGEN6 = 0 mA –1 . 0 2 . 0 % VGEN6LOTR Transient load response
  • VIN3 = VIN3MIN, 4.5 V
  • IGEN6 = 20 to 200 mA in 1.0 μs
  • Peak of overshoot or undershoot of VGEN6 with respect to final value. Refer to Figure 31 –– 3 . 0 %

Table 107. VGEN6 electrical characteristics (continued) IGEN6 = 10 mA, and 25 °C, unless otherwise noted.

6.4.7 VSNVS LDO/switch

the switch, which is 40 mV at a rated maximum load current of 400 μA. certain conditions are met as described in Table 108. Figure 32. VSNVS supply switch architecture Table 108 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system.

  • IGEN6 = 150 mA
  • VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN6[3:0] = 0000 to 0111
  • VIN3INITIAL = VGEN6+0.3 V to VIN3FINAL = VGEN6+0.8 V for VGEN6[3:0] = 1000 to 1111
  • Refer to Figure 31 –5 . 0 8 . 0 m V Notes 74. When the LDO output voltage is set above 2.6 V the minimum al lowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 75. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.

IGEN6 = 10 mA, and 25 °C, unless otherwise noted.

2.25 V (VTL0) -

96 NXP Semiconductors

6.4.7.0.1 VSNVS control

The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in Table 109.

6.4.7.0.2 VSNVS external components

6.4.7.0.3 VSNVS specifications

Table 108. VSNVS modes of operation Table 109. Register VSNVSCTL - ADDR 0x6B

  • 000 = 1.0 V
  • 001 = 1.1 V
  • 010 = 1.2 V
  • 011 = 1.3 V
  • 100 = 1.5 V
  • 101 = 1.8 V
  • 110 = 3.0 V
  • 111 = RSVD UNUSED 7:3 – 0x00 unused Notes 76. Only valid when a valid input voltage is present.

Table 110. VSNVS external components Table 111. VSNVS electrical characteristics

  • Valid coin cell range
  • Valid V IN 1.8 2.25 3.3 4.5 V ISNVS Operating load current
  • VINMIN < VIN < VINMAX 5.0 – 400 μA
  • 5 . 0 μA < ISNVS < 400 μA (OFF)
  • 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
  • VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
  • 5 . 0 μA < ISNVS < 400 μA (ON)
  • 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
  • UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
  • 5 .0 μA < ISNVS < 400 μA (Coin Cell mode)
  • 2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110
  • 1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101] -5.0% -8.0% -5.0% -4.0% VCOIN-0.04 -8.0% 3.0 1.0 - 1.8 3.0 1.0 - 1.8 1.0 - 1.8 7.0% 7.0% 5.0% 4.0% VCOIN 7.0% V (77) VSNVSDROP Dropout voltage
  • VIN = VCOIN = 2.85 V, VSNVSVOLT[2:0] = 110, ISNVS = 400 μA –– 5 0 m V ISNVSLIM Current limit
  • MMPF0100
  • V IN > VTH1, VSNVSVOLT[2:0] = 110
  • VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101
  • VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101
  • MMPF0100A
  • V IN > VTH1, VSNVSVOLT[2:0] = 110
  • VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101
  • VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 750 500 480 1100 500 480 5900 5900 3600 6750 6750 4500 μA V TH0 VIN Threshold (coin cell powered to VIN powered) VIN going high with valid coin cell
  • VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.25 2.40 2.55 V VTL0 VIN threshold (VIN powered to coin cell powered) VIN going low with valid coin cell
  • VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.20 2.35 2.50 V VHYST1 VIN threshold hysteresis for VTH1-VTL1 5.0 – – mV VHYST0 VIN threshold hysteresis for VTH0-VTL0 5.0 – – mV VSNVSCROSS Output voltage during crossover
  • VSNVSVOLT[2:0] = 110
  • V COIN > 2.9 V
  • Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA
  • LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA 2.7 – – V (80) VSNVS AC and transient tONSNVS Turn-on time (load capacitor, 0.47 μF)
  • VIN > UVDET to 90% of VSNVS
  • VCOIN = 0.0 V, ISNVS = 5.0 μA
  • VSNVSVOLT[2:0] = 000 to 110 VSNVSOSH Start-up overshoot
  • VSNVSVOLT[2:0] = 000 to 110
  • I SNVS = 5.0 μA
  • dVIN/dt = 50 mV/μs –4 0 7 0 m V VSNVSLITR Transient line response ISNVS = 75% of ISNVSMAX
  • 3.2 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
  • 2.45 V < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101] – mV

Table 111. VSNVS electrical characteristics (continued)

98 NXP Semiconductors

6.4.7.1 Coin cell battery backup

placed from LICELL to ground under all circumstances.

6.4.7.1.1 Coin cell charger control

cell charging is not available as the main battery could be depleted unnecessarily. The coin cell charging stops when VIN is below UVDET.

  • VSNVSVOLT[2:0] = 110
  • 3.1 V (UVDETL)< V IN ≤ 4.5 V
  • ISNVS = 75 to 750 μA
  • VSNVSVOLT[2:0] = 000 to 101
  • 2.45 V < V IN ≤ 4.5 V
  • VTL0 > VIN, 1.8 V ≤ VCOIN ≤ 3.3 V
  • ISNVS = 40 to 400 μA
  • Refer to Figure 31 2.8 1.0 2.0 V VSNVS DC, switch VINSNVS Operating input voltage
  • Valid coin cell range 1.8 – 3.3 V ISNVS Operating load current 5.0 – 400 μA RDSONSNVS Internal switch RDS(on)
  • VCOIN = 2.6 V – – 100 Ω VTL1 VIN threshold (VIN powered to coin cell powered)
  • VSNVSVOLT[2:0] = 110 2.725 2.90 3.00 V (80) VTH1 VIN threshold (coin cell powered to VIN powered)
  • VSNVSVOLT[2:0] = 110 2.775 2.95 3.1 V Notes 77. For 1.8 V I SNVS limited to 100 μA for VCOIN < 2.1 V 78. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tr1 time. 79. From coin cell insertion to VSNVS =1.0 V, the delay time is typically 400 ms. 80. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause any malfunction. The i.MX 6’s RTC continues to operate through the transition, and as a worst case it may switch to the internal RC oscillator for a few clock cycles before switching back to the external crystal oscillator.

6.4.7.1.2 External components

6.4.7.1.3 Coin cell specifications

Table 112. Coin cell charger voltage

  1. Coin cell voltages selected based on the

type of LICELL used on the system. Table 113. Register COINCTL - ADDR 0x1A Coin cell charger output voltage selection. Table 114. Coin cell charger external components Table 115. Coin cell charger specifications

100 NXP Semiconductors

6.5 Control interface I 2C block description

the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.

6.5.1 I2C device ID

address; these bits take affect right away.

6.5.2 I 2C operation

is sent out unless a STOP command or NACK is received prior to completion. the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction. Figure 33. I2C write example Figure 34. I2C read example

6.5.3 Interrupt handling

existing interrupt bit, the INTB pin remains low. INTB pin goes low after unmasking. read only, and not latched or clearable. asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

6.5.4 Interrupt bit summary

Table 116. Interrupt, mask and sense bits

102 NXP Semiconductors

A full description of all interrupt, mask, and sense registers is provided in Tables 117 to 128.

  1. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].

Table 117. Register INTSTAT0 - ADDR 0x05 Table 118. Register INTMASK0 - ADDR 0x06 Table 116. Interrupt, mask and sense bits (continued)

Table 119. Register INTSENSE0 - ADDR 0x07

  • 0 = PWRON low
  • 1 = PWRON high LOWVINS 1 R 0 Low-voltage sense bit
  • 0 = VIN > 2.8 V
  • 1 = VIN ≤ 2.8 V THERM110S 2 R 0 110 °C thermal sense bit
  • 0 = Below threshold
  • 1 = Above threshold THERM120S 3 R 0 120 °C thermal sense bit
  • 0 = Below threshold
  • 1 = Above threshold THERM125S 4 R 0 125 °C thermal sense bit
  • 0 = Below threshold
  • 1 = Above threshold THERM130S 5 R 0 130 °C thermal sense bit
  • 0 = Below threshold
  • 1 = Above threshold UNUSED 6 – 0 unused VDDOTPS 7 R 00 Additional VDDOTP voltage sense pin
  • 0 = VDDOTP grounded
  • 1 = VDDOTP to VCOREDIG or greater

Table 120. Register INTSTAT1 - ADDR 0x08 Table 121. Register INTMASK1 - ADDR 0x09

104 NXP Semiconductors

Table 122. Register INTSENSE1 - ADDR 0x0A

  • 0 = Normal operation
  • 1 = Above current limit SW1BFAULTS 1 R 0 SW1B overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit SW1CFAULTS 2 R 0 SW1C overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit SW2FAULTS 3 R 0 SW2 overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit SW3AFAULTS 4 R 0 SW3A overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit SW3BFAULTS 5 R 0 SW3B overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit SW4FAULTS 6 R 0 SW4 overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit UNUSED 7 – 0 unused

Table 123. Register INTSTAT3 - ADDR 0x0E Table 124. Register INTMASK3 - ADDR 0x0F Table 121. Register INTMASK1 - ADDR 0x09 (continued)

Table 125. Register INTSENSE3 - ADDR 0x10

  • 0 = Normal operation
  • 1 = Above current limit UNUSED 6:1 – 0x00 unused OTP_ECCS 7 R 0 OTP error sense bit
  • 0 = No error detected
  • 1 = OTP error detected

Table 126. Register INTSTAT4 - ADDR 0x11 Table 127. Register INTMASK4 - ADDR 0x12 Table 128. Register INTSENSE4 - ADDR 0x13

  • 0 = Normal operation
  • 1 = Above current limit VGEN2FAULTS 1 R 0 VGEN2 overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit VGEN3FAULTS 2 R 0 VGEN3 overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit VGEN4FAULTS 3 R 0 VGEN4 overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit

106 NXP Semiconductors

6.5.5 Specific registers

6.5.5.1 IC and version identification

The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 129 to 131.

6.5.5.2 Embedded memory

  • 0 = Normal operation
  • 1 = Above current limit VGEN6FAULTS 5 R 0 VGEN6 overcurrent sense bit
  • 0 = Normal operation
  • 1 = Above current limit UNUSED 7:6 – 00 unused

Table 129. Register DEVICEID - ADDR 0x00 DEVICEID 3:0 R 0x00 Die version.

  • 0000 = PF0100 UNUSED 7:4 – 0x01 unused

Table 130. Register SILICON REV- ADDR 0x03

  • Pass 0.0 = 0000
  • .
  • .
  • Pass 0.15 = 1111 FULL_LAYER_REV 7:4 R 0x01 Represents the full mask revision
  • Pass 1.0 = 0001
  • .
  • .
  • Pass 15.0 = 1111

Table 131. Register FABID - ADDR 0x04 Table 128. Register INTSENSE4 - ADDR 0x13 (continued)

6.5.6 Register bitmap

pages, no write to the page register is necessary. Registers missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect.

  • R is read-only access
  • R/W is read and write access
  • RW1C is read and write access with write 1 to clear Reset: Reset signals are color coded based on the following legend. Default: The value after reset, as noted in the default column of the memory map.
  • Fixed defaults are explicitly declared as 0 or 1.
  • “X” corresponds to read/write bits which are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits which may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts.

Table 132. Register MEMA ADDR 0x1C Table 133. Register MEMB ADDR 0x1D Table 134. Register MEMC ADDR 0x1E Table 135. Register MEMD ADDR 0x1F

108 NXP Semiconductors

6.5.6.1 Register map

Table 136. Functional page

00 DeviceID R 8'b0001_0000

03 SILICONREVID R 8'b0001_0000

04 FABID R 8'b0000_0000

05 INTSTAT0 RW1C 8'b0000_0000

06 INTMASK0 R/W 8'b0011_1111

07 INTSENSE0 R 8'b00xx_xxxx

08 INTSTAT1 RW1C 8'b0000_0000

09 INTMASK1 R/W 8'b0111_1111

10 INTSENSE3 R 8'b0000_000x

11 INTSTAT4 RW1C 8'b0000_0000

12 INTMASK4 R/W 8'b0011_1111

13 INTSENSE4 R 8'b00xx_xxxx

20 SW1ABVOLT R/W/M 8'b00xx_xxxx

21 SW1ABSTBY R/W 8'b00xx_xxxx

22 SW1ABOFF R/W 8'b00xx_xxxx

23 SW1ABMODE R/W 8'b0000_1000

24 SW1ABCONF R/W 8'bxx00_xx00

30 SW1COFF R/W 8'b00xx_xxxx

31 SW1CMODE R/W 8'b0000_1000

32 SW1CCONF R/W 8'bxx00_xx00

35 SW2VOLT R/W 8'b0xxx_xxxx

36 SW2STBY R/W 8'b0xxx_xxxx

37 SW2OFF R/W 8'b0xxx_xxxx

Table 136. Functional page (continued)

110 NXP Semiconductors

38 SW2MODE R/W 8'b0000_1000

39 SW2CONF R/W 8'bxx01_xx00

40 SW3ACONF R/W 8'bxx10_xx00

43 SW3BVOLT R/W 8'b0xxx_xxxx

44 SW3BSTBY R/W 8'b0xxx_xxxx

45 SW3BOFF R/W 8'b0xxx_xxxx

46 SW3BMODE R/W 8'b0000_1000

47 SW3BCONF R/W 8'bxx10_xx00

66 SWBSTCTL R/W 8'b0xx0_10xx

70 VGEN5CTL R/W 8'b000x_xxxx

71 VGEN6CTL R/W 8'b000x_xxxx

Table 137. Extended page 1

80 OTP FUSE READ

84 OTP LOAD MASK R/W 8'b0000_0000

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Table 137. Extended page 1 (continued)

114 NXP Semiconductors

  1. In the MMPF0100 FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1

required to set all of the FUSE_PORx bits to be able to load the fuses. Table 138. Extended Page 2

81 SW1AB PWRSTG R/W 8'b1111_1111

82 PWRSTG RSVD R 8'b0000_0000

83 SW1C PWRSTG R 8'b1111_1111

84 SW2 PWRSTG R 8'b1111_1111

85 SW3A PWRSTG R 8'b1111_1111

86 SW3B PWRSTG R 8'b1111_1111

87 SW4 PWRSTG R 8'b0111_1111

88 PWRCTRL OTP

116 NXP Semiconductors

90 IO DRV R/W 8'b00xx_xxxx

Table 138. Extended Page 2 (continued)

  1. Do not write in reserved registers.

118 NXP Semiconductors

7 Typical applications

7.1 Introduction

references and additional components such as filters, refer to the individual sections.

7.1.1 Application diagram

Figure 35. Typical application schematic

7.1.2 Bill of materials

°C to 85 °C applications. Components are provided with an example part number; equivalent components may be used. Table 139. Bill of materials -40 °C to 85 °C applications (85)

1 Power management IC MMPF0100 NXP

120 NXP Semiconductors

  1. NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP

offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. Table 139. Bill of materials -40 °C to 85 °C applications (continued) (85)

°C to 105 °C applications. Components are provided with an example part number; equivalent components may be used. Table 140. Bill of materials -40 °C to 105 °C applications (86)

122 NXP Semiconductors

1.0 A 1 DIODE SCH PWR RECT 1A 20V SMT MBR120LSFT3G ON Semiconductor Schottky diode

  1. NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP

offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. Table 140. Bill of materials -40 °C to 105 °C applications (continued) (86)

7.2 PF0100 layout guidelines

7.2.1 General board recommendations

  1. It is recommended to use an eight layer board stack-up arranged as follows:
  • High current signal
  • G N D
  • Signal
  • P o w e r
  • P o w e r
  • Signal
  • G N D
  • High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTIN G (high current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.

7.2.2 Component placement

It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output capacitors.

7.2.3 General routing requirements

  1. Some recommended things to keep in mind for manufacturability:
  • Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
  • Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
  • Minimum allowed spacing between line and hole pad is 3.5 mils
  • Minimum allowed spacing between line and line is 3.0 mils 2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be also shielded. 3. Shield feedback traces of the regulators and keep them as s hort as possible (trace them on the bottom so the ground and power planes shield these traces). 4. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node (i.e. SW1ALX, SW1BLX, SW1CLX, SW2LX, SW3ALX, SW3BLX, SW4LX, and SWBSTLX). 5. Make sure all components related to a specific block are referenced to the corresponding ground.

7.2.4 Parallel routing requirements

  1. I 2C signal routing
  • CLK is the fastest signal of the syst em, so it must be given special care.
  • To avoid contamination of these delicate si gnals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.

124 NXP Semiconductors

Figure 36. Recommended shielding for critical signals

  • These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
  • Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

7.2.5 Switching regulator layout recommendations

  1. Per design, the switching regulators in PF0100 are designed to operate with only one input bulk capacitor. However, it is

should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.

  1. Make high-current ripple traces low- inductance (short, high W/L ratio).
  2. Make high-current traces wide or copper islands.
  3. Make high-current traces symetrica l for dual–phase regulators (SW1, SW3).

Figure 37. Generic buck regulator architecture

Figure 38. Layout example for buck regulators

7.3 Thermal information

7.3.1 Rating data

The thermal rating data of the packages has been simulated with the results listed in Table 6. test boards. It is anticipated the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.

7.3.2 Estimation of junction temperature

The junction to ambient thermal resistance is an industry standard value providing a quick and easy estimation of thermal performance. somewhat degraded in case of significant power dissipated by other components placed close to the device. When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See 6 Functional block requirements and behaviors, page 18 for more details on thermal management.

126 NXP Semiconductors

8 Packaging

8.1 Packaging dimensions

characteristics for each package. Table 141. Package drawing information

128 NXP Semiconductors

130 NXP Semiconductors

132 NXP Semiconductors

134 NXP Semiconductors

9 Reference section

9.1 Reference documents

Table 142. PF0100 reference documents

REVISION HISTORY

Revision Date Description of changes 1 7/2011 • Preliminary specif ication release 2 8/2012 • NPI phase: prototype major updates throughout cycle 3 10/2012 • Initial production release 4 5/2013 • Table 4. Added recommended pin connection when regulators are unused

  • Update Table 9. Current Consumption summary
  • Table 10. Removed VREFDDR_VOLT row
  • Removed automatic fuse programming feature
  • Updated Max frequency specification for the 16 MHz clock to 17.2 MHz
  • Table 17. Added specification for derived 2.0 Mhz clock
  • Added Clock adjustment
  • Table 22. Updated VREFDDR minimum Current limit specification
  • Updated Block diagram for all Switching Regulators
  • Updated current limit and overcurrent pr otection minimum specification on LDOS
  • Table 111. Update VTH0 and VTL0 specification on VSNVS
  • Updated Table 137, Address FF
  • Updated Table 138, address D8 and D9
  • Update Figure 35. Typical application diagram
  • Removed Part Identification section 5 7/2013 • Added part numbers to the ordering information for the MMPF0100A
  • Added corrections and notes to the document to accomodate the new part numbers, where identified by MMPF0100A
  • VIN threshold (coin cell powered to VIN powered) Max. changed to 3.1 6 8/2013 • Removed LICELL connection to VIN on PF0100A
  • Removed 4.7 μF LICELL bypass capacitor as coin cell replacement 7 12/2013 • Updated typical and max Off Current
  • Add bypass capacitor in VDDIO
  • Added industrial part numbers PMPF0100xxANES
  • Added parts F3 and F4
  • Added Table 3, Ambient temperature range and updated specification headers accordingly.
  • Increased max standby and sleep cu rrents on Extended Industrial parts.
  • Update output accuracy on SW1A/B , SW1C, SW2, SW3A/B and SW4.
  • Corrected the default value on DEVICEID register, bit4 (unused) from 0 to 1.
  • Corrected default register values on Table 118.
  • Added VDDIO capacitor to Miscellaneous in the BOM 8 4/2014 • Corrected VDDOTP maximum rating
  • Corrected SWBSTFB maximum rating
  • Corrected inductor Isat for SW1ABC single phase mode from 4.5 A to 6.0 A
  • Added note to clarify SWBST default operation in Auto mode
  • Corrected default value of bits in SILICONREVID register in Table 136
  • Changed VSNVS current limit for PF0100A
  • Noted that voltage settings 0.6V and below are not supported
  • VSNVS Turn On Delay (td1) spec corrected from 15 ms to 5.0 ms
  • Updated per GPCN 16298 6/2014 • Corrected GPCN number in the revi sion history table (16220 changed to 16298) 9 7/2014 • Updated VTL1, VTH1, and VSNVSCROSS threshold specifications
  • Added F6 part
  • Changes documented in GPCN 16369 10 7/2015 • Added new part numbers MMPF0100F9ANES and MMPF0100FAANES to Table 1
  • Updated Table 10 11 8/2015 • Removed MMPF0100F3EP and MMPF0100F4 EP from Orderable Parts table

136 NXP Semiconductors

  • Updated Table 53
  • Updated Table 62
  • Updated Table 77
  • Updated Table 86
  • Fixed typo in Table 138
  • Updated Table 139
  • Added Table 140
  • Corrected the default regist er value for SW1ABMODE in Table 46
  • Corrected the default register value for SW1CMODE in Table 51
  • Corrected the default regist er value for SW2MODE in Table 60
  • Corrected the default register value for SW3AMODE in Table 70
  • Corrected the default register value for SW3BMODE in Table 75
  • Corrected the default regist er value for SW4MODE in Table 84
  • Updated Figure 35 13 12/2015
  • Removed MMPF0100NPEP, MMPF0100F0EP, MMPF0100F1EP, and MMPF0100F2EP from Orderable Part Variations. No longer manufactured.
  • Updated Table 10
  • Reformatted to newer template form and style 14 3/2016 • Updated SW2 current capability from 2000 mA to 2500 mA for F9/FA versions 15 5/2016 • Changed Table 10 row - Default I2C Address from 0x80 to 0x08 for F9 and FA 16 9/2016
  • Added NP version to OTP's with SW2 current capability of 2500 mA
  • Added MMPF0100FBANES part number to Table 1
  • Added FB OTP option to Table 10 17 1/2017 • Added MMPF0100FCAEP, MMPF0100FDAEP, and MMPF0100FCANES part numbers to Table 1
  • Added OTP configurations for FC and FD to Table 10 18 7/2019 • Updated 98ASA00405D drawing as per PCN 201906034F01
  • Changed document status from Advance Information to Technical Data 19 4/2022 • Added 98ASA00405D optional bottom view page for E-type package as per CIN 202204010I 20 5/2022 • Table 139: replaced Freescale by NXP
  • Table 140: replaced Freescale by NXP Revision Date Description of changes

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or sp ecifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo, and SMARTMOS, are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © NXP B.V. 2022. Document Number: MMPF0100 Rev. 20