MMPF0100F8AZES

MMPF0100Z NXP | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 128

Technical content

• This document contains certain information on a new product.

Specifications and information herein are subject to change without notice. designs, and pre-programmed versions of the device.

• Four to six buck converters, depending on configuration
• Single/dual phase/ parallel options
• DDR termination tracking mode option
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (one time programmable) memory for device configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event detection
• I 2C control
• Individually programmable on, off, and standby modes

Figure 1. Simplified application diagram

• G P S
• Auto infotainment
• Heads up display (HUD)
• Rear displays
• Digital instrument ation cluster (DIC) Automotive ES SUFFIX (WF-TYPE) 98ASA00589D

56 QFN 8X8

2 NXP Semiconductors

4 NXP Semiconductors

1 Orderable parts

the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 9.

1.1 PF0100Z version differences

and should be referred to when migrating from the PF0100Z to the PF0100AZ. Table 1. Orderable part variations

56 QFN ES, 8x8 mm

1. For tape and reel add an R2 suffix to the part number.
2. These reference designs use the default st artup configuration (VDDOTP = VCOREDIG), which is available on any OTP programmed part.
3. SW2 can support an output current rating of 2. 5 A in NP, F9 and FA versions when SW2ILIM=0

Table 2. Differences between PF0100Z and PF0100AZ has to be 1 for fuses to be loaded during startup. FUSE_PORx bits during OTP programming. FUSE_POR3 bits during OTP programming.

2 Internal block diagram

Figure 2. Simplified internal block diagram

6 NXP Semiconductors

3 Pin connections

3.1 Pinout diagram

Figure 3. Pinout diagram

3.2 Pin definitions

Table 3. PF0100Z pin definitions Analog Reserved pin. Connect to GND in application. high current path and terminate at the output capacitance. and a 0.1 μF decoupling capacitor as close to the pin as possible. and a 0.1 μF decoupling capacitor as close to the pin as possible. and a 0.1 μF decoupling capacitor as close to the pin as possible. high current path and terminate at the output capacitance. GNDREF through a board ground plane. GNDREF, via board ground plane. 16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor. 18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor. current path and terminate at the output capacitance. a 0.1 μF decoupling capacitor as close to the pin as possible. current path and terminate at the output capacitance. 26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor.

8 NXP Semiconductors

as close to the pin as possible. high current path and terminate at the output capacitance. and a 0.1 μF decoupling capacitor as close to the pin as possible. and a 0.1 μF decoupling capacitor as close to the pin as possible. high current path and terminate at the output capacitance. 39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor. load. Keep this trace away from other noisy traces and planes. and a 0.1 μF decoupling capacitor as close to the pin as possible.

47 VDDOTP I 10 V (4) Digital &

48 GNDREF GND - GND Ground reference for the main band gap regulator.

1. 10 V Maximum voltage rating during OTP fuse progra mming. 7.5 V Maximum DC voltage rated otherwise.
2. Unused switching regulators should be connected as follows: Pins SWxLX and SWxFB should be unconnected and pin SWxIN should be

connected to VIN with a 0.1 μF bypass capacitor. Table 3. PF0100Z pin definitions (continued)

4 General product characteristics

4.1 Absolute maximum ratings

Table 4. Absolute maximum ratings to the device. The detailed maximum voltage rating per pin can be found in the pin list section.

1. ESD testing is performed in accor dance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),

10 NXP Semiconductors

4.2 Thermal characteristics

4.2.1 Power dissipation

this protection is not tripped under normal conditions. Table 5. Thermal ratings

1. Do not operate beyond 125 °C for extended periods of time . Operation above 150 °C may cause permanent damage to the IC. See Table 6 for

thermal protection features.

1. Pin soldering temperature limit is for 10 seconds maximum du ration. Not designed for immersion soldering. Exceeding these limits may cause a

malfunction or permanent damage to the device.

1. NXP’s package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and

parts, and review parametrics.

1. Junction temperature is a function of die size, on-chip powe r dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

1. The Board uses the JEDEC specifications for th ermal testing (and simulation) JESD51-7 and JESD51-5.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit boar d per JEDEC JESD51-8. Board temperature is measured on the top surface of the
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
5. Thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature per JEDEC JESD51-
6. When the Greek letter (Ψ) is not available, the thermal characterization parameter is written as Psi-JT.

4.3 Electrical characteristics

4.3.1 General Specifications

Table 6. Thermal protection thresholds Table 7. General PMIC Static Characteristics values and full load current range, unless otherwise noted.

12 NXP Semiconductors

4.3.2 Current consumption

follows for standard use cases. Table 8. Current consumption summary VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.

Figure 4. Current overtemperature waveforms

1. Refer to Figure 4 for coin cell mode characteristics over temperature.
2. When V IN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
3. For PFM operation, headroom should be 300 mV or greater.
4. Additional current may be drawn in the coin cell mode when R ESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.

RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail that is off in the coin cell mode. Table 8. Current consumption summary (continued) VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.

14 NXP Semiconductors

5 General description

The PF0100Z is the power management integrat ed circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of applicatio n processors.

5.1 Features

This section summarizes the PF0100Z features.

• Input voltage range to PMIC: 2.8 V - 4.5 V
• Buck regulators
• Four to six channel configurable
• SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V
• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V
• SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V
• S W 3 A , 1 . 2 5 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V
• S W 4 , 1 . 0 A; 0.4 V to 3.3 V
• SW4, VTT mode provide DDR termination at 50% of SW3A
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable soft start
• Programmable PWM switching frequency
• Programmable OCP with fault interrupt
• Boost regulator
• SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support
• Modes: PFM and Auto
• OCP fault interrupt
• L D O s
• Six user programable LDO
• VGEN1, 0.80 V to 1.55 V, 100 mA
• VGEN2, 0.80 V to 1.55 V, 250 mA
• VGEN3, 1.8 V to 3.3 V, 100 mA
• VGEN4, 1.8 V to 3.3 V, 350 mA
• VGEN5, 1.8 V to 3.3 V, 100 mA
• VGEN6, 1.8 V to 3.3 V, 200 mA
• Soft start
• LDO/switch supply
• DDR memory reference voltage
• V R E F D D R , 0 . 6 V to 0.9 V, 10 mA
• 1 6 MHz internal master clock
• OTP (one time programmable) me mory for device configuration
• User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
• I 2C interface
• User programmable standby, sleep, and off modes Notes 22. SW2 capable of 2.5 A in NP/F9/FA versions

5.2 Functional block diagram

Figure 5. Functional block diagram

5.3 Functional description

5.3.1 Power generation

switch/LDO combination, and a DDR voltage reference to supply voltages for the application processor and peripheral devices. the processor cores and/or other circuitry. powered from VIN, or from a coin cell.

5.3.2 Control logic

configuring the “try before buy” feature to test different power up sequences before choosing the final OTP configuration.

16 NXP Semiconductors

5.3.2.1 Interface signals

5.3.2.1.1 PWRON

5.3.2.1.2 STANDBY

VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode.

5.3.2.1.3 RESETBMCU

to bring the processor out of reset, or as an indicator all supplies have been enabled; it is only asserted for a turn-off event. Table 136. Extended page 1, page 106 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses.

5.3.2.1.4 SDWNB

cycle before powering down and then de-asserted in the OFF state.

5.3.2.1.5 INTB

after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.

6 Functional block requirements and behaviors

6.1 Start-up

OTP configuration is enabled by connecting VDDOTP to GND. the I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration.

6.1.1 Device start-up configuration

Table 9. Start-up configuration

18 NXP Semiconductors

Table 9. Start-up configuration (continued)

Figure 6. Default start-up sequence Table 10. Default start-up sequence timing *VSNVS starts from 1.0 V if LICELL is valid before VIN.

20 NXP Semiconductors

6.1.2 One time programmability (OTP)

algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. The following parameters which can be configured by OTP are listed.

• General: I 2C slave address, PWRON pin configuration, start-up sequence and timing
• Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching frequency, and soft start ramp rate
• Boost regulator and LDOs: Output voltage NOTE: When prototyping or programming fuses, the user must ensure register settings ar e consistent with the hardware configuration. This is most important for the buck regul ators, where the quantity, size, and value of the inductors depend on the configuratio n (single/ dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it is gated by the buck regulator in the start-up sequence.

6.1.2.1 Start-up sequence and timing

Table 11. The delay between each position is equal; howe ver, four delay options are available. See Table 12. The start-up sequence terminates at the last programmed regulator.

1. Assumes LICELL voltage is valid before V IN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may extend to a
2. Depends on the external signal driving PWRON.
3. Rise time is a function of slew rate of regulators and nominal voltage selected.

Table 11. Start-up sequence

00000 Off

00001 SEQ_CLK_SPEED[1:0] * 1

00010 SEQ_CLK_SPEED[1:0] * 2

11111 SEQ_CLK_SPEED[1:0] * 31

Table 10. Default start-up sequence timing (continued)

6.1.2.2 PWRON pin configuration

The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input (PWRON_CFG = 1). greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.

6.1.2.3 I 2C address configuration

The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I 2C address to avoid bus conflicts. (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 14.

6.1.2.4 Soft start ramp rate

Table 12. Start-up Sequence Clock Speed Table 13. PWRON configuration

0 PWRON pin HIGH = ON

1 PWRON pin pulled LOW momentarily = ON

Table 14. I2C address configuration

22 NXP Semiconductors

6.1.3 OTP prototyping

are referred to as the TBBOTP registers. The portion of the register map concerning OTP is shown in Table 136 and Table 137. registers depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR bits. Refer to Table 15.

• If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 1, the values are loaded from the fuses. In the MMPF0100Z, FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR must be 1 for fuses to be loaded. This is achieved by setting any one or all of the FUSE_PORx bits. The XOR function is removed in the MMPF0100AZ. It is required to set all of the FUSE_PORx bits to be able to load the fuses.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 0, the TBBOTP registers remain initialized at zero. The initial value of TBB_POR is a lways “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP registers maintained and not loaded from a different source. The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 V to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. To power on with t he contents of the TBBOTP registers, the following c onditions must exist; VIN is valid, VDDOTP = 0 .0 V, TBB_POR = 1, and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping.

6.1.4 Reading OTP fuses

powers on with the configuration programmed in the fuses. For more details on reading the OTP fuses, see application note AN4536.

6.1.5 Programming OTP fuses

PF0100AZ offers ECC, the control registers for which functions are located in Table 137. Extended page 2, page 110 of the register map. Table 15. Source of start-up sequence

• VIN < UVDET
• All regulators are in sleep mode
• All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
• PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the on mode, the debounce times in Table 26 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.

6.2.1 Clock adjustment

NXP representative for detailed information on this feature.

6.3 Bias and references block description

6.3.1 Internal core voltage references

valid supply and/or valid coin cell. Table 17 shows the main characteristics of the core circuitry. Table 16. 16 MHz clock specifications component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

1. The 2.0 MHz clock is derived from the 16 MHz clock.

Table 17. Core voltages electrical specifications(29) component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

24 NXP Semiconductors

6.3.1.1 External components

6.3.2 VREFDDR voltage reference

voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider uses a voltage follower to drive the load. Figure 7. VREFDDR block diagram

6.3.2.1 VREFDDR control register

The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 19. Table 18. External components for core voltages Table 17. Core voltages electrical specifications(29) (continued) component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.

6.3.2.1.1 External components

6.3.2.1.2 VREFDDR specifications

Table 19. Register VREFDDCRTL - ADDR 0x6A Table 20. VREFDDR external components (30)

1. Use X5R or X7R capacitors.
2. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output.

Table 21. VREFDDR electrical characteristics 25 °C, unless otherwise noted.

26 NXP Semiconductors

1. When VREFDDR is off there is a quiescent current of 1.5 μA typical.

Table 21. VREFDDR electrical characteristics (continued) 25 °C, unless otherwise noted.

6.4 Power generation

6.4.1 Modes of operation

diagram of the PF0100Z, along with the conditions to enter and exit from each state. Figure 8. State diagram coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and on states.

6.4.1.1 On mode

The PF0100Z enters the on mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.

6.4.1.2 Off mode

asserted, low, in this mode.

28 NXP Semiconductors

6.4.1.3 Standby mode

• Depending on STANDBY pin configuration, stan dby is entered when the STANDBY pin is asserted. This is typically used for low- power mode of operation.
• When STANDBY is de-asserted, standby mode is exited. A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators, or disabling some regulators. The configuration of the regulators in standby is pre-programmed through the I2C interface. Note that the STANDBY pin is programmable for active high or active low polarity, and decoding of a Standby event takes into ac count the programmed input polarity, as shown in Table 22. When the PF0100Z is powered up first, regulator settings for the standby mode are mirrored from the regulator settings for t he on mode. To change the STANDBY pin polarity to active low, set the STANDBYINV bit via software first, and then change the regulator settings for standby mode as required. For simplicity, STANDBY is generally referred to as active high throughout this document. Since STANDBY pin activity is driven asynchronously to the system , a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and peripherals some time after a standby instruction was receiv ed to terminate processes to facilitate seamless entering into standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 23, STBYDLY delays the standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the standby event.

6.4.1.4 Sleep mode

• Depending on the PWRON pin configuration, sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
• To exit sleep mode, assert the PWRON pin. In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/ B, and SW4. The activated regulators maintain settings for this mode and voltage until the next turn-on event. Table 24 shows the control bits in sleep mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event.

Table 22. Standby pin and polarity control

1. STANDBY = 0: System is not in standby, STANDBY = 1: System is in standby
2. The state of the STANDBY pin only has influence in on mode.
3. Bit 6 in power control register (ADDR - 0x1B)Table 23. STANDBY delay - initiated response

00 No delay

01 One 32 k period (default)

10 Two 32 k periods

11 Three 32 k periods

1. Bits [5:4] in Power Control Register (ADDR - 0x1B)

6.4.1.5 Coin cell mode

state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. system is re-initialized with all I2C bits including those reset on COINPORB, which are restored to their default states.

6.4.2 State machine flow summary

Table 25 provides a summary matrix of the PF0100Z flow diagram to show the conditions needed to transition from one state to another. Table 24. Regulator mode control

1. For sleep mode, an activated switching regulator, should use the off mode

SWxOFF[6:0] for SW2, SW3A/B, and SW4. Table 25. State machine flow summary

30 NXP Semiconductors

6.4.2.1 Turn on events

From off and sleep modes, the PMIC is powered on by a turn-on event. The type of turn-on event depends on the configuration of PWRON. PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1.

• If PWRON_CFG = 0, the PWRON signal is high and V IN > UVDET, the PMIC turns on; the interrupt and sense bits, PWRONI and PWRONS respectively, are set.
• If PWRON_CFG = 1, V IN > UVDET and PWRON transitions from high to low, the PMIC turns on; the interrupt and sense bits, PWRONI and PWRONS respectively, are set. The sense bit shows the real time status of the PWRON pin. In this configuration, the PWRON in put can be a mechanical switch debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a ve ry short (unintentional) key press. The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in Table 26. The interrupt is cleared by software, or when cycling through the off mode.

6.4.2.2 Turn off events

6.4.2.2.1 PWRON pin

1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.

Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

6.4.2.2.2 Thermal protection

6.4.2.2.3 Undervoltage detection

When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin cell mode. Table 26. PWRON hardware debounce bit settings

1. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.

6.4.3 Power tree

by any rail supplying voltage to DDR memories; the typical applicat ion recommends the use of SW3 as the input supply for VREFDD R. voltage and current requirements, therefore a proper input voltage should be selected for the regulators. Table 27. Power tree summary

1. Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up to 2500 mA.
2. SW2 capable of 2500 mA in NP/F9/FA versions

Table 28. UVDET threshold

32 NXP Semiconductors

Figure 9. PF0100Z typical power map

6.4.4 Buck regulators

Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.

6.4.4.1 Current limit

condition persists for more than 8.0 ms, a fault interrupt is generated.

6.4.4.2 General control

variation. Available switching modes for buck regulators are presented in Table 29. summarizes the buck regulator programmability for normal and standby modes. regulator, the output voltage options are the same for normal and standby modes. Table 29. Switching mode description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is always in PFM mode, wh ich is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS In this mode, the regulator move s automatically between pulse skipping mode and PWM mode depending on load conditions. Table 30. Regulator mode control

0000 Off Off

0001 PWM Off

0010 Reserved Reserved

0011 PFM Off

0100 APS Off

0101 PWM PWM

0110 PWM APS

0111 Reserved Reserved

1000 APS APS

1001 Reserved Reserved

1010 Reserved Reserved

1011 Reserved Reserved

1100 APS PFM

1101 PWM PFM

1110 Reserved Reserved

1111 Reserved Reserved

34 NXP Semiconductors

programmed in its voltage register. regulator returns to its default ON state output voltage and switch mode settings. programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.

6.4.4.2.1 Dynamic voltage scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.

1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4.

A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 33 and Table 34.

1. Standby mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state

SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.

1. Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state

SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively. Table 31, Table 32, Table 33, and Table 34 summarize the set point control and DVS time stepping applied to all regulators. Table 31. DVS control logic for SW1A/B/C

0 SW1x[5:0]

1 SW1xSTBY[5:0]

Table 32. DVS control logic for SW2, SW3A/B, and SW4

0 SWx[6:0]

1 SWxSTBY[6:0]

Table 33. DVS speed selection for SW1A/B/C

PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. DVS period the overcurrent condition on the regulator should be masked. Figure 10. Voltage stepping with DVS

6.4.4.2.2 Regulator phase clock

4.0 MHz, 180 ° are the same in terms of phasing. Table 36 shows the optimum phasing when using more than one switching frequency. Table 34. DVS Speed Selection for SW2, SW3A/B, and SW4 Table 35. Regulator phase clock selection

36 NXP Semiconductors

6.4.4.2.3 Programmable maximum current

power stages that are enabled. Table 36. Optimum phasing

1.0 MHz

2.0 MHz

4.0 MHz

Table 37. Regulator frequency configuration

11 Reserved

Table 38. Programmable current configuration

6.4.4.3 SW1A/B/C

• SW1A/B/C single phase with one inductor
• SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor
• SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Table 136. Extended page 1, page 106, as shown in Table 39.

6.4.4.3.1 SW1A/B/C single phase

respectively. Figure 11 shows the connection for SW1A/B/C in single phase mode. be used. The SW1FB pin should be left floating in this configuration. Table 39. SW1 configuration

00 A/B/C single phase

01 A/B single phase

10 A/B dual phase

Table 38. Programmable current configuration (continued)

38 NXP Semiconductors

Figure 11. SW1A/B/C single phase block diagram

6.4.4.3.2 SW1A/B single phase - SW1C independent mode

physical connection for SW1A/B in single phase and SW1C as an independent output.

Figure 12. SW1A/B single phase, SW1C independent mode block diagram SW1CLX node operates independently, using the configuration in the SW1CCONF register.

6.4.4.3.3 SW1A/B dual phase - SW1C independent mode

output using its own inductor and configurati on parameters. This mode provides a sma ller output voltage ripple on the SW1A/B ou tput. connection for SW1A/B in dual phase and SW1C as an independent output.

40 NXP Semiconductors

Figure 13. SW1A/B dual phase, SW1C independent mode block diagram

6.4.4.3.4 SW1A/B/C setup and control registers

respectively. Table 40 shows the output voltage coding for SW1A/B or SW1C. Note: Voltage set points of 0.6 V and below are not supported. provided in Table 42 through Table 51. Table 40. SW1A/B/C output voltage configuration

42 NXP Semiconductors

Table 41. SW1A/B/C register summary Table 42. Register SW1ABVOLT - ADDR 0x20 Table 43. Register SW1ABSTBY - ADDR 0x21 Table 44. Register SW1ABOFF - ADDR 0x22 Table 45. Register SW1ABMODE - ADDR 0x23 SW1ABMODE 3:0 R/W 0x80 Sets the SW1AB switching operation mode. See Table 30 for all possible configurations.

Table 46. Register SW1ABCONF - ADDR 0x24 SW1ABFREQ 3:2 R/W 0x00 SW1A/B switching frequency selector. SW1ABPHASE 5:4 R/W 0x00 SW1A/B phase clock selection. SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection. Table 47. Register SW1CVOLT - ADDR 0x2E Table 48. Register SW1CSTBY - ADDR 0x2F Table 49. Register SW1COFF - ADDR 0x30 Table 50. Register SW1CMODE - ADDR 0x31 SW1CMODE 3:0 R/W 0x80 Sets the SW1C switching operation mode. See Table 29 for all possible configurations.

44 NXP Semiconductors

6.4.4.3.5 SW1A/B/C external components

Table 51. Register SW1CCONF - ADDR 0x32 SW1CFREQ 3:2 R/W 0x00 SW1C switching frequency selector. SW1CPHASE 5:4 R/W 0x00 SW1C phase clock selection. SW1CDVSSPEED 7:6 R/W 0x00 SW1C DVS speed selection. Table 52. SW1A/B/C external component recommendations

1. Use X5R or X7R capacitors.

6.4.4.3.6 SW1A/B/C specifications

Table 53. SW1A/B/C electrical characteristics

• PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1ABC < 4.5 A 0.625 V ≤ VSW1ABC ≤ 1.450 V 1.475 V ≤ VSW1ABC ≤ 1.875 V
• PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1ABC < 150 mA 0.625 V < VSW1ABC < 0.675 V 0.7 V < VSW1ABC < 0.85 V 0.875 V < VSW1ABC < 1.875 V -25 -3.0% -65 -45 -3.0% 3.0% 3.0% mV I SW1ABC Rated output load current, 2.8 V < VIN < 4.5 V, 0.625 V < VSW1ABC < 1.875 V – – 4500 mA ISW1ABCLIM Current limiter peak current detection
• Current through inductor SW1ABILIM = 0 SW1ABILIM = 1 7.1 5.3 10.5 7.9 13.7 10.3 A VSW1ABCOSH Start-up overshoot ISW1ABC = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V –– 6 6 m V tONSW1ABC Turn-on time Enable to 90% of end value ISW1x = 0 mA DVS clk = 25 mV/4.0 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V – – 500 µs fSW1ABC Switching frequency SW1xFREQ[1:0] = 00 SW1xFREQ[1:0] = 01 SW1xFREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW1ABC Efficiency
• V IN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 850 mA APS, PWM, 1.2 V, 1275 mA APS, PWM, 1.2 V, 2125 mA APS, PWM, 1.2 V, 4500 mA ΔV SW1ABC Output ripple – 10 – mV VSW1ABCLIR Line regulation (APS, PWM) – – 20 mV VSW1ABCLOR DC load regulation (APS, PWM) – – 20 mV VSW1ABCLOTR Transient load regulation
• Transient load = 0 A to 2.25 A, di/dt = 100 mA/ μs Overshoot Undershoot mV

46 NXP Semiconductors

• PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 2.5 A 0.625 V ≤ VSW1AB ≤ 1.450 V 1.475 V ≤ VSW1AB ≤ 1.875 V
• PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 150 mA 0.625 V < VSW1AB < 0.675 V 0.7 V < VSW1AB < 0.85 V 0.875 V < VSW1AB < 1.875 V -25 -3.0% -65 -45 -3.0% 3.0% -65 -45 3.0% mV I SW1AB Rated output load current, 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V – – 2500 mA (43) ISW1ABLIM Current limiter peak current detection
• SW1A/B single phase (current through inductor) SW1ABILIM = 0 SW1ABILIM = 1
• SW1A/B dual phase (current through inductor per phase) SW1ABILIM = 0 SW1ABILIM = 1 4.5 3.3 2.2 1.6 6.5 4.9 3.2 2.4 8.5 6.4 4.3 3.2 A (43) VSW1ABOSH Start-up overshoot ISW1AB = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V –– 6 6 m V tONSW1AB Turn-on time Enable to 90% of end value ISW1AB = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V – – 500 µs fSW1AB Switching frequency SW1ABFREQ[1:0] = 00 SW1ABFREQ[1:0] = 01 SW1ABFREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW1AB Efficiency (single phase)
• V IN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 500 mA APS, PWM, 1.2 V, 750 mA APS, PWM, 1.2 V, 1250 mA APS, PWM, 1.2 V, 2500 mA ΔV SW1AB O u t p u t r i p p l e –1 0– m V VSW1ABLIR Line regulation (APS, PWM) – – 20 mV

Table 53. SW1A/B/C electrical characteristics (continued)

• Transient load = 0 A to 1.25 A, di/dt = 100 mA/ μs Overshoot Undershoot mV ISW1ABQ Quiescent current PFM mode APS mode 235 µA RONSW1AP SW1A P-MOSFET RDS(on) VINSW1A = 3.3 V – 215 245 m Ω RONSW1AN SW1A N-MOSFET RDS(on) VINSW1A = 3.3 V – 258 326 m Ω ISW1APQ SW1A P-MOSFET leakage current VINSW1A = 4.5 V –– 7 . 5 µ A ISW1ANQ SW1A N-MOSFET leakage current VINSW1A = 4.5 V –– 2 . 5 µ A RONSW1BP SW1B P-MOSFET RDS(on) VINSW1B = 3.3 V – 215 245 m Ω RONSW1BN SW1B N-MOSFET RDS(on) VINSW1B = 3.3 V – 258 326 m Ω ISW1BPQ SW1B P-MOSFET leakage current VINSW1B = 4.5 V –– 7 . 5 µ A ISW1BNQ SW1B N-MOSFET leakage current VINSW1B = 4.5 V –– 2 . 5 µ A RSW1ABDIS Discharge Resistance – 600 – W SW1C (independent) VINSW1C Operating input voltage 2.8 – 4.5 V VSW1C Nominal output voltage – Table 40 –V VSW1CACC Output voltage accuracy
• PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1C < 2.0 A 0.625 V ≤ VSW1C ≤ 1.450 V 1.475 V ≤ VSW1C ≤ 1.875 V
• PFM, steady state 2.8 V < V IN < 4.5 V, 0 < ISW1C < 50 mA 0.625 V < VSW1C < 0.675 V 0.7 V < VSW1C < 0.85 V 0.875 V < VSW1C < 1.875 V -25 -3.0% -65 -45 -3.0% 3.0% 3.0% mV I SW1C Rated output load current 2.8 V < VIN < 4.5 V, 0.625 V < VSW1C < 1.875 V – – 2000 mA ISW1CLIM Current limiter peak current detection
• Current through inductor SW1CILIM = 0 SW1CILIM = 1 2.6(42) 1.95 4.0 3.0 5.2 3.9 A

48 NXP Semiconductors

• V IN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 400 mA APS, PWM, 1.2 V, 600 mA APS, PWM, 1.2 V, 1000 mA APS, PWM, 1.2 V, 2000 mA ΔV SW1C O u t p u t r i p p l e –1 0– m V VSW1CLIR Line regulation (APS, PWM) – – 20 mV VSW1CLOR DC load regulation (APS, PWM) – – 20 mV VSW1CLOTR Transient load regulation
• Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ μs Overshoot Undershoot mV I SW1CQ Quiescent current PFM mode APS mode 145 µA RONSW1CP SW1C P-MOSFET RDS(on) at VINSW1C = 3.3 V – 184 206 m Ω RONSW1CN SW1C N-MOSFET RDS(on) at VINSW1C = 3.3 V – 211 260 m Ω ISW1CPQ SW1C P-MOSFET leakage current VINSW1C = 4.5 V – – 10.5 µA ISW1CNQ SW1C N-MOSFET leakage current VINSW1C = 4.5 V –– 3 . 5 µ A RSW1CDIS Discharge resistance – 600 – W Notes 42. Supports the Coremark and 3D MM benchmark maximum current value of 2500 mA of the VDD_SOC_IN domain in the i.MX 6Dual/Quad processors. 43. Current rating of SW1AB supports the power viru s mode of operation of the i.MX 6X processor.

Figure 14. SW1AB and SW1C efficiency waveforms

50 NXP Semiconductors

6.4.4.4 SW2

options for the SWxMODE[3:0] bits. Figure 15 shows the block diagram and the external component connections for SW2 regulator. Figure 15. SW2 block diagram

6.4.4.4.1 SW2 setup and control registers

set to “0”, the output is limited to the lower output voltages from 0.400 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. increments, as determined by bits SW2[5:0]. and the lower range be used for voltages from 0.400 V to 1.975 V. and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] is copi ed into bits SW2STBY[6], and SW2OFF[6] bits . Note: Voltage set points of 0.6 V and below are not supported. Table 54. SW2 output voltage configuration

Table 54. SW2 output voltage configuration (continued)

52 NXP Semiconductors

1. For voltages less than 2.0 V, only use set points 0 to 63.

Table 55. SW2 register summary Table 56. Register SW2VOLT - ADDR 0x35 mode. See Table 54 for all possible configurations. for all possible configurations. Table 57. Register SW2STBY - ADDR 0x36 SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during standby mode. See Table 54 for all possible configurations. for all possible configurations.

6.4.4.4.2 SW2 external components

Table 58. Register SW2OFF - ADDR 0x37 Table 54 for all possible configurations. for all possible configurations. Table 59. Register SW2MODE - ADDR 0x38 SW2MODE 3:0 R/W 0x80 Sets the SW2 switching operation mode. See Table 29 for all possible configurations. Table 60. Register SW2CONF - ADDR 0x39 SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. SW2PHASE 5:4 R/W 0x00 SW2 phase clock selection. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection.

1. SW2ILIM = 0 must be used in NP/F9/FA vers ions if 2.5 A output load current is desired

Table 61. SW2 external component recommendations

1. Use X5R or X7R capacitors.

54 NXP Semiconductors

6.4.4.4.3 SW2 specifications

Table 62. SW2 electrical characteristics

• PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW2 < 2.0 A 0.625 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V
• PFM, 2.8 V < V IN < 4.5 V, 0 < ISW2 ≤ 50 mA 0.625 V < VSW2 < 0.675 V 0.7 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV I SW2 Rated output load current
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V
• 2.8 V < VIN < 4.5 V, 1.2 V < VSW2 < 3.3 V, SW2LIM = 0 2000 2500 mA (48) (49) ISW2LIM Current limiter peak current detection
• Current through inductor SW2ILIM = 0 SW2ILIM = 1 2.8 2.1 4.0 3.0 5.2 3.9 A VSW2OSH Start-up overshoot ISW2 = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V –– 6 6 m V tONSW2 Turn-on time Enable to 90% of end value ISW2 = 0.0 mA DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V – – 550 µs fSW2 Switching frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW2 Efficiency
• V IN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH PFM, 3.15 V, 1.0 mA PFM, 3.15 V, 50 mA APS, PWM, 3.15 V, 400 mA APS, PWM, 3.15 V, 600 mA APS, PWM, 3.15 V, 1000 mA APS, PWM, 3.15 V, 2000 mA ΔV SW2 O u t p u t r i p p l e –1 0– m V VSW2LIR Line regulation (APS, PWM) – – 20 mV VSW2LOR DC load regulation (APS, PWM) – – 20 mV VSW2LOTR Transient load regulation
• Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ μs Overshoot Undershoot mV

Figure 16. SW2 efficiency waveforms

1. When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V.
2. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:

(VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).

1. Applies to NP/F9/FA versions

Table 62. SW2 electrical characteristics (continued)

56 NXP Semiconductors

6.4.4.5 SW3A/B

Table 30 show the actual configuration options for the SW3xMODE[3:0] bits.

• A single phase
• A dual phase
• Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 63 shows the options for the SW3CFG[1:0] bits.

6.4.4.5.1 SW3A/B single phase

from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. Figure 17. SW3A/B single phase block diagram Table 63. SW3 configuration

00 A/B single phase

11 A/B independent

6.4.4.5.2 SW3A/B dual phase

registers of both regulators, SW3A and SW3B, must be identically set. In this configuration, the regulators switch 180 degrees apart. Figure 18. SW3A/B dual phase block diagram

6.4.4.5.3 SW3A - SW3B independent outputs

58 NXP Semiconductors

Figure 19. SW3A/B independent output block diagram

6.4.4.5.4 SW3A/B setup a nd control registers

with 50 mV increments, as determined by bits SW3x[5:0]. and the lower range be used for voltages from 0.400 V to 1.975 V. Note: Voltage set points of 0.6 V and below are not supported. Table 64. SW3A/B output voltage configuration

Table 64. SW3A/B output voltage configuration (continued)

60 NXP Semiconductors

on Tables 66 through Table 75.

1. For voltages less than 2.0 V, only use set points 0 to 63.

Table 65. SW3AB register summary

Table 66. Register SW3AVOLT - ADDR 0x3C all possible configurations. (independent) or SW3A/B (single/dual phase). for all possible configurations. Table 67. Register SW3ASTBY - ADDR 0x3D Table 68. Register SW3AOFF - ADDR 0x3E on bit SW3A[6] during OTP or TBB configuration. See Table 64 for all possible configurations. Table 69. Register SW3AMODE - ADDR 0x3F dual phase) switching operation mode. See Table 29 for all possible configurations. (single/dual phase) when in sleep mode.

62 NXP Semiconductors

Table 70. Register SW3ACONF - ADDR 0x40 SW3APHASE 5:4 R/W 0x00 SW3A phas e clock selection. See Table 35. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 34. Table 71. Register SW3BVOLT - ADDR 0x43 all possible configurations. Table 72. Register SW3BSTBY - ADDR 0x44 Table 73. Register SW3BOFF - ADDR 0x45

6.4.4.5.5 SW3A/B external components

Table 74. Register SW3BMODE - ADDR 0x46 Table 75. Register SW3BCONF - ADDR 0x47 SW3BPHASE 5:4 R/W 0x00 SW3B phase clock selection. See Table 35. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 34. Table 76. SW3A/B external component requirements

1. Use X5R or X7R capacitors.

64 NXP Semiconductors

6.4.4.5.6 SW3A/B specifications

Table 77. SW3A/B electrical characteristics SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

• PWM, APS 2.8 V < V IN < 4.5 V, 0 < ISW3x < ISW3xMAX 0.625 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V
• PFM , steady state (2.8 V < V IN < 4.5 V, 0 < ISW3x < 50 mA) 0.625 V < VSW3x < 0.675 V 0.7 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV I SW3x Rated output load current
• 2.8 V < V IN < 4.5 V, 0.625 V < VSW3x < 3.3 V PWM, APS mode single/dual phase PWM, APS mode independent (per phase) 2500 1250 mA (53) ISW3xLIM Current limiter peak current detection
• Single phase (current through inductor) SW3xILIM = 0 SW3xILIM = 1
• Independent mode or dual phase (current through inductor per phase) SW3xILIM = 0 SW3xILIM = 1 3.5 2.7 1.8 1.3 5.0 3.8 2.5 1.9 6.5 4.9 3.3 2.5 A V SW3xOSH Start-up overshoot ISW3x = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V –– 6 6 m V tONSW3x Turn-on time Enable to 90% of end value ISW3x = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V – – 500 µs fSW3x Switching frequency SW3xFREQ[1:0] = 00 SW3xFREQ[1:0] = 01 SW3xFREQ[1:0] = 10 1.0 2.0 4.0 MHz η SW3AB Efficiency (single phase)
• f SW3 = 2.0 MHz, LSW3x 1.0 μH PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA ΔV SW3x Output ripple – 10 – mV

• Transient load = 0.0 mA to I SW3x/2, di/dt = 100 mA/μs Overshoot Undershoot mV ISW3xQ Quiescent current PFM mode (single/dual phase) APS mode (single/dual phase) PFM mode (independent mode) APS mode (SW3A independent mode) APS mode (SW3B independent mode) 300 250 150 µA R ONSW3AP SW3A P-MOSFET RDS(on) at VIN = VINSW3A = 3.3 V – 215 245 m Ω RONSW3AN SW3A N-MOSFET RDS(on) at VIN = VINSW3A = 3.3 V – 258 326 m Ω ISW3APQ SW3A P-MOSFET leakage current VIN = VINSW3A = 4.5 V –– 7 . 5 µ A ISW3ANQ SW3A N-MOSFET leakage current VIN = VINSW3A = 4.5 V –– 2 . 5 µ A RONSW3BP SW3B P-MOSFET RDS(on) at VIN = VINSW3B = 3.3 V – 215 245 m Ω RONSW3BN SW3B N-MOSFET RDS(on) at VIN = VINSW3B = 3.3 V – 258 326 m Ω ISW3BPQ SW3B P-MOSFET leakage current VIN = VINSW3B = 4.5 V –– 7 . 5 µ A ISW3BPQ SW3B N-MOSFET leakage current VIN = VINSW3B = 4.5 V –– 2 . 5 µ A RSW3xDIS Discharge resistance – 600 – W Notes 52. When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V. 53. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance).

Table 77. SW3A/B electrical characteristics (continued) SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.

66 NXP Semiconductors

Figure 20. SW3AB single phase efficiency waveforms

6.4.4.6 SW4

PFM, APS, and PWM, described on Table 29 and configured by the SW4MODE[3:0] bits, as shown in Table 30. be configured by use of VTT bit in the OTP_SW4_CONFIG register. Figure 21 shows the block diagram and the external component connections for the SW4 regulator. Figure 21. SW4 block diagram

6.4.4.6.1 SW4 setup and control registers

is programmed during OTP or TBB configuration; setting bit VTT to “1” enables SW4 to operate in VTT mode and “0” in Regulator mode. See 6.1.2 One time programmability (OTP), page 20 for detailed information on OTP configuration. read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP reg isters. to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits.

that that the lower range be used for voltages from 0.400 V to 1.975 V. the output voltage range remains the same on all three operating modes. Table 78 shows the output voltage coding valid for SW4. Note: Voltage set points of 0.6 V and below are not supported, except in VTT mode. Table 78. SW4 output voltage configuration

68 NXP Semiconductors

is provided in Tables 80 to Table 84.

1. For voltages less than 2.0 V, only use set points 0 to 63.

Table 79. SW4 register summary Table 78. SW4 output voltage configuration (continued)

Table 80. Register SW4VOLT - ADDR 0x4A Sets the operating output voltage range for SW4. for all possible configurations. Table 81. Register SW4STBY - ADDR 0x4B Table 82. Register SW4OFF - ADDR 0x4C SW4OFF 5:0 R/W 0x00 Sets the SW4 output voltage during sleep mode. See Table 78 for all possible configurations. Table 83. Register SW4MODE - ADDR 0x4D SW4MODE 3:0 R/W 0x80 Sets the SW4 switching operation mode. See Table 29 for all possible configurations.

70 NXP Semiconductors

6.4.4.6.2 SW4 external components

6.4.4.6.3 SW4 specifications

Table 84. Register SW4CONF - ADDR 0x4E SW4PHASE 5:4 R/W 0x00 SW4 phase clock selection. See Table 35. SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 34. Table 85. SW4 external component requirements

1. Use X5R or X7R capacitors.

Table 86. SW4 electrical characteristics SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.

• PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW4 < 1.0 A 0.625 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V 2.0 V < VSW4 < 3.3 V
• PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW4 < 50 mA 0.625 V < VSW4 < 0.675 V 0.7 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V 2.0 V < VSW4 < 3.3 V
• VTT mode , 2.8 V < V IN < 4.5 V, 0 < ISW4 < 1.0 A -25 -3.0% -6.0% -65 -45 -3.0% -3.0% -40 3.0% 6.0% 3.0% 3.0% mV

• f SW4 = 2.0 MHz, LSW4 = 1.0 μH PFM, 1.8 V, 1.0 mA PFM, 1.8 V, 50 mA APS, PWM 1.8 V, 200 mA APS, PWM 1.8 V, 500 mA APS, PWM 1.8 V, 1000 mA PWM 0.75 V, 200 mA PWM 0.75 V, 500 mA PWM 0.75 V, 1000 mA ΔV SW4 Output ripple – 10 – mV VSW4LIR Line regulation (APS, PWM) – – 20 mV VSW4LOR DC load regulation (APS, PWM) – – 20 mV VSW4LOTR Transient load regulation
• Transient load = 0.0 mA to 500 mA, di/dt = 100 mA/ μs Overshoot Undershoot – 50 mV ISW4Q Quiescent current PFM mode APS mode 145 µA RONSW4P SW4 P-MOSFET RDS(on) at VIN = VINSW4 = 3.3 V – 236 274 m Ω RONSW4N SW4 N-MOSFET RDS(on) at VIN = VINSW4 = 3.3 V – 293 378 m Ω ISW4PQ SW4 P-MOSFET leakage current VIN = VINSW4 = 4.5 V –– 6 . 0 µ A ISW4NQ SW4 N-MOSFET leakage current VIN = VINSW4 = 4.5 V –– 2 . 0 µ A

Table 86. SW4 electrical characteristics (continued) SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.

72 NXP Semiconductors

Figure 22. SW4 efficiency waveforms

6.4.5 Boost regulator

integrated on-chip. Figure 23 shows the block diagram and component connection for the boost regulator.

1. When the output is set to > 2.6 V, the output follows the input down when V IN gets near 2.8 V.
2. The higher output voltages available depend on the voltage dr op in the conduction path as given by the following equation:

(VINSW4 - VSW4) = ISW4* (DCR of Inductor +RONSW4P + PCB trace resistance). SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.

Figure 23. Boost Regulator Architecture

6.4.5.1 SWBST setup and control

if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros. Table 87. Register SWBSTCTL - ADDR 0x66

1. In auto mode, the controller automatically swit ches between PFM and APS modes depending on the load current.

The SWBST regulator starts up by default in the auto mode, if SWBST is part of the startup sequence.

74 NXP Semiconductors

6.4.5.2 SWBST external components

6.4.5.3 SWBST specifications

Table 88. SWBST external component requirements

1. Use X5R or X7R capacitors.

Table 89. SWBST electrical specifications VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.

6.4.6 LDO regulators description

and references block description, page 23 for further information on the internal reference voltages. disabled, the output is discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low. Figure 24. General LDO block diagram Table 89. SWBST electrical specifications (continued) VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.

76 NXP Semiconductors

6.4.6.1 Transient response waveforms

and load response refers to the overshoot, or undershoot only, excluding the DC shift. Figure 25. Transient waveforms

6.4.6.2 Short-circuit protection

in an overload condition regardless of the state of the REGSCPEN bit. See Table 90 for SCP behavior configuration. Table 90. Short-circuit behavior

0 Current limit

1 Shutdown

6.4.6.3 LDO regulator control

according to Table 91 for VGEN1 and VGEN2; and uses the voltage set point on Table 92 for VGEN3 through VGEN6. presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output. Table 91. VGEN1, VGEN2 output voltage configuration Table 92. VGEN3/ 4/ 5/ 6 output voltage configuration

78 NXP Semiconductors

Table 93. LDO control

1. STANDBY refers to a standby event as described earlier.

Table 94. Register VGEN1CTL - ADDR 0x6C VGEN1 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 91 for all possible configurations. Table 95. Register VGEN2CTL - ADDR 0x6D VGEN2 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 91 for all possible configurations.

Table 96. Register VGEN3CTL - ADDR 0x6E VGEN3 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 92 for all possible configurations. Table 97. Register VGEN4CTL - ADDR 0x6F VGEN4 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 92 for all possible configurations. Table 98. Register VGEN5CTL - ADDR 0x70 VGEN5 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 92 for all possible configurations.

80 NXP Semiconductors

6.4.6.4 External components

Table 100 lists the typical component values for the general purpose LDO regulators.

6.4.6.5 LDO specifications

6.4.6.5.1 VGEN1

Table 99. Register VGEN6CTL - ADDR 0x71 VGEN6 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 92 for all possible configurations. Table 100. LDO external components

1. Use X5R/X7R ceramic capacitors.

Table 101. VGEN1 electrical characteristics

• I GEN1 = 75 mA, 20 Hz to 20 kHz VGEN1[3:0] = 0000 - 1101 VGEN1[3:0] = 1110, 1111 dB (63) NOISEVGEN1 Output noise density VIN1 = 1.75 V, IGEN1 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -108 -118 -124 -100 -108 -112 dBV/ √Hz SLWR VGEN1 Turn-on slew rate
• 10% to 90% of end value
• 1.75 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA VGEN1[3:0] = 0000 to 0111 VGEN1[3:0] = 1000 to 1111 12.5 16.5 mV/μs GEN1tON Turn-on time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN1 = 0.0 mA 60 – 500 μs GEN1tOFF Turn-off time Disable to 10% of initial value, VIN1 = 1.75 V IGEN1 = 0.0 mA –– 1 0 m s GEN1OSHT Start-up overshoot VGEN1LOTR Transient load response
• V IN1 = 1.75 V, 3.4 V IGEN1 = 10 mA to 100 mA in 1.0 μs. Peak of overshoot or undershoot of VGEN1 with respect to final value
• Refer to Figure 25 –– 3 . 0 %

Table 101. VGEN1 electrical characteristics (continued)

82 NXP Semiconductors

6.4.6.5.2 VGEN2

• I GEN1 = 75 mA VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN1[3:0] = 0000 to 1101 VIN1 INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for VGEN1[3:0] = 1110, 1111
• Refer to Figure 25 –5 . 0 8 . 0 m V Notes 63. The PSRR of the regulators is measured with the perturbing sig nal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test.

Table 102. VGEN2 electrical characteristics VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.

• I GEN2 = 187.5 mA, 20 Hz to 20 kHz VGEN2[3:0] = 0000 - 1101 VGEN2[3:0] = 1110, 1111 dB NOISEVGEN2 Output noise density
• V IN1 = 1.75 V, IGEN2 = 187.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -108 -118 -124 -100 -108 -112 dBV/√Hz SLWR VGEN2 Turn-on slew rate
• 10% to 90% of end value
• 1 . 7 5 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA VGEN2[3:0] = 0000 to 0111 VGEN2[3:0] = 1000 to 1111 12.5 16.5 mV/μs GEN2tON Turn-on time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN2 = 0.0 mA 60 – 500 μs GEN2tOFF Turn-off time Disable to 10% of initial value, VIN1 = 1.75 V IGEN2 = 0.0 mA –– 1 0 m s GEN2OSHT Start-up overshoot VGEN2LOTR Transient load response VIN1 = 1.75 V, 3.4 V IGEN2 = 25 mA to 250 mA in 1.0 μs Peak of overshoot or undershoot of VGEN2 with respect to final value Refer to Figure 25 –– 3 . 0 % VGEN2LITR Transient line response IGEN2 = 187.5 mA VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN2[3:0] = 0000 to 1101 VIN1INITIAL = VGEN2+0.3 V to VIN1FINAL = VGEN2+0.8 V for VGEN2[3:0] = 1110, 1111 Refer to Figure 25 –5 . 0 8 . 0 m V Notes 64. The PSRR of the regulators is measured with the perturbing signa l at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test.

Table 102. VGEN2 electrical characteristics (continued) VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.

84 NXP Semiconductors

6.4.6.5.3 VGEN3

Table 103. VGEN3 electrical characteristics

• I GEN3 = 75 mA, 20 Hz to 20 kHz VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V dB (66) NOISEVGEN3 Output noise density
• V IN2 = VIN2MIN, IGEN3 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN3 Turn-on slew rate
• 10% to 90% of end value
• V I N 2MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA VGEN3[3:0] = 0000 to 0011 VGEN3[3:0] = 0100 to 0111 VGEN3[3:0] = 1000 to 1011 VGEN3[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs GEN3 tON Turn-on time Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V IGEN3 = 0.0 mA 60 – 500 μs

6.4.6.5.4 VGEN4

1. When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper

regulation due to the dropout voltage generated through the internal LDO transistor.

1. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately

region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage. Table 104. VGEN4 electrical characteristics Table 103. VGEN3 electrical characteristics (continued)

86 NXP Semiconductors

• I GEN4 = 262.5 mA, 20 Hz to 20 kHz VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V dB (68) NOISEVGEN4 Output noise density
• V IN2 = VIN2MIN, IGEN4 = 262.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN4 Turn-on slew rate
• 10% to 90% of end value
• V I N 2MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA VGEN4[3:0] = 0000 to 0011 VGEN4[3:0] = 0100 to 0111 VGEN4[3:0] = 1000 to 1011 VGEN4[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs GEN4 tON Turn-on time Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V IGEN4 = 0.0 mA 60 – 500 μs GEN4tOFF Turn-off time Disable to 10% of initial value, VIN2 = VIN2MIN IGEN4 = 0.0 mA –– 1 0 m s GEN4OSHT Start-up overshoot VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA –1 . 0 2 . 0 % VGEN4LOTR Transient load response VIN2 = VIN2MIN, 3.6 V IGEN4 = 35 mA to 350 mA in 1.0 μs Peak of overshoot or undershoot of VGEN4 with respect to final value. Refer to Figure 25 –– 3 . 0 %

Table 104. VGEN4 electrical characteristics (continued)

6.4.6.5.5 VGEN5

1. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage need to be at least the output voltage plu s 0.25 V for proper

regulation due to the dropout voltage generated through the internal LDO transistor.

1. The PSRR of the regulators is measured with the perturbing signa l at the input of the regulator. The power management IC is supplied separately

region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage. Table 105. VGEN5 electrical characteristics

88 NXP Semiconductors

• I GEN5 = 75 mA, 20 Hz to 20 kHz VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V dB (70) NOISEVGEN5 Output noise density
• V IN3 = VIN3MIN, IGEN5 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN5 Turn-on slew rate
• 10% to 90% of end value
• V I N 3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA VGEN5[3:0] = 0000 to 0011 VGEN5[3:0] = 0100 to 0111 VGEN5[3:0] = 1000 to 1011 VGEN5[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs GEN5 tON Turn-on time Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V IGEN5 = 0.0 mA 60 – 500 μs GEN5tOFF Turn-off time Disable to 10% of initial value, VIN3 = VIN3MIN IGEN5 = 0.0 mA –– 1 0 m s GEN5OSHT Start-up overshoot VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA –1 . 0 2 . 0 % VGEN5LOTR Transient load response VIN3 = VIN3MIN, 4.5 V IGEN5 = 10 to 100 mA in 1.0 μs Peak of overshoot or undershoot of VGEN5 with respect to final value. Refer to Figure 25 –– 3 . 0 % VGEN5LITR Transient line response IGEN5 = 75 mA VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN5[3:0] = 0000 to 0111 VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for VGEN5[3:0] = 1000 to 1111 Refer to Figure 25 -5 . 0 8 . 0 m V Notes 69. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 70. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.

Table 105. VGEN5 electrical characteristics (continued)

6.4.6.5.6 VGEN6

Table 106. VGEN6 electrical characteristics

• I GEN6 = 150 mA, 20 Hz to 20 kHz VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V dB (72) NOISEVGEN6 Output noise density
• V IN3 = VIN3MIN, IGEN6 = 150 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz -114 -129 -135 -102 -123 -130 dBV/√Hz SLWR VGEN6 Turn-on slew rate
• 10% to 90% of end value
• V I N 3MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA VGEN6[3:0] = 0000 to 0011 VGEN6[3:0] = 0100 to 0111 VGEN6[3:0] = 1000 to 1011 VGEN6[3:0] = 1100 to 1111 22.0 26.5 30.5 34.5 mV/μs

90 NXP Semiconductors

6.4.7 VSNVS LDO/switch

the switch, which is 40 mV at a rated maximum load current of 400 μA. certain conditions are met as described in Table 107.

1. When the LDO output voltage is set above 2.6 V, the minimu m allowed input voltage needs to be at least the output voltage plus 0.25 V for proper

regulation due to the dropout voltage generated through the internal LDO transistor.

1. The PSRR of the regulators is measured with the perturbing si gnal at the input of the regulator. The power management IC is supplied separately

region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage. Table 106. VGEN6 electrical characteristics (continued)

Figure 26. VSNVS supply switch architecture

6.4.7.0.1 VSNVS control

The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 108.

6.4.7.0.2 VSNVS external components

Table 107. VSNVS modes of operation Table 108. Register VSNVSCTL - ADDR 0x6B

1. Only valid when a valid input voltage is present.

Table 109. VSNVS external components

2.25 V (VTL0) -

92 NXP Semiconductors

6.4.7.0.3 VSNVS specifications

Table 110. VSNVS electrical characteristics VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.

• 5 . 0 μA < ISNVS < 400 μA (off) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
• 5 . 0 μA < ISNVS < 400 μA (on) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
• 5 .0 μA < ISNVS < 400 μA (coin cell mode) 2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110 1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101] -5.0% -8.0% -5.0% -4.0% VCOIN-0.04 -8.0% 3.0 1.0 - 1.8 3.0 1.0 - 1.8 1.0 - 1.8 7.0% 7.0% 5.0% 4.0% VCOIN 7.0% V (77) VSNVSDROP Dropout voltage 2.85 V < VIN < 2.9 V, VSNVSVOLT[2:0] = 110 5.0 μA < ISNVS < 400 μA –– 5 0 m V ISNVSLIM Current limit PF0100Z VIN > VTH1, VSNVSVOLT[2:0] = 110 VIN > VTL0, VSNVSVOLT[2:0] = 000 to 101 VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 PF0100AZ V IN > VTH1, VSNVSVOLT[2:0] = 110 VIN > VTL0, VSNVSVOLT[2:0] = 000 to 101 VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 750 500 480 1100 500 480 5900 5900 3600 6750 6750 4500 μA VTH0 VIN threshold (coin cell powered to VIN powered) VIN going high with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.25 2.40 2.55 V VTL0 VIN threshold (VIN powered to coin cell powered) VIN going low with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.20 2.35 2.50 V VHYST1 VIN threshold hysteresis for VTH1-VTL1 5.0 – – mV VHYST0 VIN threshold hysteresis for VTH0-VTL0 5.0 – – mV VSNVSCROSS Output voltage during crossover VSNVSVOLT[2:0] = 110 VCOIN > 2.9 V Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA 2.7 – – V (74)

6.4.7.1 Coin cell battery backup

1. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though t his is outside

back to the external crystal oscillator.

1. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tr1 time.
2. From coin cell insertion to VSNVS = 1. 0 V, the delay time is typically 400 ms.
3. For 1.8 V I SNVS limited to 100 μA for VCOIN < 2.1 V

Table 110. VSNVS electrical characteristics (continued) VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.

94 NXP Semiconductors

6.4.7.1.1 Coin cell charger control

is not available as the main battery could be depleted unnecessarily. The coin cell charging is stopped when VIN is below UVDET.

6.4.7.1.2 External components

6.4.7.1.3 Coin cell specifications

Table 111. Coin cell charger voltage

1. Coin cell voltages selected based on the

type of LICELL used on the system. Table 112. Register COINCTL - ADDR 0x1A Coin cell charger output voltage selection. Table 113. Coin cell charger external components Table 114. Coin cell charger specifications

6.5 Control interface I 2C block description

SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of 4.8 kΩ.

6.5.1 I2C device ID

address; these bits take affect right away.

6.5.2 I 2C operation

will be sent out unless a STOP command or NACK is received prior to completion. transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction. Figure 27. I2C write example Figure 28. I2C read example

96 NXP Semiconductors

6.5.3 Interrupt handling

existing interrupt bit, the INTB pin remains low. INTB pin goes low after unmasking. read only, and not latched or clearable. asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

6.5.4 Interrupt bit summary

Table 115. Interrupt, Mask and Sense Bits

A full description of all interrupt, mask, and sense registers is provided in Tables 116 to 127.

1. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].

Table 116. Register INTSTAT0 - ADDR 0x05 Table 117. Register INTMASK0 - ADDR 0x06 Table 115. Interrupt, Mask and Sense Bits (continued)

98 NXP Semiconductors

Table 118. Register INTSENSE0 - ADDR 0x07 Table 119. Register INTSTAT1 - ADDR 0x08 Table 120. Register INTMASK1 - ADDR 0x09

Table 121. Register INTSENSE1 - ADDR 0x0A Table 122. Register INTSTAT3 - ADDR 0x0E Table 123. Register INTMASK3 - ADDR 0x0F Table 124. Register INTSENSE3 - ADDR 0x10

100 NXP Semiconductors

Table 125. Register INTSTAT4 - ADDR 0x11 Table 126. Register INTMASK4 - ADDR 0x12 Table 127. Register INTSENSE4 - ADDR 0x13

6.5.5 Specific registers

6.5.5.1 IC and version identification

The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 128 to 130.

6.5.5.2 Embedded memory

Table 128. Register DEVICEID - ADDR 0x00 DEVICEID 3:0 R 0x00 Die version. Table 129. Register SILICON REV- ADDR 0x03 Table 130. Register FABID - ADDR 0x04 Table 132. Register MEMB ADDR 0x1D

102 NXP Semiconductors

6.5.6 Register Bitmap

pages, no write to the page register is necessary.

• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear Reset: Reset signals are color coded based on the following legend. Default: The value after reset, as noted in the default column of the memory map.
• Fixed defaults are explic itly declared as 0 or 1.
• “X” corresponds to Read / Write bits initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits which may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts.

Table 133. Register MEMC ADDR 0x1E Table 134. Register MEMD ADDR 0x1F

6.5.6.1 Register map

Table 135. Functional page

00 DeviceID R 8'b0001_0000

03 SILICONREVID R 8'b0001_0000

04 FABID R 8'b0000_0000

05 INTSTAT0 RW1C 8'b0000_0000

06 INTMASK0 R/W 8'b0011_1111

07 INTSENSE0 R 8'b00xx_xxxx

08 INTSTAT1 RW1C 8'b0000_0000

09 INTMASK1 R/W 8'b0111_1111

10 INTSENSE3 R 8'b0000_000x

11 INTSTAT4 RW1C 8'b0000_0000

12 INTMASK4 R/W 8'b0011_1111

13 INTSENSE4 R 8'b00xx_xxxx

104 NXP Semiconductors

20 SW1ABVOLT R/W/M 8'b00xx_xxxx

21 SW1ABSTBY R/W 8'b00xx_xxxx

22 SW1ABOFF R/W 8'b00xx_xxxx

23 SW1ABMODE R/W 8'b0000_1000

24 SW1ABCONF R/W 8'bxx00_xx00

30 SW1COFF R/W 8'b00xx_xxxx

31 SW1CMODE R/W 8'b0000_1000

32 SW1CCONF R/W 8'bxx00_xx00

35 SW2VOLT R/W 8'b0xxx_xxxx

36 SW2STBY R/W 8'b0xxx_xxxx

37 SW2OFF R/W 8'b0xxx_xxxx

Table 135. Functional page (continued)

38 SW2MODE R/W 8'b0000_1000

39 SW2CONF R/W 8'bxx01_xx00

40 SW3ACONF R/W 8'bxx10_xx00

43 SW3BVOLT R/W 8'b0xxx_xxxx

44 SW3BSTBY R/W 8'b0xxx_xxxx

45 SW3BOFF R/W 8'b0xxx_xxxx

46 SW3BMODE R/W 8'b0000_1000

47 SW3BCONF R/W 8'bxx10_xx00

106 NXP Semiconductors

66 SWBSTCTL R/W 8'b0xx0_10xx

70 VGEN5CTL R/W 8'b000x_xxxx

71 VGEN6CTL R/W 8'b000x_xxxx

Table 136. Extended page 1

80 OTP FUSE READ

84 OTP LOAD MASK R/W 8'b0000_0000

Table 136. Extended page 1 (continued)

108 NXP Semiconductors

110 NXP Semiconductors

1. In the PF0100Z FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for

required to set all of the FUSE_PORx bits to be able to load the fuses. Table 137. Extended page 2

81 SW1AB PWRSTG R/W 8'b1111_1111

82 PWRSTG RSVD R 8'b0000_0000

83 SW1C PWRSTG R 8'b1111_1111

84 SW2 PWRSTG R 8'b1111_1111

85 SW3A PWRSTG R 8'b1111_1111

86 SW3B PWRSTG R 8'b1111_1111

87 SW4 PWRSTG R 8'b0111_1111

88 PWRCTRL OTP

90 IO DRV R/W 8'b00xx_xxxx

Table 137. Extended page 2 (continued)

112 NXP Semiconductors

1. Do not write in reserved registers.

7 Typical applications

7.1 Introduction

references and additional components such as filters, refer to the individual sections.

7.1.1 Application diagram

Figure 29. Typical application schematic

114 NXP Semiconductors

7.1.2 Bill of materials

Table 138. Bill of materials (82)

1 Power management IC MMPF0100Z NXP

Table 138. Bill of materials (82) (continued)

116 NXP Semiconductors

1.0 A 1 20 V SOD-123FL MBR120VLSFT1G ON Semiconductor Schottky diode

7.2 PF0100Z layout guidelines

7.2.1 General board recommendations

1. It is recommended to use an eight layer board stack-up arranged as follows:

• High current signal
• G N D
• Signal
• P o w e r
• P o w e r
• Signal
• G N D
• High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.

7.2.2 Component placement

7.2.3 General routing requirements

1. Some recommended things to keep in mind for manufacturability:

• Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
• Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils 2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be also shielded. 3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node (i.e. SW1ALX, SW1BLX, SW1CLX, SW2LX, SW3ALX, SW3BLX, SW4LX, and SWBSTLX). 5. Make sure all components related to a specific block are referenced to the corresponding ground. Miscellaneous 0.1 μF 1 10 V X5R 0402 CD402C104K8PAC Kemet VDDIO 1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VIN 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER PWRON 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER RESETBMCU 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER SDWN 100 kΩ 1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER INTB Notes 82. NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.

118 NXP Semiconductors

7.2.4 Parallel routing requirements

• CLK is the fastest signal of the system, so it must be given special care.
• To avoid contamination of these delicate si gnals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.

Figure 30. Recommended shielding for critical signals.

• These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
• Care must be taken with these signals not to contaminate anal og signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

7.2.5 Switching regulato r layout recommendations

1. Per design, the switching regulators in PF0100Z are designed to operate with only one input bulk capacitor. However, it is

should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.

1. Make high-current ripple traces low-inductance (short, high W/L ratio).
2. Make high-current traces wide or copper islands.
3. Make high-current traces symetrical for dual–phase regulators (SW1, SW3).

Figure 31. Generic buck regulator architecture Figure 32. Recommended layout for buck regulators

7.3 Thermal information

7.3.1 Rating data

The thermal rating data of the packages has been simulated with the results listed in Table 5. test boards. It is anticipated the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.

120 NXP Semiconductors

7.3.2 Estimation of junction temperature

An estimation of the chip junction temperature TJ can be obtained from the equation: TJ = TA + (RθJA x PD) with: TA = Ambient temperature for the package in °C RθJA = Junction to ambient thermal resistance in °C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value provideing a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four layer board R θJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RθJB x PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See 6 Functional block requirements and behaviors, page 17 for more details on thermal management.

8 Packaging

8.1 Packaging dimensions

characteristics for each package. Table 139. Package drawing information

122 NXP Semiconductors

124 NXP Semiconductors

9 Reference section

9.1 Reference documents

Table 140. PF0100Z reference documents

126 NXP Semiconductors

REVISION HISTORY

10.1 Document changes

Revision Date Description of Changes 1.0 11/2012 • Initial release 2.0 1/2013

• Deleted unneeded rows from Ordering information and updated part number
• Changed Note 2
• Added Note 4 to Pin Definitions and as signed it to the applicable pin names
• Corrected Functional Block diagram
• Corrected pin name in section 7.1
• Deleted unnecessary columns in Table 9
• Added section 7.2.1 and fixed TOC
• Corrected FF row in Table 136
• Corrected schematics 10, 11, 12, 14, 16, 17, 18, 20, and 22
• Corrected page one package isometric
• Added warning to note 6
• Changed graphics on figures 13, 15, 19, and 21
• Deleted original note 64.
• Deleted reference to ICOINLO in Coin Cell Charger Control
• Updated figure 28
• Corrected part number in BOM
• Corrected #4 in General Routing Requirements
• Added AN4622 to Reference Documents 3.0 2/2013
• Separated VSNS pin for HBM page 9
• Reworded sentence in Programming OTP fuses
• Added 2.0 MHz clock frequency
• Changed min. for VREFDDR Current Limit
• Changed min. for VGEN1 DC Current Limit
• Changed min. for VGEN1 DC Overcurrent Protection Threshold
• Changed max. for VGEN2 ACTIVE MODE - DC Current Limit
• Changed min. for VGEN3 DC Current Limit
• Changed min. for VGEN4 DC Current Limit
• Changed min. for VGEN5 ACTIVE MODE - DC Current Limit
• Changed min. for VGEN6 DC Current Limit
• Changed min. for VGEN6 DC Overcurrent Protection Threshold
• Changed max. for VSNVS DC, LDO VIN Threshold, VIN going high with valid coin cell
• Changed max. for VSNVS DC, LDO VIN Threshold, VIN going low with valid coin cell
• Added note to VSNVS AC AND TRANSIENT Turn-on Time, and deleted notation of conditions
• Register D8 and D9 in table 137 marked as reserved.
• Added Figure 4
• Updated table 8. Current consumption summary.

4.0 4/2014

• Added new package name and drawing for PF0100AZ
• Added Table 2 listing differences between PF0100Z and PF0100AZ
• Corrected VDDOTP maximum rating
• Corrected SWBSTFB maximum rating
• Updated Table 8 to included PF0100AZ specifications
• Updated Figure 4
• Added note of FUSE_POR-XOR bit for PF0100AZ in OTP prototyping
• Corrected 2.0 MHz clock minimum specif ication from 1.85 MHz to 1.84 MHz in 16 MHz and 32 kHz clocks
• Corrected inductor Isat for SW1ABC single phase mode from 4.5 A to 6.0 A
• Tightened accuracy specification in PF M mode for all the switching regulators
• Corrected typical efficiency specif ications for all switching regulators
• Added note to clarify SWBST default operation in Auto mode
• Added current limit specifications for VGEN2, VGEN6, and VSNVS for PF0100AZ
• Corrected conditions for VSN VS turn-on time specifications
• Changed VTH1 maximum specification from 3.05 V to 3.1 V
• Updated Control interface I2C block description to include note about SCL/SDA drive strength
• Corrected default values of bi ts in INTMASK0 register in Table 118
• Corrected default value of 4 MSBs in Table 128
• Corrected default value of bits in SILICONREVID register in Table 126
• Updated Typical Application Schematic to add bypass capacitor on VDDIO pin
• Added capacitor at VDDIO pin in Bill of Material table
• Noted that voltage settings 0.6 V and below are not supported
• VSNVS Turn On Delay (td1) spec corrected from 15 ms to 5.0 ms
• Updated per GPCN 16220 5.0 10/2014
• Updated as per PB 16482
• Increased ambient operating temperature of MMPF0100NPAZES device
• Added additional specification li ne items for Standby current, Sleep current, and VREFDDR accuracy for the extended temperature operation
• Added new part number MMPF0100F8AZES
• Updated Table 9 6.0 11/2014
• Corrected the temperature range for the device MMPF0100F8AZES in Table 1
• Updated Table 23
• Updated Bill of Materials Table 138 7.0 7/2015 • Added new part numbers MMPF0100F9AZES and MMPF0100FAAZES to Table 1
• Updated Table 9 8.0
• Added MMPF0100F0AZES to Table 1
• Updated Table 9
• Updated Table 52
• Updated Table 137 10/2015 • Fixed typo on page 1 9.0 12/2015
• Removed MMPF0100NPZES from Orderable part variations. No longer manufactured.
• Added MMPF0100F6AZES to Orderable part variations
• Updated Table 9 for MMPF0100F6AZES 10.0 3/2016 • Updated SW2 current capability from 2000 mA to 2500 mA for F9/FA versions 11.0 5/2016 • Changed Table 9 row - Default I2C Address from 0x80 to 0x08 for F0, F9, and FA 12.0 8/2016 • Added NP version to OTP's with SW2 current capability of 2500 mA
• Added BOM for SW1ABC Revision Date Description of Changes

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Document Number: MMPF0100Z Rev. 12.0