MMPF0100 FREESCALE | Alldatasheet
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Technical content
Applications
- T a b l e t s
- I P T V
- Industrial control
- Medical monitoring
- Home automation/ alarm/ energy management EP SUFFIX (E-TYPE)
56 QFN 8X8
Document order number: MMPF0100 Rev. 3.0, 10/2012 Freescale Semiconductor Advance Information * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2012. All rights reserved.
14 Channel Configurable Power
Management Integrated Circuit The PF0100 Power Management Integrated Circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With up to six buck converters, six linear regulators, RTC supply, and coin-cell charger, the PF0100 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip One Time Programmable (OTP) memory, the PF0100 is available in pre-programmed standard versions, or non-programmed to support custom programming. The PF0100 is especially suited to the I.MX6 family of devices and is supported by full system level reference designs, and pre- programmed versions of the device. Features:
- Four to six buck converters, depending on configuration
- Single/ Dual phase/ parallel options
- DDR termination tracking mode option
- Boost regulator to 5.0 V out
- Six general purpose linear regualtors
- Programmable output voltage, sequence, and timing
- OTP (One Time Programmable) memory for device configuration
- Coin cell charger and RTC supply
- DDR termination reference voltage
- Power control logic with processor interface and event detection 2C control
- Individually programmable ON, OFF, and Standby modes VGEN3 100 mA VGEN5 100 mA Camera Audio Codec Cluster/HUD External AMP Microphones Speakers Front USB POD Rear USB POD Rear Seat Infotaiment Sensors i.MX6X I2C Communication I2C Communication PF0100 Control Signals Parallel control/GPIOS LICELL Charger COINCELL Main Supply 2.8 – 4.5 V VGEN1 100 mA VGEN2 250 mA VGEN4 350 mA VGEN6 200 mA SWBST 600 mA SW3A/B 2500 mA SW1C 2000 mA SW1A/B 2500 mA SW2 2000 mA SW4 1000 mA GPS MIPI uPCIe SATA - FLASH NAND - NOR Interfaces Processor Core Voltages Camera VREFDDR DDR Memory DDR MEMORY INTERFACE SD-MMC/ NAND Mem. SATA HDD WAM GPS MIPI HDMI LDVS Display USB Ethernet CAN
Figure 1. Simplified Application Diagram
Analog Integrated Circuit Device Data
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Analog Integrated Circuit Device Data Freescale Semiconductor 3 PF0100
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1 Orderable Parts
Table 1. Orderable Part Variations
- For Tape and Reel add an R2 suffix to the part number.
- For programming details see Table 9.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 PF0100 Part Identification
Description
2 Part Identification
This section provides an explanation of the part numbers and their alphanumeric breakdown.
2.1 Description
Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received.
2.2 Format and Fields Description
The part number is structured in the following format: MM-ff-xxxx-yy-r-v-PP-RR Table 2 shows the meaning and possible values for each field contained in the part number (not all combinations are valid). Table 2. Part Number Structure Definition
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3 Internal Block Diagram
Figure 2. Simplified Internal Block Diagram
4 Pin Connections
4.1 Pinout Diagram
Figure 3. Pinout Diagram
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4.2 Pin Definitions
Table 3. PF0100 Pin Definitions Analog Reserved pin. Connect to GND in application. externally to GNDREF through a board ground plane. externally to GNDREF, via board ground plane. capacitor as close to the pin as possible.
close to the pin as possible. capacitor as close to the pin as possible. externally via the board ground plane. close to the pin as possible. Table 3. PF0100 Pin Definitions (continued)
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48 GNDREF GND - GND Ground reference for the main band gap regulator. allow effective thermal dissipation.
5 General Product Characteristics
5.1 Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
- ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
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5.2 Thermal Characteristics
5.2.1 Power Dissipation
THERMxxxS bits in register INTSENSE0. should be configured such that this protection is not tripped under normal conditions. Table 5. Thermal Ratings
- Do not operate beyond 125 °C for extended periods of time. See Table 6 for thermal protection features.
- Pin soldering temperature limit is for 10 seconds maximum durat ion. Not designed for immersion soldering. Exceeding these limits may
cause a malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
- The Board uses the JEDEC specifications for th ermal testing (and simulation) JESD51-7 and JESD51-5.
- Per JEDEC JESD51-6 with the board horizontal.
- Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1 ).
- Thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Analog Integrated Circuit Device Data Freescale Semiconductor 13 PF0100 General Product Characteristics
Electrical Characteristics
5.3 Electrical Characteristics
5.3.1 General Specifications
Table 6. Thermal Protection Thresholds Table 7. General PMIC Static Characteristics.
Analog Integrated Circuit Device Data
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General Product Characteristics
5.3.2 Current Consumption
The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary table follows for standard use cases. Table 8. Current Consumption Summary 25 °C, unless otherwise noted.
- When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
Analog Integrated Circuit Device Data Freescale Semiconductor 15 PF0100 General Description
Features
6 General Description
The PF0100 is the Power Management Integrated Circuit (PMIC) designed primarily for use with Freescale’s i.MX6 series of application processors.
6.1 Features
This section summarizes the PF0100 features.
- Input voltage range to PMIC: 2.8 - 4.5 V
- Buck regulators
- Four to six channel configurable
- SW1A/B/C, 4.5 A (single); 0.3 to 1.875 V
- SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 to 1.875 V
- S W 2 , 2 . 0 A; 0.4 to 3.3 V
- SW3A/B, 2.5 A (single/dual); 0.4 to 3.3 V
- SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V
- S W 4 , 1 . 0 A; 0.4 to 3.3 V
- SW4, VTT mode provide DDR termination at 50% of SW3A
- Dynamic voltage scaling
- Modes: PWM, PFM, APS
- Programmable output voltage
- Programmable current limit
- Programmable soft start
- Programmable PWM switching frequency
- Programmable OCP with fault interrupt
- Boost regulator
- SWBST, 5.0 to 5.15 V, 0.6 A, OTG support
- Modes: PFM and Auto
- OCP fault interrupt
- L D O s
- Six user programable LDO
- VGEN1, 0.80 to 1.55 V, 100 mA
- VGEN2, 0.80 to 1.55 V, 250 mA
- VGEN3, 1.8 to 3.3 V, 100 mA
- VGEN4, 1.8 to 3.3 V, 350 mA
- VGEN5, 1.8 to 3.3 V, 100 mA
- VGEN6, 1.8 to 3.3 V, 200 mA
- Soft start
- LDO/Switch supply
- DDR memory reference voltage
- VREFDDR, 0.6 to 0.9 V, 10 mA
- 1 6 MHz internal master clock
- OTP(One time programmable) me mory for device configuration
- User programmable start-up sequence and timing
- Battery backed memory including coin cell charger
- I 2C interface
- User programmable Standby, Sleep, and Off modes
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6.2 Functional Block Diagram
Figure 4. Functional Block Diagram
6.3 Functional Description
6.3.1 Power Generation
allow controlled supply rail adjustments for the processor cores and/or other circuitry. the i.MX processors; VSNVS may be powered from VIN, or from a coin cell.
6.3.2 Control Logic
for the coin cell is included as well.
Analog Integrated Circuit Device Data Freescale Semiconductor 17 PF0100 General Description Functional Description
6.3.2.1 Interface Signals
PWRON is an input signal to the IC that generates a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG bit. Refer to section Turn On Events for more details. STANDBY STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section Standby Mode for more details. Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide VSNVS, or the PMIC will not reliably enter and exit the STANDBY mode. RESETBMCU RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 5 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100 is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described above will be repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on Extended Page 1 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses. SDWNB SDWNB is an open-drain, active low output that notifies the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock cycle before powering down and is then de-asserted in the OFF state. INTB INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is de-asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
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7 Functional Block Requirements and Behaviors
7.1 Start-up
100kohm resistor. The OTP configuration is enabled by connecting VCOREDIG to GND.
7.1.1 Device Start-up Configuration
programmed OTP configurations. Table 9. Start-up Configuration
*VSNVS will start from 1.0 V if LICELL is valid before VIN.
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Figure 5. Default Start-up Sequence Table 10. Default Start-up Sequence Timing
7.1.2 One Time Prog rammability (OTP)
code(ECC) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. The parameters that can be configured by OTP are listed below.
- General: I 2C slave address, PWRON pin configuration, start-up sequence and timing
- Buck regulators: Output voltage, dual/single phase or i ndependent mode configuration, switching frequency, and soft start ramp rate
- Boost regulator and LDOs: Output voltage NOTE: When prototyping or programming fuses, the user must ensure that register settings are consistent with the hardware configuration. This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single/dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it will be gated by the buck regulator in the start-up sequence.
7.1.2.1 Start-up Sequence and Timing
sequence and will remain off. See Table 11. The delay between each position is equal; however, four delay options are available. See Table 12. The start-up sequence will terminate at the last programmed regulator.
- Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may
extend to a maximum of 24 ms.
- Depends on the external signal driving PWRON.
- Rise time is a function of slew rate of regulators and nominal voltage selected.
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7.1.2.2 PWRON Pin Configuration
on the part and if the switch is held low for greater than or equal to 4.0 seconds, the part will turn off or enter Sleep mode.
7.1.2.3 I 2C Address Configuration
address (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 14. Table 11. Start-up Sequence
00000 Off
00001 SEQ_CLK_SPEED[1:0] * 1
00010 SEQ_CLK_SPEED[1:0] * 2
11111 SEQ_CLK_SPEED[1:0] * 31
Table 12. Start-up Sequence Clock Speed Table 13. PWRON Configuration
0 PWRON pin HIGH = ON
1 PWRON pin pulled LOW momentarily = ON
Table 14. I2C Address Configuration
7.1.2.4 Soft Start Ramp Rate
The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in Dynamic Voltage Scaling.
7.1.3 OTP Prototyping
shown in Table 136 and Table 137. into the TBBOTP registers depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR bits.
- If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
- If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 1, the values are loaded from the fuses.
- If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 0, the TBBOTP registers remain initialized at zero. The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP registers maintained and not loaded from a different source. The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 1 and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping.
7.1.4 Reading OTP Fuses
OTP fuses, see application note AN4536.
7.1.5 Programming OTP Fuses
located in Extended Page 2 of the register map. There are ten banks of twenty-six fuses each that can be programmed. Programming the fuses requires an 8.25 V, 100 mA supply powering the VDDOTP pin, bypassed with 10 to 20 μF of capacitance. For more details on programming the OTP fuses, see application note AN4536.
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16 MHz and 32 kHz Clocks
- VIN < UVDET
- All regulators are in SLEEP mode
- All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
- During start-up, VIN > UVDET
- PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 26 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.
7.3 Bias and References Block Description
7.3.1 Internal Core Voltage References
kept powered as long as there is a valid supply and/or valid coin cell. Table 17 shows the main characteristics of the core circuitry. Table 15. Source of Start-up Sequence Table 16. 16 MHz Clock Specifications characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
7.3.1.1 External Components
7.3.2 VREFDDR Voltage Reference
low frequency pole. This divider then utilizes a voltage follower to drive the load. Table 17. Core Voltages Electrical Specifications(21) characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
- 3.0 V < V IN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system
Table 18. External Components for Core Voltages
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Figure 6. VREFDDR Block Diagram
7.3.2.1 VREFDDR Control Register
The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 19. Table 19. Register VREFDDCRTL - ADDR 0x6A Table 20. VREFDDR External Components(22)
- Use X5R or X7R capacitors.
- VINREFDDR to GND, 1.0 μF minimum
capacitance is provided by buck regulator output.
Table 21. VREFDDR Electrical Characteristics
- When VREFDDR is off there is a quiescent current of 1.5 μA typical.
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7.4 Power Generation
7.4.1 Modes of Operation
the state diagram of the PF0100, along with the cond itions to enter and exit from each state. Figure 7. State Diagram not possible in the Coin Cell mode and the interrupt signal, INTB, is only active in Sleep, Standby, and ON states.
7.4.1.1 ON Mode
The PF0100 enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.
7.4.1.2 OFF Mode
VCOREDIG and VSNVS are powered in the mode of operation. To exit the Off mode, a valid turn-on event is required. RESETBMCU is asserted, LOW, in this mode.
7.4.1.3 Standby Mode
- Depending on STANDBY pin configuration, St andby is entered when the STANDBY pin is asserted. This is typically used for low-power mode of operation.
- When STANDBY is de-asserted, Standby mode is exited. A product may be designed to go into a Low-power mode after periods of inactivity. The STANDBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby is pre- programmed through the I2C interface. Note that the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarity as shown in Table 22. When the PF0100 is powered up first, regulator settings for the Standby mode are mirrored from the regulator settings for the ON mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY will generally be referred to as active high throughout this document. Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into Standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 23, STBYDLY will delay the Standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event.
Table 22. Standby Pin and Polarity Control
- STANDBY = 0: System is not in Sta ndby, STANDBY = 1: System is in Standby
- The state of the STANDBY pin only has influence in On mode.
- Bit 6 in Power Control Register (ADDR - 0x1B)
Table 23. STANDBY Delay - Initiated Response
00 No Delay
01 One 32 k period (default)
10 Two 32 k periods
11 Three 32 k periods
- Bits [5:4] in Power Control Register (ADDR - 0x1B)
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7.4.1.4 Sleep Mode
- Depending on PWRON pin configuration, Sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
- To exit Sleep mode, assert the PWRON pin. In the Sleep mode, the regulator will use the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 24 shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event.
7.4.1.5 Coin Cell Mode
Coin Cell state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. Table 24. Regulator Mode Control
- For sleep mode, an activated switching regulator, should use the off
SWxOFF[6:0] for SW2, SW3A/B, and SW4.
7.4.2 State Machine Flow Summary
7.4.2.1 Turn On Events
- If PWRON_CFG = 0, the PWRON signal is high and V IN > UVDET, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set.
- If PWRON_CFG = 1, V IN > UVDET and PWRON transitions from high to low, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set.
Table 25. State Machine Flow Summary
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PWRONDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode.
7.4.2.2 Turn Off Events
- PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
- PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRS TEN = 1 and PWRON is held low for longer than 4.0
seconds. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. Dissipation section for more detailed information.
7.4.3 Power Tree
cell. Refer to Table 27 for a summary of all power supplies provided by the PF0100. Table 26. PWRON Hardware Debounce Bit Settings
- The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.
the system’s voltage and current requirements, therefore a proper input voltage should be selected for the regulators. summarizes the UVDET thresholds. Table 27. Power Tree Summary
- Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up
Table 28. UVDET Threshold
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Figure 8. PF0100 Typical Power Map
7.4.4 Buck Regulators
Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.
7.4.4.1 Current Limit
current limit condition persists for more than 8.0 ms, a fault interrupt is generated.
7.4.4.2 General Control
load current variation. Available switching modes for buck regulators are presented in Table 29. Table 30 summarizes the Buck regulator programmability for Normal and Standby modes. Table 29. Switching Mode Description OFF The regulator is switched off and the output voltage is discharged. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. mode depending on load conditions. Table 30. Regulator Mode Control
0000 Off Off
0001 PWM Off
0010 Reserved Reserved
0011 PFM Off
0100 APS Off
0101 PWM PWM
0110 PWM APS
0111 Reserved Reserved
1000 APS APS
1001 Reserved Reserved
1010 Reserved Reserved
1011 Reserved Reserved
1100 APS PFM
1101 PWM PFM
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each regulator, the output voltage options are the same for Normal and Standby modes. output voltage programmed in its voltage register. set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.
- Normal operation: The output voltage is selected by I 2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B,
and SW4. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 33 and Table 34.
- Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the
SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.
- Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest
SW1xDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively. Table 31, Table 32, Table 33, and Table 34 summarize the set point control and DVS time stepping applied to all regulators.
1110 Reserved Reserved
1111 Reserved Reserved
Table 31. DVS Control Logic for SW1A/B/C
0 SW1x[5:0]
1 SW1xSTBY[5:0]
Table 32. DVS Control Logic for SW2, SW3A/B, and SW4
0 SWx[6:0]
1 SWxSTBY[6:0]
The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the over-current condition on the regulator should be masked. Figure 9. Voltage Stepping with DVS 4 is set to 270 ° by default at power up. Table 33. DVS Speed Selection for SW1A/B/C Table 34. DVS Speed Selection for SW2, SW3A/B, and SW4
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currents are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. the percentage of power stages that are enabled. Table 35. Regulator Phase Clock Selection Table 36. Optimum Phasing
1.0 MHz
2.0 MHz
4.0 MHz
Table 37. Regulator Frequency Configuration
11 Reserved
Table 38. Programmable Current Configuration
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7.4.4.3 SW1A/B/C
- SW1A/B/C single phase with one inductor
- SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor
- SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Extended Page 1, as shown in Table 39.
Table 39. SW1 Configuration
00 A/B/C Single Phase
01 A/B Single Phase
10 A/B Dual Phase
control registers, respectively. Figure 10 shows the connection for SW1A/B/C in single phase mode. registers should be used. The SW1FB pin should be left floating in this configuration. Figure 10. SW1A/B/C Single Phase Block Diagram
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off control. Figure 11 shows the physical connection for SW1A/B in single phase and SW1C as an independent output. Figure 11. SW1A/B Single Phase, SW1C Independent Mode Block Diagram while SW1CLX node operates independently, using the configuration in the SW1CCONF register.
off control. Figure 12 shows the physical connection for SW1A/B in dual phase and SW1C as an independent output. Figure 12. SW1A/B Dual Phase, SW1C Independent Mode Block Diagram configuration in the SW1CCONF register.
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SW1xOFF[5:0] bits respectively. Table 40 shows the output voltage coding for SW1A/B or SW1C. Table 40. SW1A/B/C Output Voltage Configuration
register is provided in Table 42 through Table 51. Table 41. SW1A/B/C Register Summary Table 42. Register SW1ABVOLT - ADDR 0x20 Table 43. Register SW1ABSTBY - ADDR 0x21 Table 44. Register SW1ABOFF - ADDR 0x22
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Table 45. Register SW1ABMODE - ADDR 0x23 SW1ABMODE 3:0 R/W 0x80 Sets the SW1AB switching operation mode. See Table 30 for all possible configurations. Table 46. Register SW1ABCONF - ADDR 0x24 SW1ABFREQ 3:2 R/W 0x00 SW1A/B switching frequency selector. SW1ABPHASE 5:4 R/W 0x00 SW1A/B Phase clock selection. SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection. Table 47. Register SW1CVOLT - ADDR 0x2E Table 48. Register SW1CSTBY - ADDR 0x2F Table 49. Register SW1COFF - ADDR 0x30
Table 50. Register SW1CMODE - ADDR 0x31 SW1CMODE 3:0 R/W 0x80 Sets the SW1C switching operation mode. See Table 29 for all possible configurations. Table 51. Register SW1CCONF - ADDR 0x32 SW1CFREQ 3:2 R/W 0x00 SW1C switching frequency selector. SW1CPHASE 5:4 R/W 0x00 SW1C Phase clock selection. SW1CDVSSPEED 7:6 R/W 0x00 SW1C DVS speed selection. Table 52. SW1A/B/C External Component Recommendations
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- Use X5R or X7R capacitors.
Table 53. SW1A/B/C Electrical Characteristics
- PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1ABC < 4.5 A 0.3 V ≤ VSW1ABC ≤ 1.450 V 1.475 V ≤ VSW1ABC ≤ 1.875 V
- PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1ABC < 150 mA 0.3 V < VSW1ABC < 0.85 V 0.875 V < VSW1ABC < 1.875 V VSW1ABCACC -25 -3.0% -65 -6.0% 3.0% 6.0% mV Rated Output Load Current, 2.8 V < VIN < 4.5 V, 0.3 V < VSW1ABC < 1.875 V ISW1ABC – – 4500 mA Current Limiter Peak Current Detection
- Current through Inductor SW1ABILIM = 0 SW1ABILIM = 1 ISW1ABCLIM 7.1 5.3 10.5 7.9 13.7 10.3 A Start-up Overshoot ISW1ABC = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V VSW1ABCOSH –– 6 6 m V Turn-on Time Enable to 90% of end value ISW1x = 0 mA DVS clk = 25 mV/4.0 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V tONSW1ABC – – 500 µs Switching Frequency SW1xFREQ[1:0] = 00 SW1xFREQ[1:0] = 01 SW1xFREQ[1:0] = 10 f SW1ABC 1.0 2.0 4.0 MHz
- V IN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 850 mA APS, PWM, 1.2 V, 1275 mA APS, PWM, 1.2 V, 2125 mA APS, PWM, 1.2 V, 4500 mA η SW1ABC Output Ripple ΔV SW1ABC –1 0– m V Line Regulation (APS, PWM) V SW1ABCLIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW1ABCLOR –– 2 0 m V Transient Load Regulation
- Transient load = 0 to 2.25 A, di/dt = 100 mA/ μs Overshoot Undershoot V SW1ABCLOTR – mV Quiescent Current PFM Mode APS Mode I SW1ABCQ – 145 µA Discharge Resistance R SW1ABCDIS – 600 – Ω SW1A/B (SINGLE/DUAL PHASE) Operating Input Voltage VINSW1A VINSW1B 2.8 – 4.5 V Nominal Output Voltage V SW1AB – Table 40 –V Output Voltage Accuracy
- PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 2.5 A 0.3 V ≤ VSW1AB ≤ 1.450 V 1.475 V ≤ VSW1AB ≤ 1.875 V
- PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 150 mA 0.3 V < VSW1AB < 0.85 V 0.875 V < VSW1AB < 1.875 V VSW1ABACC -25 -3.0% -65 -6.0% 3.0% 6.0% mV Rated Output Load Current, (34) 2.8 V < VIN < 4.5 V, 0.3 V < VSW1AB < 1.875 V ISW1AB – – 2500 mA Current Limiter Peak Current Detection (34)
- SW1A/B Single Phase (current through inductor) SW1ABILIM = 0 SW1ABILIM = 1
- SW1A/B Dual Phase (current through inductor per phase) SW1ABILIM = 0 SW1ABILIM = 1 I SW1ABLIM 4.5 3.3 2.2 1.6 6.5 4.9 3.2 2.4 8.5 6.4 4.3 3.2 A Start-up Overshoot ISW1AB = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V VSW1ABOSH –– 6 6 m V
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- V IN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 500 mA APS, PWM, 1.2 V, 750 mA APS, PWM, 1.2 V, 1250 mA APS, PWM, 1.2 V, 2500 mA η SW1AB Output Ripple ΔV SW1AB –1 0– m V Line Regulation (APS, PWM) V SW1ABLIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW1ABLOR –– 2 0 m V Transient Load Regulation
- Transient load = 0 to 1.25 A, di/dt = 100 mA/ μs Overshoot Undershoot VSW1ABLOTR – mV Quiescent Current PFM Mode APS Mode ISW1ABQ – 235 µA SW1A P-MOSFET RDSON VINSW1A = 3.3 V RONSW1AP – 215 245 m Ω SW1A N-MOSFET RDSON VINSW1A = 3.3 V RONSW1AN – 258 326 m Ω SW1A P-MOSFET Leakage Current VINSW1A = 4.5 V ISW1APQ –– 7 . 5 µ A SW1A N-MOSFET Leakage Current VINSW1A = 4.5 V ISW1ANQ –– 2 . 5 µ A SW1B P-MOSFET RDSON VINSW1B = 3.3 V RONSW1BP – 215 245 m Ω SW1B N-MOSFET RDSON VINSW1B = 3.3 V RONSW1BN – 258 326 m Ω SW1B P-MOSFET Leakage Current VINSW1B = 4.5 V ISW1BPQ –– 7 . 5 µ A SW1B N-MOSFET Leakage Current VINSW1B = 4.5 V ISW1BNQ –– 2 . 5 µ A Discharge Resistance R SW1ABDIS – 600 – Ω
- PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1C < 2.0 A 0.3 V ≤ VSW1C ≤ 1.450 V 1.475 V ≤ VSW1C ≤ 1.875 V
- PFM, steady state 2.8 V < V IN < 4.5 V, 0 < ISW1C < 50 mA 0.3 V < VSW1C < 0.85 V 0.875 V < VSW1C < 1.875 V VSW1CACC -25 -3.0% -65 -6.0% 3.0% 6.0% mV Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.3 V < VSW1C < 1.875 V ISW1C – – 2000 mA Current Limiter Peak Current Detection
- Current through Inductor SW1CILIM = 0 SW1CILIM = 1 I SW1CLIM 2.6(33) 1.95 4.0 3.0 5.2 3.9 A Start-up Overshoot ISW1C = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V VSW1COSH –– 6 6 m V Turn-on Time Enable to 90% of end value I SW1C = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V tONSW1C – – 500 µs Switching Frequency SW1CFREQ[1:0] = 00 SW1CFREQ[1:0] = 01 SW1CFREQ[1:0] = 10 fSW1C 1.0 2.0 4.0 MHz Efficiency
- V IN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 400 mA APS, PWM, 1.2 V, 600 mA APS, PWM, 1.2 V, 1000 mA APS, PWM, 1.2 V, 2000 mA η SW1C Output Ripple ΔV SW1C –1 0– m V Line Regulation (APS, PWM) V SW1CLIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW1CLOR –– 2 0 m V Transient Load Regulation
- Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ μs Overshoot Undershoot V SW1CLOTR – mV Quiescent Current PFM Mode APS Mode I SW1CQ – 145 µA
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- Meets 1.89 A current rating for VDDSOC_IN domain on i.MX6X processor.
- Current rating of SW1AB supports the Power Virus mode of operation of the i.MX6X processor.
Figure 13. SW1AB and SW1C Efficiency Waveforms
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7.4.4.4 SW2
Figure 14 shows the block diagram and the external component connections for SW2 regulator. Figure 14. SW2 Block Diagram range from 0.800 to 3.300 V with 50 mV increments, as determin ed by bits SW2[5:0]. h range, and the lower range be used for voltages from 0.400 to 1.975 V. output voltage coding valid for SW2. Table 54. SW2 Output Voltage Configuration
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is provided in Tables 56 to Table 60.
- For voltages less than 2.0 V, only use set points 0 to 63.
Table 55. SW2 Register Summary Table 56. Register SW2VOLT - ADDR 0x35 mode. See Table 54 for all possible configurations. for all possible configurations.
Table 57. Register SW2STBY - ADDR 0x36 SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during Standby mode. See Table 54 for all possible configurations. Table 54 for all possible configurations. Table 58. Register SW2OFF - ADDR 0x37 Table 54 for all possible configurations. for all possible configurations. Table 59. Register SW2MODE - ADDR 0x38 SW2MODE 3:0 R/W 0x80 Sets the SW2 switching operation mode. See Table 29 for all possible configurations. Table 60. Register SW2CONF - ADDR 0x39 SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. SW2PHASE 5:4 R/W 0x00 SW2 Phase clock selection. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection.
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Table 61. SW2 External Component Recommendations
- Use X5R or X7R capacitors.
Table 62. SW2 Electrical Characteristics
- PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW2 < 2.0 A 0.4 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V
- PFM, 2.8 V < V IN < 4.5 V, 0 < ISW2 ≤ 50 mA 0.4 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V VSW2ACC -25 -3.0% -6.0% -65 -6.0% -6.0% 3.0% 6.0% 6.0% 6.0% mV Rated Output Load Current (38) 2.8 V < VIN < 4.5 V, 0.4 V < VSW2 < 3.3 V ISW2 – – 2000 mA Current Limiter Peak Current Detection
- Current through Inductor SW2ILIM = 0 SW2ILIM = 1 ISW2LIM 2.8 2.1 4.0 3.0 5.2 3.9 A Start-up Overshoot ISW2 = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V VSW2OSH –– 6 6 m V Turn-on Time Enable to 90% of end value ISW2 = 0.0 mA DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V tONSW2 – – 550 µs Switching Frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 f SW2 1.0 2.0 4.0 MHz
- V IN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH PFM, 3.15 V, 1.0 mA PFM, 3.15 V, 50 mA APS, PWM, 3.15 V, 400 mA APS, PWM, 3.15 V, 600 mA APS, PWM, 3.15 V, 1000 mA APS, PWM, 3.15 V, 2000 mA η SW2 Output Ripple ΔV SW2 –1 0– m V Line Regulation (APS, PWM) V SW2LIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW2LOR –– 2 0 m V Transient Load Regulation
- Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ μs Overshoot Undershoot V SW2LOTR – mV Quiescent Current PFM Mode APS Mode (Low output voltage settings) APS Mode (High output voltage settings) I SW2Q 145 305 µA SW2 P-MOSFET RDSON at VIN = VINSW2 = 3.3 V RONSW2P – 190 209 m Ω SW2 N-MOSFET RDSON at VIN = VINSW2 = 3.3 V RONSW2N – 212 255 m Ω SW2 P-MOSFET Leakage Current VIN = VINSW2 = 4.5 V ISW2PQ –– 1 2 µ A SW2 N-MOSFET Leakage Current VIN = VINSW2 = 4.5 V ISW2NQ –– 4 . 0 µ A Discharge Resistance R SW2DIS – 600 – Ω Notes 37. When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V. 38. The higher output voltages available depend on the voltage dr op in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).
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Figure 15. SW2 Efficiency Waveforms
7.4.4.5 SW3A/B
modes and Table 30 show the actual configuration options for the SW3xMODE[3:0] bits.
- A single phase
- A dual phase
- Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 63 shows the options for the SW3CFG[1:0] bits.
Table 63. SW3 Configuration
00 A/B Single Phase
11 A/B Independent
open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set. Figure 16. SW3A/B Single Phase Block Diagram
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Figure 17. SW3A/B Dual Phase Block Diagram
registers as shown in Table 65. Figure 18. SW3A/B Independent Output Block Diagram voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by bits SW3x[5:0]. h range and that that the lower range be used for voltages from 0.400 to 1.975 V. SW3xSTBY[6] and SW3xOFF[6] bits. Therefore, the output voltage range will remain the same on all three operating modes. Table 64 shows the output voltage coding valid for SW3x.
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Table 64. SW3A/B Output Voltage Configuration
- For voltages less than 2.0 V, only use set points 0 to 63.
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provided on Tables 66 through Table 75. Table 65. SW3AB Register Summary Table 66. Register SW3AVOLT - ADDR 0x3C all possible configurations. (Independent) or SW3A/B (Single/Dual phase). for all possible configurations. Table 67. Register SW3ASTBY - ADDR 0x3D
Table 68. Register SW3AOFF - ADDR 0x3E on bit SW3A[6] during OTP or TBB configuration. for all possible configurations. Table 69. Register SW3AMODE - ADDR 0x3F (Single/Dual phase) switching operation mode. for all possible configurations. (Single/Dual phase) when in Sleep mode. Table 70. Register SW3ACONF - ADDR 0x40 SW3APHASE 5:4 R/W 0x00 SW3A Phase clock selection. See Table 35. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 34. Table 71. Register SW3BVOLT - ADDR 0x43 all possible configurations.
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Table 72. Register SW3BSTBY - ADDR 0x44 Table 73. Register SW3BOFF - ADDR 0x45 Table 74. Register SW3BMODE - ADDR 0x46 Table 75. Register SW3BCONF - ADDR 0x47 SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 37. SW3BPHASE 5:4 R/W 0x00 SW3B Phase clock selection. See Table 35. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 34.
Table 76. SW3A/B External Component Requirements
- Use X5R or X7R capacitors.
Table 77. SW3A/B Electrical Characteristics SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
- PWM, APS 2.8 V < V IN < 4.5 V, 0 < ISW3x < ISW3xMAX 0.4 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V
- PFM , steady state (2.8 V < V IN < 4.5 V, 0 < ISW3x < 50 mA) 0.4 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V VSW3xACC -25 -3.0% -6.0% -65 -6.0% -6.0% 3.0% 6.0% 6.0% 6.0% mV Rated Output Load Current (42)
- 2.8 V < V IN < 4.5 V, 0.4 V < VSW3x < 3.3 V PWM, APS mode single/dual phase PWM, APS mode independent (per phase) ISW3x – 2500 1250 mA
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- Single phase (Current through inductor) SW3xILIM = 0 SW3xILIM = 1
- Independent mode or Dual phase (Current through inductor per phase) SW3xILIM = 0 SW3xILIM = 1 I SW3xLIM 3.5 2.7 1.8 1.3 5.0 3.8 2.5 1.9 6.5 4.9 3.3 2.5 A Start-up Overshoot ISW3x = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V VSW3xOSH –– 6 6 m V Turn-on Time Enable to 90% of end value ISW3x = 0 mA DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V tONSW3x – – 500 µs Switching Frequency SW3xFREQ[1:0] = 00 SW3xFREQ[1:0] = 01 SW3xFREQ[1:0] = 10 f SW3x 1.0 2.0 4.0 MHz Efficiency (Single Phase)
- f SW3 = 2.0 MHz, LSW3x 1.0 μH PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA η SW3AB Output Ripple ΔV SW3x –1 0– m V Line Regulation (APS, PWM) V SW3xLIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW3xLOR –– 2 0 m V Transient Load Regulation
- Transient Load = 0.0 mA to I SW3x/2, di/dt = 100 mA/μs Overshoot Undershoot VSW3xLOTR – mV Quiescent Current PFM Mode (Single/Dual Phase) APS Mode (Single/Dual Phase) PFM Mode (Independent mode) APS Mode (SW3A Independent mode) APS Mode (SW3B Independent mode) I SW3xQ 300 250 150 µA SW3A P-MOSFET R DSON at VIN = VINSW3A = 3.3 V RONSW3AP – 215 245 mΩ SW3A N-MOSFET RDSON at VIN = VINSW3A = 3.3 V RONSW3AN – 258 326 mΩ SW3A P-MOSFET Leakage Current VIN = VINSW3A = 4.5 V ISW3APQ –– 7 . 5 µ A
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Figure 19. SW3AB Single Phase Efficiency Waveforms
7.4.4.6 SW4
modes: PFM, APS, and PWM, described on Table 29 and configured by the SW4MODE[3:0] bits, as shown in Table 30. VTT mode can be configured by use of VTT bit in the OTP_SW4_CONFIG register. Figure 20 shows the block diagram and the external component connections for the SW4 regulator.
- When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V.
- The higher output voltages available depend on the voltage dr op in the conduction path as given by the following equation:
(VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance). SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
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Figure 20. SW4 Block Diagram One Time Programmability (OTP) for detailed information on OTP configuration. limited to the higher output voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits. h range and that that the lower range be used for voltages from 0.400 to 1.975 V. shows the output voltage coding valid for SW4. Table 78. SW4 Output Voltage Configuration
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registers is provided in Tables 80 to Table 84.
- For voltages less than 2.0 V, only use set points 0 to 63.
Table 79. SW4 Register Summary Table 80. Register SW4VOLT - ADDR 0x4A Sets the operating output voltage range for SW4. Table 78 for all possible configurations.
Table 81. Register SW4STBY - ADDR 0x4B Table 82. Register SW4OFF - ADDR 0x4C SW4OFF 5:0 R/W 0x00 Sets the SW4 output voltage during Sleep mode. See Table 78 for all possible configurations. Table 83. Register SW4MODE - ADDR 0x4D SW4MODE 3:0 R/W 0x80 Sets the SW4 switching operation mode. See Table 29 for all possible configurations. Table 84. Register SW4CONF - ADDR 0x4E SW4PHASE 5:4 R/W 0x00 SW4 Phas e clock selection. See Table 35. SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 34.
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Table 85. SW4 External Component Requirements
- Use X5R or X7R capacitors.
Table 86. SW4 Electrical Characteristics SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
- PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW4 < 1.0 A 0.4 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V 2.0 V < VSW4 < 3.3 V
- PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW4 < 50 mA 0.4 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V 2.0 V < VSW4 < 3.3 V
- VTT Mode , 2.8 V < V IN < 4.5 V, 0 < ISW4 < 1.0 A VSW4ACC -25 -3.0% -6.0% -65 -6.0% -6.0% -40 3.0% 6.0% 6.0% 6.0% mV Rated Output Load Current (46) 2.8 V < VIN < 4.5 V, 0.4 V < VSW4 < 3.3 V ISW4 – – 1000 mA Current Limiter Peak Current Detection Current through inductor SW4ILIM = 0 SW4ILIM = 1 ISW4LIM 1.4 1.0 2.0 1.5 3.0 2.4 A Start-up Overshoot ISW4 = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V VSW4OSH –– 6 6 m V Turn-on Time Enable to 90% of end value ISW4 = 0.0 mA DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V tONSW4 – – 500 µs
- f SW4 = 2.0 MHz, LSW4 = 1.0 μH PFM, 1.8 V, 1.0 mA PFM, 1.8 V, 50 mA APS, PWM 1.8 V, 200 mA APS, PWM 1.8 V, 500 mA APS, PWM 1.8 V, 1000 mA PWM 0.75 V, 200 mA PWM 0.75 V, 500 mA PWM 0.75 V, 1000 mA η SW4 Output Ripple ΔV SW4 –1 0– m V Line Regulation (APS, PWM) V SW4LIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW4LOR –– 2 0 m V Transient Load Regulation
- Transient Load = 0.0 mA to 500 mA, di/dt = 100 mA/ μs Overshoot Undershoot V SW4LOTR – – 50 mV Quiescent Current PFM Mode APS Mode I SW4Q – 145 µA SW4 P-MOSFET RDSON at VIN = VINSW4 = 3.3 V RONSW4P – 236 274 m Ω SW4 N-MOSFET RDSON at VIN = VINSW4 = 3.3 V RONSW4N – 293 378 m Ω SW4 P-MOSFET Leakage Current VIN = VINSW4 = 4.5 V ISW4PQ –– 6 . 0 µ A SW4 N-MOSFET Leakage Current VIN = VINSW4 = 4.5 V ISW4NQ –– 2 . 0 µ A Discharge Resistance R SW4DIS – 600 – Ω Notes 45. When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V. 46. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW4 - VSW4) = ISW4* (DCR of Inductor +RONSW4P + PCB trace resistance).
SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
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Figure 21. SW4 Efficiency Waveforms
7.4.5 Boost Regulator
NMOS transistor is integrated on-chip. Figure 22 shows the block diagram and component connection for the boost regulator. Figure 22. Boost Regulator Architecture
7.4.5.1 SWBST Setup and Control
sequence if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros. Table 87. Register SWBSTCTL - ADDR 0x66
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7.4.5.2 SWBST External Components
7.4.5.3 SWBST Specifications
- In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current.
Table 88. SWBST External Component Requirements
- Use X5R or X7R capacitors.
Table 89. SWBST Electrical Specifications VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
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7.4.6 LDO Regulators Description
Bias and References Block Description section for further information on the internal reference voltages. of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. Figure 23. General LDO Block Diagram
7.4.6.1 Transient Response Waveforms
transient line and load response refers to the overshoot, or undershoot only, excluding the DC shift. Figure 24. Transient Waveforms
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7.4.6.2 Short-circuit Protection
maskable through the VGENxFAULTM mask bit. for SCP behavior configuration.
7.4.6.3 LDO Regulator Control
voltage according to Table 91 for VGEN1 and VGEN2; and uses the voltage set point on Table 92 for VGEN3 through VGEN6. Table 90. Short-circuit Behavior
0 Current limit
1 Shutdown
Table 91. VGEN1, VGEN2 Output Voltage Configuration
Table 92. VGEN3/ 4/ 5/ 6 Output Voltage Configuration Table 93. LDO Control
- STANDBY refers to a Standby event as described earlier.
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Table 94. Register VGEN1CTL - ADDR 0x6C VGEN1 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 91 for all possible configurations. Table 95. Register VGEN2CTL - ADDR 0x6D VGEN2 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 91 for all possible configurations. Table 96. Register VGEN3CTL - ADDR 0x6E VGEN3 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 92 for all possible configurations.
Table 97. Register VGEN4CTL - ADDR 0x6F VGEN4 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 92 for all possible configurations. Table 98. Register VGEN5CTL - ADDR 0x70 VGEN5 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 92 for all possible configurations. Table 99. Register VGEN6CTL - ADDR 0x71 VGEN6 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 92 for all possible configurations.
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7.4.6.4 External Components
Table 100 lists the typical component values for the general purpose LDO regulators.
7.4.6.5 LDO Specifications
Table 100. LDO External Components
- Use X5R/X7R ceramic capacitors.
Table 101. VGEN1 Electrical Characteristics IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN1 = 75 mA, 20 Hz to 20 kHz VGEN1[3:0] = 0000 - 1101 VGEN1[3:0] = 1110, 1111 PSRRVGEN1 50 dB Output Noise Density VIN1 = 1.75 V, IGEN1 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISE VGEN1 – -108 -118 -124 -100 -108 -112 dBV/ √Hz Turn-on Slew Rate
- 10% to 90% of end value
- 1 . 7 5 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA VGEN1[3:0] = 0000 to 0111 VGEN1[3:0] = 1000 to 1111 SLWRVGEN1 12.5 16.5 mV/μs Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN1 = 0.0 mA GEN1tON 60 – 500 μs Turn-Off Time Disable to 10% of initial value, VIN1 = 1.75 V IGEN1 = 0.0 mA GEN1tOFF –– 1 0 m s Start-Up Overshoot Transient Load Response
- V IN1 = 1.75 V, 3.4 V IGEN1 = 10 to 100 mA in 1.0 μs. Peak of overshoot or undershoot of VGEN1 with respect to final value
- Refer to Figure 24 VGEN1LOTR –– 3 . 0 % Transient Line Response
- I GEN1 = 75 mA VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN1[3:0] = 0000 to 1101 VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for VGEN1[3:0] = 1110, 1111
- Refer to Figure 24 VGEN1LITR –5 . 0 8 . 0 m V Notes 52. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test.
IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
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Table 102. VGEN2 Electrical Characteristics IGEN2 = 10mA and 25°C, unless otherwise noted.
- I GEN2 = 187.5 mA, 20 Hz to 20 kHz VGEN2[3:0] = 0000 - 1101 VGEN2[3:0] = 1110, 1111 PSRRVGEN2 50 dB Output Noise Density
- V IN1 = 1.75 V, IGEN2 = 187.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN2 – -108 -118 -124 -100 -108 -112 dBV/ √Hz Turn-On Slew Rate
- 10% to 90% of end value
- 1 . 7 5 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA VGEN2[3:0] = 0000 to 0111 VGEN2[3:0] = 1000 to 1111 SLWRVGEN2 12.5 16.5 mV/μs Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN2 = 0.0 mA GEN2tON 60 – 500 μs
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
operate in the dropout region of the regulator under test. IGEN2 = 10mA and 25°C, unless otherwise noted.
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Table 103. VGEN3 Electrical Characteristics IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN3 = 75 mA, 20 Hz to 20 kHz VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V PSRRVGEN3 35 dB Output Noise Density
- V IN2 = VIN2MIN, IGEN3 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN3 – -114 -129 -135 -102 -123 -130 dBV/ √Hz Turn-On Slew Rate
- 10% to 90% of end value
- V I N 2MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA VGEN3[3:0] = 0000 to 0011 VGEN3[3:0] = 0100 to 0111 VGEN3[3:0] = 1000 to 1011 VGEN3[3:0] = 1100 to 1111 SLWR VGEN3 – 22.0 26.5 30.5 34.5 mV/μs
- When the LDO Output voltage is set above 2.6 V, the minimum al lowed input voltage needs to be at least the output voltage plus 0.25 V,
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
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Table 104. VGEN4 Electrical Characteristics IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN4 = 262.5 mA, 20 Hz to 20 kHz VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V PSRRVGEN4 35 dB Output Noise Density
- V IN2 = VIN2MIN, IGEN4 = 262.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN4 – -114 -129 -135 -102 -123 -130 dBV/ √Hz Turn-On Slew Rate
- 10% to 90% of end value
- V I N 2MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA VGEN4[3:0] = 0000 to 0011 VGEN4[3:0] = 0100 to 0111 VGEN4[3:0] = 1000 to 1011 VGEN4[3:0] = 1100 to 1111 SLWR VGEN4 – 22.0 26.5 30.5 34.5 mV/μs
- When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
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Table 105. VGEN5 Electrical Characteristics IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN5 = 75 mA, 20 Hz to 20 kHz VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V PSRRVGEN5 35 dB Output Noise Density
- V IN3 = VIN3MIN, IGEN5 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN5 – -114 -129 -135 -102 -123 -130 dBV/ √Hz Turn-On Slew Rate
- 10% to 90% of end value
- V I N 3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA VGEN5[3:0] = 0000 to 0011 VGEN5[3:0] = 0100 to 0111 VGEN5[3:0] = 1000 to 1011 VGEN5[3:0] = 1100 to 1111 SLWR VGEN5 – 22.0 26.5 30.5 34.5 mV/μs
- When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
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Table 106. VGEN6 Electrical Characteristics IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN6 = 150 mA, 20 Hz to 20 kHz VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V PSRRVGEN6 35 dB Output Noise Density
- V IN3 = VIN3MIN, IGEN6 = 150 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN6 – -114 -129 -135 -102 -123 -130 dBV/ √Hz Turn-On Slew Rate
- 10% to 90% of end value
- V I N 3 MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA VGEN6[3:0] = 0000 to 0011 VGEN6[3:0] = 0100 to 0111 VGEN6[3:0] = 1000 to 1011 VGEN6[3:0] = 1100 to 1111 SLWR VGEN6 – 22.0 26.5 30.5 34.5 mV/μs Turn-On Time Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V IGEN6 = 0.0 mA GEN6tON 60 – 500 μs
7.4.7 VSNVS LDO/Switch
voltage minus the voltage drop across the switch, which is 40 mV at a rated maximum load current of 400 μA. voltages as when VIN is applied, providing certain conditions are met as described in Table 107.
- When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
2.25 V (VTL0) -
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Figure 25. VSNVS Supply Switch Architecture The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 108. Table 107. VSNVS Modes of Operation Table 108. Register VSNVSCTL - ADDR 0x6B
- Only valid when a valid input voltage is present.
Table 109. VSNVS External Components
Table 110. VSNVS Electrical Characteristics
- 5 . 0 μA < ISNVS < 400 μA (OFF) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
- 5 . 0 μA < ISNVS < 400 μA (ON) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
- 5 .0 μA < ISNVS < 400 μA (Coin Cell mode) 2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110 1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - 101 VSNVS -5.0% -8.0% -5.0% -4.0% VCOIN-0.04 -8.0% 3.0 1.0 - 1.8 3.0 1.0 - 1.8 1.0 - 1.8 7.0% 7.0% 5.0% 4.0% VCOIN 7.0% V Dropout Voltage 2.85 V < VIN < 2.9 V, VSNVSVOLT[2:0] = 110 5.0 μA < ISNVS < 400 μA VSNVSDROP –– 5 0 m V Current Limit VIN > VTH1, VSNVSVOLT[2:0] = 110 VIN > VTL0, VSNVSVOLT[2:0] = 000 to 101 VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 ISNVSLIM 750 500 480 5900 5900 3600 μA VIN Threshold (Coin Cell Powered to VIN Powered) VIN going high with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 V TH0 2.25 2.40 2.50 V VIN Threshold (VIN Powered to Coin Cell Powered) VIN going low with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 V TL0 2.20 2.35 2.45 V VIN Threshold Hysteresis for VTH1-VTL1 VHYST1 5.0 – – mV VIN Threshold Hysteresis for VTH0-VTL0 VHYST0 5.0 – – mV Output Voltage During Crossover VSNVSVOLT[2:0] = 110 V COIN > 2.9 V Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA VSNVSCROSS 2.80 – – V
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- Current required by i.MX6X SNVS domain may change.
- The start-up of VSNVS is not monotonic. It first rises to 1. 0 V and then settles to its programmed value within the specified tr1 time.
- For 1.8 V I SNVS limited to 100 μA for VCOIN < 2.1 V
7.4.7.1 Coin Cell Battery Backup
applied to LICELL. A small capacitor should be placed from LICELL to ground under all circumstances. programmable through the VCOIN[2:0] bits on register COINCTL on Table 112. The coin cell charger voltage is programmable. unnecessarily. The coin cell charging will be stopped when VIN is below UVDET. Table 111. Coin Cell Charger Voltage
- Coin cell voltages selected based on the
type of LICELL used on the system. Table 112. Register COINCTL - ADDR 0x1A Coin cell charger output voltage selection. Table 113. Coin Cell Charger External Components
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7.5 Control Interface I 2C Block Description
registers the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.
7.5.1 I2C Device ID
new slave address; these bits take affect right away.
7.5.2 I 2C Operation
each byte will be sent out unless a STOP command or NACK is received prior to completion. The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. Figure 26. I2C Write Example Table 114. Coin Cell Charger Specifications
Figure 27. I2C Read Example
7.5.3 Interrupt Handling
occurs while the processor clears an existing interrupt bit, the INTB pin will remain low. bit was already high, the INTB pin will go low after unmasking. The sense registers contain status and input sense bits so the system p rocessor can poll the current state of interrupt sources. They are read only, and not latched or clearable. to the asynchronous nature of the debounce timer, th e effective debounce time can vary slightly.
7.5.4 Interrupt Bit Summary
descriptions, refer to the related chapters. Table 115. Interrupt, Mask and Sense Bits
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A full description of all interrupt, mask, and sense registers is provided in Tables 116 to 127.
- Debounce timing for the falling edge c an be extended with PWRONDBNC[1:0].
Table 116. Register INTSTAT0 - ADDR 0x05
Table 117. Register INTMASK0 - ADDR 0x06 Table 118. Register INTSENSE0 - ADDR 0x07 Table 119. Register INTSTAT1 - ADDR 0x08
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Table 120. Register INTMASK1 - ADDR 0x09 Table 121. Register INTSENSE1 - ADDR 0x0A Table 122. Register INTSTAT3 - ADDR 0x0E
Table 123. Register INTMASK3 - ADDR 0x0F Table 124. Register INTSENSE3 - ADDR 0x10 Table 125. Register INTSTAT4 - ADDR 0x11 Table 126. Register INTMASK4 - ADDR 0x12
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7.5.5 Specific Registers
7.5.5.1 IC and Version Identification
Table 127. Register INTSENSE4 - ADDR 0x13 Table 128. Register DEVICEID - ADDR 0x00 DEVICEID 3:0 R 0x00 Die version. Table 129. Register SILICON REV- ADDR 0x03
7.5.5.2 Embedded Memory
for bit retention with coin cell backup. Table 130. Register FABID - ADDR 0x04 Table 131. Register MEMA ADDR 0x1C Table 132. Register MEMB ADDR 0x1D Table 133. Register MEMC ADDR 0x1E Table 134. Register MEMD ADDR 0x1F
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7.5.6 Register Bitmap
write to the page register is necessary.
- R is read-only access
- R/W is read and write access
- RW1C is read and write access with write 1 to clear Reset: Reset signals are color coded based on the following legend. Default: The value after reset, as noted in the Default column of the memory map.
- Fixed defaults are explicitly declared as 0 or 1.
- “X” corresponds to Read / Write bits that are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits that may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts.
7.5.6.1 Register map
Table 135. Functional Page
00 DeviceID R 8'b0001_0000
03 SILICONREVID R 8'b0001_0000
04 FABID R 8'b0000_0000
05 INTSTAT0 RW1C 8'b0000_0000
06 INTMASK0 R/W 8'b0011_1111
07 INTSENSE0 R 8'b00xx_xxxx
08 INTSTAT1 RW1C 8'b0000_0000
09 INTMASK1 R/W 8'b0111_1111
10 INTSENSE3 R 8'b0000_000x
11 INTSTAT4 RW1C 8'b0000_0000
12 INTMASK4 R/W 8'b0011_1111
13 INTSENSE4 R 8'b00xx_xxxx
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20 SW1ABVOLT R/W/M 8'b00xx_xxxx
21 SW1ABSTBY R/W 8'b00xx_xxxx
22 SW1ABOFF R/W 8'b00xx_xxxx
23 SW1ABMODE R/W 8'b0000_1000
24 SW1ABCONF R/W 8'bxx00_xx00
30 SW1COFF R/W 8'b00xx_xxxx
31 SW1CMODE R/W 8'b0000_1000
32 SW1CCONF R/W 8'bxx00_xx00
35 SW2VOLT R/W 8'b0xxx_xxxx
36 SW2STBY R/W 8'b0xxx_xxxx
37 SW2OFF R/W 8'b0xxx_xxxx
38 SW2MODE R/W 8'b0000_1000
39 SW2CONF R/W 8'bxx01_xx00
40 SW3ACONF R/W 8'bxx10_xx00
43 SW3BVOLT R/W 8'b0xxx_xxxx
44 SW3BSTBY R/W 8'b0xxx_xxxx
45 SW3BOFF R/W 8'b0xxx_xxxx
46 SW3BMODE R/W 8'b0000_1000
47 SW3BCONF R/W 8'bxx10_xx00
66 SWBSTCTL R/W 8'b0xx0_10xx
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70 VGEN5CTL R/W 8'b000x_xxxx
71 VGEN6CTL R/W 8'b000x_xxxx
Table 136. Extended Page 1
80 OTP FUSE READ
84 OTP LOAD MASK R/W 8'b0000_0000
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120 Freescale Semiconductor
Table 137. Extended Page 2
81 SW1AB PWRSTG R/W 8'b1111_1111
82 PWRSTG RSVD R 8'b0000_0000
83 SW1C PWRSTG R 8'b1111_1111
84 SW2 PWRSTG R 8'b1111_1111
85 SW3A PWRSTG R 8'b1111_1111
86 SW3B PWRSTG R 8'b1111_1111
87 SW4 PWRSTG R 8'b0111_1111
88 PWRCTRL OTP
90 IO DRV R/W 8'b00xx_xxxx
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8 Typical Applications
8.1 Introduction
component references and additional components such as filters, refer to the individual sections.
8.1.1 Application Diagram
Figure 28. Typical Application Schematic
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8.1.2 Bill of Material
The following table provides a complete list of the recommended components on a full featured system using the PF0100 Device. Table 138. Bill of Material (68)
1 Power management IC MMPF0100 Freescale
1.0 A 1 20 V SOD-123FL MBR120VLSFT1G ON Semiconductor Schottky Diode
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8.2 PF0100 Layout Guidelines
8.2.1 General Board Recommendations
- It is recommended to use an eight layer board stack-up arranged as follows:
- High current signal
- G N D
- S i g n a l
- Power
- Power
- S i g n a l
- G N D
- High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUT ING (high current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.
8.2.2 Component Placement
- Freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circuit drawings
8.2.3 General Routing Requirements
- Some recommended things to keep in mind for manufacturability:
- Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
- Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
- Minimum allowed spacing between line and hole pad is 3.5 mils
- Minimum allowed spacing between line and line is 3.0 mils 2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be also shielded. 3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. Avoid coupling traces between important signal/low no ise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node (i.e. SW1ALX, SW2LX, SW3LX, SW4ALX, SW4BLX, and SWBSTLX). 5. Make sure that all components related to a specif i c block are referenced to the corresponding ground.
8.2.4 Parallel Routing Requirements
- CLK is the fastest signal of the system, so it must be given special care.
- To avoid contamination of these delicate signals by near by hi gh power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.
Figure 29. Recommended Shielding for Critical Signals.
- These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground pla ne.
- Care must be taken with these signals not to contamin a te analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
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8.2.5 Switching Regulator Layout Recommendations
- Per design, the switching regulators in PF 0100 are designed to operate with only one input bulk capacitor. However, it is
capacitor should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
- Make high-current ripple traces low-inductance (short, high W/L ratio).
- Make high-current traces wide or copper islands.
- Make high-current traces symetrical fo r dual–phase regulators (SW1, SW3).
Figure 30. Generic Buck Regulator Architecture Figure 31. Recommended Layout for Buck Regulators
Analog Integrated Circuit Device Data Freescale Semiconductor 129 PF0100 Typical Applications Thermal Information
8.3 Thermal Information
8.3.1 Rating Data
The thermal rating data of the packages has been simulated with the results listed in Table 5. Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta- JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.
8.3.2 Estimation of Junction Temperature
An estimation of the chip junction temperature TJ can be obtained from the equation: TJ = TA + (RθJA x PD) with: TA = Ambient temperature for the package in °C RθJA = Junction to ambient thermal resistance in °C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RθJB x PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See Functional Block Requirements and Behaviors for more details on thermal management.
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9 Packaging
9.1 Packaging Dimensions
for specific thermal characteristics for each package. Table 139. Package Drawing Information
Analog Integrated Circuit Device Data Freescale Semiconductor 131 PF0100 Packaging Packaging Dimensions
Analog Integrated Circuit Device Data
132 Freescale Semiconductor
Analog Integrated Circuit Device Data Freescale Semiconductor 133 PF0100 Packaging Packaging Dimensions
134 Freescale Semiconductor
10 Reference Section
10.1 Reference Documents
Table 140. PF0100 Reference Documents
Analog Integrated Circuit Device Data Freescale Semiconductor 135 PF0100
Revision History
11.1 Document Changes
REVISION DATE DESCRIPTION OF CHANGES 1.0 7/2011 • Preliminary specif ication release 2.0 8/2012 • NPI phase: prototype major updates throughout cycle 3.0 10/2012 • Initial production release
Document Number: MMPF0100 Rev. 3.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/Policy.aspx?Selector=RT&s=STR0326182960&pc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C- Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.