MMFT5P03HD ONSEMI | Alldatasheet

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Publication Order Number: MMFT5P03HD/D  Semiconductor Components Industries, LLC, 2000 November, 2000 – Rev. 3 MMFT5P03HD Preferred Device Power MOSFET

5 Amps, 30 Volts

P–Channel SOT–223 This miniature surface mount MOSFET features ultra low RDS(on) and true logic level performance. It is capable of withstanding high energy in the avalanche and commutation modes and the drain–to–source diode has a very low reverse recovery time. MMFT5P03HD devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc–dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.

  • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
  • Logic Level Gate Drive – Can Be Driven by Logic ICs
  • Miniature SOT–223 Surface Mount Package – Saves Board Space
  • Diode Is Characterized for Use In Bridge Circuits
  • Diode Exhibits High Speed, With Soft Recovery
  • IDSS Specified at Elevated Temperature
  • Avalanche Energy Specified Device Package Shipping

ORDERING INFORMATION

MMFT5P03HDT3 SOT–223 4000 Tape & Reel

5 AMPERES

30 VOLTS

R DS(on) = 100 mΩ D S G P–Channel TO–261AA CASE 318E STYLE 3 http://onsemi.com LWW MARKING DIAGRAM 5P03H L = Location Code WW = Work Week PIN ASSIGNMENT Preferred devices are recommended choices for future use and best overall value. 321 Gate Drain Source Drain

http://onsemi.com MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Negative sign for P–Channel devices omitted for clarity Rating Symbol Max Unit Drain–to–Source Voltage VDSS 30 V Drain–to–Gate Voltage (RGS = 1.0 MΩ ) VDGR 30 V Gate–to–Source Voltage – Continuous VGS ± 20 V 1″ SQ. FR–4 or G–10 PCB 10 seconds Thermal Resistance – Junction to Ambient Total Power Dissipation @ TA = 25°C Linear Derating Factor Drain Current – Continuous @ TA = 25°C Continuous @ TA = 70°C Pulsed Drain Current (Note 1.) R THJA PD ID ID IDM 3.13 5.2 4.1 °C/W Watts mW/ °C A A A Minimum FR–4 or G–10 PCB 10 seconds Thermal Resistance – Junction to Ambient Total Power Dissipation @ TA = 25°C Linear Derating Factor Drain Current – Continuous @ TA = 25°C Continuous @ TA = 70°C Pulsed Drain Current (Note 1.) R THJA PD ID ID IDM 1.56 12.5 3.7 2.9 °C/W Watts mW/ °C A A A Operating and Storage Temperature Range TJ, Tstg – 55 to 150 Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.5 mH, RG = 25 ) EAS 250 mJ 1. Repetitive rating; pulse width limited by maximum junction temperature.

http://onsemi.com ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (Notes 2. & 4.) (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 1.0 µAdc Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 100 nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (Cpk ≥ 2.0) (Notes 2. & 4.) (VDS = VGS , ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) 1.0 1.75 3.5 3.0 Vdc mV/°C Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (Notes 2. & 4.) (VGS = 10 Vdc, ID = 5.2 Adc) (VGS = 4.5 Vdc, ID = 2.6 Adc) R DS(on) 119 100 150 m Ω Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) (Note 2.) gFS 2.0 4.0 – Mhos DYNAMIC CHARACTERISTICS Input Capacitance (V 25 Vd V 0 Vd C iss – 475 950 pF Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C oss – 220 440 Transfer Capacitance f = 1.0 MHz) C rss – 70 140 SWITCHING CHARACTERISTICS (Note 3.) Turn–On Delay Time td(on) – 12 24 ns Rise Time (VDD = 15 Vdc, ID = 4.0 Adc, VGS =1 0V d c tr – 24 48 Turn–Off Delay Time VGS = 10 Vdc, R G = 6.0 Ω ) (Note 2.) td(off) – 47 94 Fall Time R G 6.0 Ω ) (Note 2.) tf – 46 92 Turn–On Delay Time td(on) – 19 38 Rise Time (VDD = 15 Vdc, ID = 2.0 Adc, VGS =45V d c tr – 55 110 Turn–Off Delay Time VGS = 4.5 Vdc, R G = 6.0 Ω ) (Note 2.) td(off) – 30 60 Fall Time R G 6.0 Ω ) (Note 2.) tf – 40 80 Gate Charge Q T – 17 24 nC (VDS = 24 Vdc, ID = 4.0 Adc, Q 1 – 1.7 –(VDS 24 Vdc, ID 4.0 Adc, VGS = 10 Vdc) (Note 2.) Q 2 – 6.3 – Q 3 – 4.6 – SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc) (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 1.1 0.89 1.5 Vdc Reverse Recovery Time trr – 39 – ns (IS = 4.0 Adc, VGS = 0 Vdc, ta – 20 –(IS 4.0 Adc, VGS 0 Vdc, dIS/dt = 100 A/µs) (Note 2.) tb – 19 – Reverse Recovery Stored Charge Q RR – 0.042 – µC 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. C pk = Max limit – Typ 3 x SIGMA

be charged by current from the generator. and Q2 and VGSP are read from the gate charge curve. on–state when calculating td(off). is difficult to measure and, consequently, is not specified. maintain a value of unity regardless of the switching speed. however, snubbing reduces switching losses. Figure 7. Capacitance Variation

http://onsemi.com INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.079 2.0 0.15 3.8 0.248 6.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 0.091 2.3 0.091 2.3 mm inches SOT–223 POWER DISSIPATION The power dissipation of the SOT–223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–223 package, PD can be calculated as follows: PD = TJ(max) – TA R θJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 3.13 watts. PD = 150°C – 25°C 40°C/W = 3.13 watts The 40°C/W for the SOT–223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.13 watts. There are other alternatives to achieving higher power dissipation from the SOT–223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

efficiently, then distributes this energy to the components. be up to 30 degrees cooler than the adjacent solder joints.

40 TO 80 SECONDS

Figure 16. Typical Solder Heating Profile

http://onsemi.com PACKAGE DIMENSIONS STYLE 3: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN H S F A B D G L 12 3 0.08 (0003) C M K J DIM A MIN MAX MIN MAX MILLIMETERS 0.249 0.263 6.30 6.70 INCHES B 0.130 0.145 3.30 3.70 C 0.060 0.068 1.50 1.75 D 0.024 0.035 0.60 0.89 F 0.115 0.126 2.90 3.20 G 0.087 0.094 2.20 2.40 H 0.0008 0.0040 0.020 0.100 J 0.009 0.014 0.24 0.35 K 0.060 0.078 1.50 2.00 L 0.033 0.041 0.85 1.05 M 0 10 0 10 S 0.264 0.287 6.70 7.30 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SOT–223 (TO–261) CASE 318E–04 ISSUE K

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