MMFT3055VL ONSEMI | Alldatasheet
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Publication Order Number: MMFT3055VL/D © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 3 MMFT3055VL Power MOSFET
1 Amp, 60 Volts
N−Channel SOT−223 These Power MOSFETs are designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
- Avalanche Energy Specified
- IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−repetitive (tp ≤ 10 ms) VGS VGSM ± 15 ± 20 Vdc Vpk Drain Current − Continuous Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 μs) ID ID IDM 1.5 1.2 5.0 Adc Apk Total PD @ TA = 25°C mounted on 1″ sq. Drain pad on FR−4 bd material Total PD @ TA = 25°C mounted on 0.70″ sq. Drain pad on FR−4 bd material Total PD @ TA = 25°C mounted on min. Drain pad on FR−4 bd material Derate above 25°C PD 2.1 1.7 0.94 6.3 Watts mW/°C Operating and Storage Temperature Range TJ, Tstg −55 to 175 Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 Ω ) EAS mJ Thermal Resistance − Junction to Ambient on 1″ sq. Drain pad on FR−4 bd material − Junction to Ambient on 0.70″ sq. Drain pad on FR−4 bd material − Junction to Ambient on min. Drain pad on FR−4 bd material RθJA RθJA RθJA 159 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
1 AMPERE
60 VOLTS
RDS(on) = 140 m/C0087 D G S N−Channel Device Package Shipping
ORDERING INFORMATION
MMFT3055VLT1 SOT −223 1000 Tape & Reel TO−261AA CASE 318E STYLE 3 http://onsemi.com LWW MARKING DIAGRAM TBD L = Location Code WW = Work Week PIN ASSIGNMENT 321 Gate Drain Source Drain MMFT3055VLT3 SOT −223 4000 Tape & Reel
http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Cpk ≥ 2.0) (Note 3) (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS 100 μAdc Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS − − 100 nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (Cpk ≥ 2.0) (Note 3) (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) VGS(th) 1.0 1.5 3.7 2.0 Vdc mV/°C Static Drain−to−Source On−Resistance (Cpk ≥ 2.0) (Note 3) (VGS = 5.0 Vdc, ID = 0.75 Adc) RDS(on) − 0.125 0.14 Ohm Drain−to−Source On−Voltage (VGS = 5.0 Vdc, ID = 1.5 Adc) (VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150°C) VDS(on) 0.25 0.24 Vdc Forward Transconductance (VDS = 8.0 Vdc, ID = 1.5 Adc) gFS 1.0 3.5 − mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 350 490 pF Output Capacitance Coss − 110 150 Transfer Capacitance Crss − 29 60 SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time (VDD = 30 Vdc, ID = 1.5 Adc, VGS = 5.0 Vdc, RG = 9.1 Ω) td(on) − 9.5 20 ns Rise Time tr − 18 40 Turn−Off Delay Time td(off) − 35 70 Fall Time tf − 22 40 Gate Charge (VDS = 48 Vdc, ID = 1.5 Adc, VGS = 5.0 Vdc) QT − 9.0 10 nC Q1 − 1.0 − Q2 − 4.0 − Q3 − 3.5 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 1) (IS = 1.5 Adc, VGS = 0 Vdc) (IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150°C) VSD 0.82 0.68 1.2 Vdc Reverse Recovery Time (IS = 1.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) trr − 41 − ns ta − 29 − tb − 12 − Reverse Recovery Stored Charge QRR − 0.066 − μC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD − 4.5 − nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS − 7.5 − nH 1. Pulse Test: Pulse Width ≤300 μs, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk = Max limit − Typ 3 x SIGMA
be charged by current from the generator. and Q2 and VGSP are read from the gate charge curve. on−state when calculating td(off). is difficult to measure and, consequently, is not specified. maintain a value of unity regardless of the switching speed. however, snubbing reduces switching losses. Figure 7. Capacitance Variation
5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage versus Current junction temperature and a case temperature (TC) of 25°C. exceed (TJ(MAX) − TC)/(RθJC). assumed to equal the values indicated.
http://onsemi.com INFORMATION FOR USING THE SOT−223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.079 2.0 0.15 3.8 0.248 6.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 0.091 2.3 0.091 2.3 mm inches SOT−223 POWER DISSIPATION The power dissipation of the SOT −223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T J(max), the maximum rated junction temperature of the die, R θJA, the thermal resistance from the device junction to am bient, and the operating temperature, T A. Using the values provided on the data sheet for the SOT −223 package, P D can be calculated as follows: PD = TJ(max) − TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature T A of 25 °C, one can calculate the power dissipation of the device which in this case is 943 milliwatts. PD = 175°C − 25°C 159°C/W = 943 milliwatts The 159°C/W for the SOT−223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 943 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT −223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RθJA versus drain pad area is shown in Figure 17.
0.8 Watts
Figure 15. Thermal Resistance versus Drain Pad or stainless steel with a typical thickness of 0.008 inches.
- Always preheat the device.
- The delta temperature between the preheat and soldering should be 100°C or less.*
- When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
- The soldering temperature and time shall not exceed 260°C for more than 10 seconds.
- When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.
- After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
- Mechanical stress or shock should not be applied during cooling * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
being used. This profile shows temperature versus time. degrees cooler than the adjacent solder joints.
40 TO 80 SECONDS
Figure 16. Typical Solder Heating Profile
http://onsemi.com PACKAGE DIMENSIONS STYLE 3: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN H S F A B D G L 12 3 0.08 (0003) C M K J DIM A MIN MAX MIN MAX MILLIMETERS 0.249 0.263 6.30 6.70 INCHES B 0.130 0.145 3.30 3.70 C 0.060 0.068 1.50 1.75 D 0.024 0.035 0.60 0.89 F 0.115 0.126 2.90 3.20 G 0.087 0.094 2.20 2.40 H 0.0008 0.0040 0.020 0.100 J 0.009 0.014 0.24 0.35 K 0.060 0.078 1.50 2.00 L 0.033 0.041 0.85 1.05 M 0 10 0 10 S 0.264 0.287 6.70 7.30 NOTES: /Em/figure1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. /Em/figure2. CONTROLLING DIMENSION: INCH. /C0095/C0095/C0095/C0095 SOT−223 (TO−261) CASE 318E−04 ISSUE K ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MMFT3055VL/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Thermal Clad is a registered trademark of the Bergquist Company.