MMC2080 MOTOROLA | Alldatasheet
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Rev. 0, 10/1999 This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Products Sector © Motorola, Inc., 1999. All rights reserved. MMC2080/2075 Advance Information MMC2080/2075 Integrated Processor with Roaming FLEX™ Decoder Part 1 Introduction The MMC2080/2075 is designed to provide the messaging and paging marketplace with a powerful and flexible solution to carry communications design into the next millennium. The MMC2080 integrates two of Motorola’s most successful product families, MCORE™ and the Roaming FLEX™ alphanumeric decoders, a combination that will set a new standard in the communications industry. Except for the FLEX decoder, the MMC2075 offers all features of the MMC2080. Both the The MMC2080/2075 are members of the low-power, high-performance MCORE family of 32-bit microcontroller units (MCUs). The MCORE is a streamlined execution engine that provides many of the performance enhancements found in mainstream reduced instruction set computers (RISCs). Combining performance, speed, and cost efficiency in a compact, low-power design, the MCORE microRISC architecture is a natural solution for applications where battery life and systems cost are critical design goals. Given that a total system’s components and processor core determine its power consumption, the instruction set architecture (ISA) for the MCORE is designed to optimize the trade-off between performance and total power consumption. The result is system-wide reduction of total energy consumption with maintenance of acceptable performance levels. Memory power consumption (both on-chip and external) is a major factor in system energy consumption. By adopting 16-bit instruction encoding, and thus significantly decreasing the memory bandwidth needed for a high rate of instruction execution, the MMC2080/2075 minimizes the overhead of memory system energy consumption. The MMC2080/2075 also reduces power consumption by coupling a fully static design with dynamic power management and low-voltage operation. Versatile power management is achieved through automatic power downs of any internal functional blocks not needed on a clock-by-clock basis. Power conservation modes are also provided for absolute power conservation. A table of contents for this document appears on the following page. Figure 1 on page 3 and Figure 2 on page 4 provide simplified block diagrams of the MMC2080/2075.
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Figure 1. MMC2080/2075 144 Block Diagram (144-Pin Package)
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Figure 2. MMC2080/2075 DVL Block Diagram (208-Pin Package)
1.1 Conventions and Terminology
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. — Active low signals change from logic level one to logic level zero. — Active high signals change from logic level zero to logic level one. Deasserted means that an asserted discrete signal changes logic state. — Active low signals change from logic level zero to logic level one. — Active high signals change from logic level on to logic level zero. and high bytes or words are spelled out. Please refer to the examples in Table 1. Table 1. Data Conventions
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Features
1.2 Features
The MMC2080/2075 offers the following suite of features. M CORE ™ RISC Processor — 32-bit load/store MCORE RISC architecture — Fixed 16-bit instruction length — 16-entry 32-bit general-purpose register file — 32-bit internal address and data buses — Efficient, four-stage, fully interlocked execution pipeline — Single-cycle execution for most instructions; two cycles for branches and memory accesses — Special branch, byte, and bit manipulation instructions — Support for byte, halfword, and word memory accesses — Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file Integrated Roaming FLEX alphanumeric decoder (MMC2080 only) — FLEX paging protocol signal processor — 1600, 3200, and 6400 bits per second (bps) decoding — Highly programmable receiver control — FLEX message fragmentation and group messaging support — SSID and NID roaming support — Internal demodulator and data slicer — Improved battery savings via partial address correlation and intermittent receiver clock — Full support for revision G1.9 of the FLEX protocol — External CAP code access through parallel or serial FLASH/PROM On-chip memory — 24 K × 32 CPU ROM (96 K) — 1.5 K × 32 CPU RAM (6 K) On-chip peripherals — Asynchronous serial communications interface (SCI) with IrDA capability — Synchronous serial peripheral interface (SPI) — Frequency synthesizer controller (FSC) — Melody generator — 4 × 4 keypad interface — Multipurpose I/O ports (MPIO) — Two 16-bit general purpose timers — Time-of-day (TOD) timer — Watchdog timer — Vectored interrupt controller with 16 programmable priority levels
/G8Introduction 7 Preliminary — Oscillator and PLL with software selectable speeds — AMBA peripheral bridge depipelines system bus for simpler peripheral bus — 8/16-bit external system bus with 22-bit address bus Operating features — Processor operation to 10 MHz over full operating range — Low-power modes — OnCE ™ (On-Chip Emulation) debug module — V oltage range 1.8 V to 3.6 V; temperature range -20 °C to 85 °C — Chip-select outputs for four external devices (4 Mbyte per chip select, 16 Mbyte directly addressable) — Programmable wait states for external accesses — External boot option — External bus interface that accepts internal, half-word, and byte transfers — External device that may become system bus master Development tools — Development option (different package) that adds select to bypass internal ROM — Development option (different package) that extends external bus to 32 bits — External bus that can display internal transfers
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1.3 Integrated Roaming FLEX Protocol and the MMC2080
The MMC2080 integrates several field-proven technologies, providing a versatile Roaming FLEX solution. gives the service provider an upward migration path that is completely transparent to the end user.
1.4 Target Applications
intended for applications requiring the processing power and flexibility of the MCORE CPU.
1.5 Product Documentation
World Wide Web. See the last page of this document for contact information.
1.6 Ordering Information
Products Sector sales office or authorized distributor to determine availability and to order parts. Table 2. MMC2080/2075 Documentation Table 3. MMC2080/2075 Ordering Information
MMC2080/2075 Pin Descriptions /G8Signal and Connection Descriptions 9 Preliminary Part 2 Signal and Connection Descriptions The pins and signals of the MMC2080/2075 are described in the following sections. Figure 3 on page 10 and Figure 4 on page 11 are top and bottom views, respectively, of the 12 mm x 12 mm MAP Ball Grid Array (BGA) package, and Figure 5 on page 12 and Figure 6 on page 13 are top and bottom views, respectively, of the 43 mm x 43 mm ceramic Pin Grid Array (PGA) package, showing the pin-outs. Table 4 on page 14 and Table 5 on page 17 list the pins by number and signal name. Figure 7 on page 21 is a representational pin-out of the chip, grouping the signals by their function. Table 6 on page 20 identifies the number of signals for each group and refers to Table 8 on page 23 through Table 20 on page 27, which are organized according to signal type and give a brief description of each signal pin.
2.1 MMC2080/2075 Pin Descriptions
The following section provides information about the available packages for this product, including diagrams of the package pin-outs and tables describing how the signals of the MMC2080/2075 are allocated. There are two packages for each part: The 144-pin I/O, STD small ball (SMBALL) mold array process (MAP) ball grid array (BGA), 12 mm x 12 mm package. Table 4 on page 14 identifies the signal associated with each pin. The 208-pin I/O, PGA, 43 mm x 43 mm ceramic package. Table 5 on page 17 identifies the signal associated with each pin.
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Figure 3. MMC2080/2075 BGA (144-Pin) Top View
Figure 4. MMC2080/2075 BGA (144-Pin) Bottom View
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Figure 5. MMC2080/2075 PGA (208-Pin) Top View
Figure 6. MMC2080/2075 PGA (208-Pin) Bottom View
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Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 1 of 3)
Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 2 of 3)
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Table 4. MMC2080/2075 BGA (144-Pin) Signal ID by Pin Number (Sheet 3 of 3)
Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 1 of 4)
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Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 2 of 4)
Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 3 of 4)
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2.2 Tables of Signals
in the 208-pin development extensions package. Table 6. MMC2080 Signal Functional Group Organization Table 5. MMC2080/2075 PGA (208-Pin) Signal ID by Pin Number (Sheet 4 of 4)
Figure 7. MMC2080 Signal Group Organization
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Table 7. I/O Cell Description
Table 8. External System Bus Signals disabled and pull-up resistors are enabled during reset. resistors are enabled during reset. two bits is a 4 Mbyte address space. (high) and EB1 is always asserted (low). driven by the MMC2080 and received by an external device. also indicates the end of internal transactions. aborted, this pin is driven low. BUSCLK O Y OTP External Bus Clock. may be individually programmed as active low or active high. otherwise the internal boot map is enabled.
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Table 9. Development Extensions (208-Pin Package) either DVL0 or _DVL0 is asserted. output. DVLEB0 enables D[31:24] and DVLEB1 enables D[23:16]. asserted to select an external memory. bus masters (BGNT is low) and for debug monitor modes. DVLMX I N INHPP Selects the output of DSTAT[5:0]. TC[2:0] ON O T P Processor Transfer Code. TEA I N INHPP Transfer Error Acknowledge (active low). the pull-up resistor on this I/O cell) are disabled. SHS ON O T P Show Cycle Strobe (active low)— Strobes low when data is valid.
Table 10. FLEX Signals (MMC2080 Only) sensing circuit is required.) Polarity is programmable. EXTS[1:0] In Y IOHP External Symbol — EXTS 1 is the MSB of the current FLEX symbol. when demodulation is being performed externally. clock output (derived from oscillator). by reducing jitter from cable-induced noise. control lines. Selectable polarity. clear (that is, the internal demodulator is disabled). the internal demodulator is enabled). Table 11. FSC/SPI1 Signals Table 12. SCI Signals
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Table 13. Timer Signals Table 14. Melody Generator Signal Table 15. Keypad Signals Table 16. MPIO Signals latched at the beginning of a read cycle. MPIO input pin is latched at the beginning of a read cycle. Table 17. SIM Signals
Table 20. Arbitration Signals Table 18. JTAG/OnCE™ Signals Table 19. Clock and Power
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3.1 General Characteristics
completion of full characterization and device qualifications.
3.2 Maximum Ratings
represents a condition that can never exist. Remaining specification information to be provided. Table 21. DC Absolute Maximum Operating Conditions
engineering use only. Contact the factory for availability.
4.1 BGA Details
4.1.1 BGA Package Mechanical Drawings
The mechanical drawings for the 144-pin Ball Grid Array package are shown in Figure 8. Figure 8. MMC2080/2075 BGA Mechanical Drawings
0.15 Z XY
- DIMENSIONS ARE IN MILLIMETERS.
- INTERPRET DIMENSIONS AND TOLERANCES PER
- DIMENSION b IS MEASURED AT THE MAXIMUM
- DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
- PARALLELISM MEASUREMENT SHALL EXCLUDE ANY
EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
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4.2 PGA Details
the factory for availability. Refer to Figure 9 for the package drawings and dimensions.
4.2.1 PGA Package Mechanical Drawings
The mechanical drawings for the 208-pin Ball Grid PGA package are shown in Figure 9. Figure 9. MMC2080/2075 PGA Mechanical Drawings
- DIMENSIONS ARE IN MILLIMETERS.
- INTERPRET DIMENSIONS AND TOLERANCES PER
- MINIMUM SPACING BETWEEN CONDUCTORS SHALL
/G8Pin-out and Package Information 31 Preliminary
4.3 Ordering Drawings
Complete mechanical information regarding MMC2080/2075 packaging is available by facsimile through Motorola’s MFAX ™ system. Call the following number to obtain information by facsimile: The MFAX automated system requests the following information: The receiving facsimile telephone number, including area code or country code The caller’s personal identification number (PIN) NOTE: For first-time callers, the system provides instructions for setting up a PIN, which requires the entry of a name and telephone number. The type of information requested: — Instructions for using the system — A literature order form — Specific-part technical information or datasheets — Other information described by the system messages A total of three documents may be ordered per call. The MMC2080/2075 144-pin BGA package mechanical drawing is referenced as Case 1248A-01 Rev. 0. The MMC2080/2075 208-pin BGA package mechanical drawing is referenced as Case 1297-01 Rev. 0. (602) 244-6591
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Part 5 Design Considerations
5.1 Heat Dissipation
An estimate of the MMC2080/2075 chip junction temperature, TJ, in °C can be obtained from the following equation. Where: TA = ambient temperature °C R θJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, as follows: Where: R θJA = package junction-to-ambient thermal resistance °C/W R θJC = package junction-to-case thermal resistance °C/W R θCA = package case-to-ambient thermal resistance °C/W R θJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA . For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; ninety percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device’s thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, if the estimations obtained from R θJA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD . As noted previously, the junction-to-case thermal resistances quoted in this document are determined using the first definition. From a practical standpoint, this value is also suitable for determining the junction TJ TA P D R θJA×()+= R θJA R θJC R θCA+=
Electrical Design Considerations /G8Design Considerations 33 Preliminary temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than the actual temperature. Hence, the new thermal metric, thermal characterization parameter or Ψ JT, has been defined to be (TJ - TT)/ PD . This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. NOTE: Section 3, “Specifications,” on page 28 of this document contains the package thermal values for this chip.
5.2 Electrical Design Considerations
WARNING: This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either Vss or V DD ). Use the following list of recommendations to assure correct operation: Provide a low-impedance path from the board power supply to each Vdd pin on the MMC2080/ 2075 and from the board ground to each Vss pin. Use at least four 0.1 µF bypass capacitors positioned as close as possible to the four sides of the package to connect the Vdd power source to Vss. Ensure that capacitor leads and associated printed circuit traces that connect to the chip Vdd and Vss pins are less than 0.5 inch per capacitor lead. Use at least a four-layer printed circuit board (PCB) with two inner layers for Vdd and Vss. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the Vdd and Vss circuits. All inputs must be terminated (that is, not allowed to float) using CMOS levels. Take special care to minimize noise levels on the PLL supply pins (both Vdd and Vss).
OnCE, M CORE, MFAX, Roaming FLEX, FLEX Alphanumeric Chip, FLEX Chip, FLEX Numeric Chip, and FLEX Stack are trademarks of Motorola, Inc. This document contains information on a new product. Specifications and information herein are subject to change without notice. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. All other tradenames, trademarks, and registered trademarks are the property of their respective owners. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217 1-303-675-2140 or 1-800-441-2447 JAPAN : Motorola Japan, Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, 2 Tai Po, N.T., Hong Kong. 852-26668334 Customer Focus Center: 1-800-521-6274 Mfax™ : RMFAX0@email.sps.mot.com –TOUCHTONE 1-602-244-6609 –US & Canada ONLY 1-800-774-184 –http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps Motorola DSP Products Home Page: http://www.motorola-dsp.com MMC2080/2075/D