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Freescale Semiconductor Document Number: MMA955xL Data Sheet: Advance Information Rev. 1, 10/2011 An Energy Efficient Solution by Freescale This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2011 Freescale Semiconductor, Inc. All rights reserved. Intelligent Motion-Sensing Platform The MMA955xL device is a member of Freescale’s Xtrinsic family of intelligent sensor platforms. This device incorporates dedicated accelerometer MEMS transducers, signal conditioning, data conversion, and a 32-bit programmable microcontroller. This unique blend transforms Freescale’s MMA955xL into an intelligent, high- precision, motion-sensing platform able to manage multiple sensor inputs. This device can make system-level decisions required for sophisticated applications such as gesture recognition, pedometer functionality, tilt compensation and calibration, and activity monitoring. The MMA955xL device is programmed and configured with the CodeWarrior Development Studio for Microcontrollers software, version 10.1 or later. This standard integrated design environment enables customers to quickly implement custom algorithms and features to exactly match their application needs. Using the master I2C port, the MMA955xL device can manage secondary sensors, such as pressure sensors, magnetometers, or gyroscopes. This allows sensor initialization, calibration, data compensation, and computation functions to be off-loaded from the system application processor. The MMA955xL device also acts as an intelligent sensing hub and a highly configurable decision engine. Total system power consumption is significantly reduced because the application processor stays powered down until absolutely needed. Hardware Features

  • Three accelerometer operating ranges: – ±2g suits most hand gestures (orientation detection and tit control) and freefall. For tap detection, ±4g and ±8g are supported. – ±4g covers most regular human dynamics (walking and jogging) – ±8g detects most abrupt activities (gaming)
  • Integrated temperature sensor
  • One slave SPI or I 2C interface operating at up to 2 Mbps, dedicated to communication with host processor. Default value of the I2C, 7-bit address is 0x4C. (This can be customized by firmware.)
  • One master I 2C interface operating at up to 400 kbps that can be used to communicate with external sensors
  • Eight selectable output data rates (ODR), from 488 Hz to 3.8 Hz
  • 10, 12, 14, and 16-bit trimm ed ADC data formats available
  • 1.8V supply voltage
  • 32-bit ColdFire V1 CPU with MAC unit
  • Extensive set of power-management features and low-power modes
  • Integrated ADC can be used to convert external analog signals
  • Single-Wire, Background-Debug Mode (BDM) pin interface
  • 16-KB flash memory
  • 2-KB Random Access Memory
  • ROM-based flash controller and sl ave-port, command-line interpreter
  • Two-channel timer with in put capture, output capture, or edge-aligned PWM
  • Programmable delay block for scheduling events relative to start of frame
  • A 16-bit, modulo timer for scheduling periodic events
  • Minimal external component requirements
  • RoHS compliant (-40 to +85ºC), 16-pin, 3 x 3 x 1-mm LGA package 16-pin LGA 3 mm x 3 mm x 1 mm Case 2094-01 MMA955xL Top and bottom view Top view Pin connections 678 16 15 14 VDD RGPIO7/AN1/ TPMCH1 RGPIO8/PDB_B SDA0/RGPIO1/SDI BKGD-MS /RGPIO9 RESETB SCL0/RGPIO0 SCLK VSS RGPIO2/SCL1/SDO RGPIO3/SDA1/SSB RGPIO6/AN0 TPMCH0 RGPIO5/PDB_A/ INT_O V SS RGPIO4/INT VDDA VSSA

2 Freescale Semiconductor, Inc.

  • Orientation detection (portrait/landscape)
  • High-g/Low-g threshold detection
  • Pulse detection (single, double and directional tap)
  • Tilt detection
  • Auto wake/sleep
  • Embedded, smart FIFO
  • Power management
  • Pedometer A selection of the software features are included in the factory-programmed firmware for some devices. Users may add their own features with user firmware.The power and flexibility of the embedded ColdFire V1 MCU core has new and unprecedented capabilities.

Table 1. Ordering information

3 Freescale Semiconductor, Inc. Related Documentation The MMA955xL device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at: http://www.freescale.com/ 2. In the Keyword search box at the top of the page, enter the device number MMA955xL. 3. In the Refine Your Result pane on the left, click on the Documentation link.

Contents

4 Freescale Semiconductor, Inc.

1 Variations of MMA955xL Device

pendent of the Freescale firmware versions. The following table lists some of the variations among the MMA955xL-platform devices. Table 2. Features of product-line devices

  • Normal mode Ye s Ye s Ye s N o
  • Legacy mode Ye s Ye s Ye s N o
  • Streaming mode Ye s Ye s Ye s N o Front-end processing
  • 100-Hz BW anti-aliasing Ye s Ye s Ye s N o
  • 50-Hz BW anti-aliasing Ye s Ye s Ye s N o
  • g-mode-dependent resolution Ye s Ye s Ye s Ye s
  • Absolute value Ye s Ye s Ye s N o
  • Low-pass filter Ye s Ye s Ye s N o
  • High-pass filter Ye s Ye s Ye s N o
  • Data-ready interrupt Ye s Ye s Ye s Ye s Gesture applications
  • High g/Low g No Y es No No
  • Tilt No Y es No No
  • Portrait/Landscape No Y es No No
  • Programmable orientation No Y es No No
  • Tap/Double-tap No Y es No No
  • Freefall No Y es No No
  • M o t i o n No Y es No No

factory. The user still can add custom software using the remaining portion of flash memory. interpreter and applications scheduler and can interact directly with the users’ host system. device needs to be programmed with custom user code.

  • D a t a F I F O Ye s Ye s Ye s N o
  • Event queue Ye s Ye s Ye s N o
  • Inter-process FIFO No No No Y es Power-control module
  • Run and Stop on idle Ye s Ye s Ye s Ye s
  • Run and No stop Ye s Ye s Ye s Ye s
  • S t o p N C Ye s Ye s Ye s Ye s
  • Auto-Wake / Auto-Sleep / Doze Ye s Ye s Ye s N o Data-management daemons Y es Y es Y es Pedometer applications
  • Step count No No Y es No
  • D i s t a n c e No No Y es No
  • Adaptive distance No No Y es No
  • Activity monitor No No Y es No

Table 2. Features of product-line devices (Continued)

6 Freescale Semiconductor, Inc.

2 Typical Applications

This low-power, intelligent sensor platform is optimized for use in portable and mobile consumer products such as:

  • Mobile phones/PMP/PDA/digital cameras – Orientation detection (portrait/landscape) – Image stability – Tilt control enabled with higher resolution – Gesture recognition – Tap to control – Auto wake/sleep for low power consumption
  • Smartbooks/ereaders/netbooks/laptops – Anti-theft – Freefall detection for hard-disk drives – Orientation detection – Tap detection
  • Pedometers
  • Gaming and toys
  • Activity monitoring in medical applications
  • S e c u r i t y – Anti-theft – Shock detection –T i l t
  • Fleet monitoring, tracking – Dead reckoning – System auto-wake on movement – Detection – Shock recording – Anti-theft
  • Power tools and small appliances –T i l t – Safety shut-off

3 General Description

3.1 Functional Overview

or a differential analog signal from an external device. These measured values can be read via the slave I2C or SPI port or utilized internally within the MMA955xL platform. Figure 1. Platform block diagram(1)

  1. Preliminary data for memory sizes.
  • The analog sub-system is composed of: – A 3-axis transducer that is an entirely passive block including the MEMS structures. – An Analog Front End (AFE) with the following:
  • A capacitance-to-voltage converter (C to V)
  • An analog-to-digital converter
  • A temperature sensor
  • The digital sub-system is composed of: – The 32-bit, ColdFire V1 CPU with a Background-Debug Module (BDM) – Memory: RAM, ROM, and flash – Rapid GPIO (RGPIO) port-control logic – Timer functions include:
  • Modulo timer module (MTIM16)
  • Programmable Delay Timer (PDB) Analog Front End (AFE)BDM INTC DBG

4 KB x 32

1 KB x 32

512 KB x 32

8 Freescale Semiconductor, Inc.

  • General-Purpose Time r/PWM Module (TPM) –I 2C master interface –I 2C or SPI slave interface – System Integration Module (SIM) – Clock-Generation Module The slave interfaces (either SPI or I2C) operate independently of the CPU subsystem. They can be accessed at any time, includ- ing while the device is in low-power, deep-sleep mode.

3.2 Packaging Information

CPU offering, as well as other competitive devices. All pins on the device are utilized and many are multiplexed. The following sections describe the pinout. Users can select from multiple pin functions via the SIM pin, mux-control registers.

3.2.1 Package diagrams

Figure 2. Device pinout (top view) and package frame convention

10 Freescale Semiconductor, Inc. Figure 5. Recommended PCB footprint

3.2.2 Sensing Direction and Output Response

the standard abbreviations or names for the six different orientation modes: portrait up/down, landscape left/right and back/front. Figure 6. Sensing direction and output response

3.2.3 Pin Functions

The following table summarizes functional options for each pin on this device. Table 3. Pin functions

  1. Pin function #1 represents the reset state of the hardware. Pin functions can be changed via the SIM pin, mux-control registe rs in Freescale or user firmware.

1 VDD Digital power supply

2 BKGD/MS RGPIO9 Background-debug / Mode select / RGPIO9

3 RESETB(2)

  1. RESETB is an open-drain, bidirectional pin. Reset must be pulled high at startup. After startup, Reset may be asserted to res et the device.

4 SCL0 RGPIO0 SCLK Serial clock for slave I2C / RGPIO0 / Serial clock for slave SPI

5 VSS Digital ground

6 SDA0 RGPIO1 SDI Serial data for slave I2C / RGPIO1 / SPI serial data input

  1. RGPIO3/SDA1/SSB = Low at startup selects SPI. High at startup selects I 2C. This is a function of the application boot code, not of the hardware.

9 RGPIO4 INT RGPIO4 / Interrupt input

11 RGPIO5 PDB_A INT_O RGPIO5 / PDB_A / INT_O slave-port interrupt output

12 RGPIO6 AN0 TPMCH0 RGPIO6 / ADC Input 0 / TPM Channel 0

13 RGPIO7 AN1 TPMCH1 RGPIO7 / ADC Input 1 / TPM Channel 1

14 VDDA Analog power

15 RGPIO8 PDB_B RGPIO8 / PDB_B

16 VSSA Analog ground

12 Freescale Semiconductor, Inc.

3.3 Pin Function Descriptions

This section provides a brief description of the various pin functions available on the MMA955xL platform. Ten of the device pins are multiplexed with Rapid GPIO (RGPIO) functions. The “Pin Function #1” column in Table 3 on page 11 lists which function is active when the hardware exits the reset state. Freescale or user firmware can use the pin mux-control registers in the System Integration Module (SIM) to change pin assignments for each pin after reset. For detailed information about these registers, see the MMA955xL Three-Axis Accelerometer Reference Manual (MMA955xLRM). VDD and VSS: Digital power and ground. VDD is nominally 1.8V. VDDA and VSSA: Analog power and ground. VDDA is nominally 1.8V. To optimize performance, the VDDA line can be filtered to remove any digital noise that can be present on the 1.8V supply. (See Figure 5 and Figure 6 on page 17.) RESETB: The RESETB pin is an open-drain, bidirectional pin with an internal, weak, pullup resistor. At start up, it is configured as an input pin, but also can be programmed to become bidirectional. Using this feature, the MMA955xL device can reset external devices for any purpose other than power-on reset. Reset must be pulled high at startup. After startup, Reset may be asserted to reset the device. The total external capacitance to ground has to be limited when using RESETB-pin, output-drive capability. For more details, see the “System Integration Module” chapter of the MMA955xL Three-Axis Accelerometer Reference Manual (MMA955xLRM). Slave I2C port: SDA0 and SCL0: These are the slave-I2C data and clock signals, respectively. The MMA955xL device can be controlled via the serial port or via the slave SPI interface. Master I 2C: SDA1 and SCL1: These are the master-I2C clock and data signals, respectively. Analog-to-Digital Conversion: AN0, AN1: The on-chip ADC can be used to perform a differential, analog-to-digital conversion based on the voltage present across pins AN0(-) and AN1(+). Conversions for these pins are at the same Output Data Rate (ODR) as the MEMS transducer signals. Input levels are limited to 1.8V differential. Rapid General Purpose I/O: RGPIO[9:0]: The ColdFire V1 CPU has a feature called Rapid GPIO (RGPIO). This is a 16-bit, input/output port with single-cycle write, set, clear, and toggle functions available to the CPU. The MMA955xL device brings out the lower 10 bits of that port as pins of the device. Interrupts: INT: This input pin can be used to wake the CPU from a deep-sleep mode. It can be programmed to trigger on either rising or falling edge, or high or low level. This pin operates as a Level-7 (high-priority) interrupt. Debug/Mode Control: BKGD/MS: At start up, this pin operates as mode select. If this pin is pulled high during start up, the CPU will boot normally and run code. If this pin is pulled low during start up, the CPU will boot into active Background-Debug Mode (BDM). In BDM, this pin operates as a bidirectional, single-wire, background-debug port. It can be used by development tools for downloading code into on-chip RAM and flash and to debug that code. Timer: PDB_A and PDB_B: These are the two outputs of the programmable delay block. Slave SPI Interface: SCLK, SDI, SDO and SSB: These pins control the slave SPI clock, data in, data out, and slave-select signals, respectively. The MMA955xL platform can be controlled via this serial port or via the slave-I 2C interface. SBB has a spe- cial function at startup that selects the Slave interface mode. Low at startup selects SPI and high selects I2C. INT_O: The slave-port output interrupt pin. This pin can be used to flag the host when a response to a command is available to read on the slave port. TPMCH0 and TPMCH1: The I/O pin associated with 16-bit, TPM channel 0 and 1.

3.4 System Connections

3.4.1 Power Sequencing

An internal circuit powered by VDDA provides the device with a power-on-reset signal. In order for this signal to be properly rec- ognized, it is important that VDD is powered up before or simultaneously with VDDA. The voltage potential between VDD and VDDA must not be allowed to exceed the value specified in Table 7 on page 17.

3.4.2 Layout Recommendations

  • Provide a low-impedance path from the board power supply to each power pin (V DD and VDDA) on the device and from the board ground to each ground pin (VSS and VSSA).
  • Place 0.01 to 0.1-µF capacitors as close as possible to th e package supply pins to meet he minimum bypass requirement. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs. VDDA/VSSA. ceramic and tantalum capacitors tend to provide better tolerances.
  • Ensure that capacitor leads and associated printed-circuit traces that connect to the chip V DD and VSS (GND) pins are as short as possible.
  • Bypass the power and ground with a capacitor of approxim ately 1 µF and a number of 0.1-µF ceramic capacitors.
  • Minimize PCB trace lengths for hi gh-frequency signals. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
  • Take special care to minimi ze noise levels on the VDDA and VSSA pins.
  • Use separate power planes for V DD and VDDA and separate ground planes for VSS and VSSA. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuits are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in series with both the VDDA and VSSA traces.
  • Physically separate the analog components from noisy digita l components by ground planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces.
  • Provide an interface to the BKGD/MS pin if in-circuit debug capability is desired.
  • Ensure that resistors R P1 and RP2, in the following figure, match the requirements stated in the I2C standard. For the shown configuration, the value of 4.7 kΩ would be appropriate.

3.4.3 MMA955xL Platform as an Intelligent Slave

I2C pullup resistors, a ferrite bead, and a few bypass capacitors are all that are required to attach this device to a host platform. to the external interrupt pins of the CPU. Figure 7. Platform as an I2C slave

14 Freescale Semiconductor, Inc. Figure 8. Platform as an SPI slave

3.4.4 MMA955xL Platform as a Sensor Hub

features can all be monitored using the on-chip ADC. fidence that the MMA955xL device will issue a wake request should any external event require its attention. Figure 9. Platform as sensor hub

16 Freescale Semiconductor, Inc.

4 Mechanical and Electrical Specifications

information on power considerations, DC/AC electrical characteristics, and AC timing specifications.

4.1 Definitions

sensitivity varies with the direction of cross acceleration and is primarily due to misalignment. calibrated during factory test using a least-squares fit of the raw sensor data. Linearity error The deviation of the sensor output from a least-squares linear fit of the input/output data. Nonlinearity The systematic deviation from the straight line that defines the nominal input/output relationship. data sheet parameters. Pin groups are defined in Section 4.2, “Pin Groups”. set calibration features—improve sensor performance. documented operating conditions.

4.2 Pin Groups

The following pin groups are used throughout the remainder of this section.

4.3 Absolute Maximum Ratings

remaining tables in this section. Table 4. Absolute maximum ratings

4.4 Operating Conditions

4.5 Electrostatic Discharge (ESD) a nd Latch-up Protection Characteristics

4.6 General DC Characteristics

Table 5. Nominal operating conditions Table 6. ESD and latch-up protection characteristics Table 7. DC characteristics(1) 1.All conditions at nominal supply: VDD = VDDA = 1.8V. 2.Pin groups are defined in “Pin Groups” on page 16.

  • Low-drive strength
  • High-drive strength VOH Pin Groups 1 and 3 ILOAD = -2 mA ILOAD = -3 mA VDD - 0.5 — — V Output voltage low
  • Low-drive strength
  • High-drive strength VOL Pin Groups 1 and 3 ILOAD = 2 mA ILOAD = 3 mA —— 0 . 5V Output-low current Max total IOL for all ports IOLT 24 mA Output-high current Max total I OH for all ports IOHT 24 mA Input-leakage current |IIN| Pin Group 2 Vin = VDD or VSS —0 . 1 1 µ A Hi-Z (off-state) leakage current |IOZ| Pin Group 3 input resistors disabled Vin = VDD or VSS —0 . 1 1 µ A Pullup resistor RPU when enabled 17.5 52.5 K Ω Power-on-reset voltage VPOR 1.50 V Power-on-reset hysteresis VPOR-hys 100 mV Input-pin capacitance CIN 7p F Output-pin capacitance COUT 7p F

18 Freescale Semiconductor, Inc.

4.7 Supply Current Characteristics

4.8 Accelerometer Transducer Mechanical Characteristics

Table 8. Supply current characteristics(1)

  1. All conditions at nominal supply: V DD = VDDA = 1.8V.
  2. Total current with the analog section active, 16 bits ADC reso lution selected, MAC unit used and all peripheral clocks enabled.

Table 9. Accelerometer characteristics

4.9 Temperature Sensor Characteristics

4.10 ADC Characteristics

4.11 ADC Sample Rates

  • 488.28 frames per second (fps)
  • 244.17 fps
  • 122.07 fps
  • 61.04 fps
  • 30.52 fps
  • 15.26 fps
  • 7 . 6 3 f p s
  • 3 . 8 1 f p s

Table 10. Temperature sensor characteristics

  1. All conditions at nominal supply: V DD = VDDA = 1.8V.

Table 11. ADC characteristics(1)

  1. All conditions at nominal supply: V DD = VDDA = 1.8V and RES = 14, unless otherwise noted.

20 Freescale Semiconductor, Inc.

4.12 AC Electrical Characteristics

points, as shown in the following figure. Figure 10. Input signal measurement references

  • Active state, when a bus or signal is driven and enters a low-impedance state
  • Three-stated, when a bus or signal is placed in a high-impedance state
  • Data Valid state, when a signal level has reached V OL or VOH
  • Data Invalid state, when a signal level is in transition between V OL and VOH

Figure 11. Signal states

4.13 General Timing Control

Table 12. General timing characteristics(1)

  1. All conditions at nominal supply: V DD = VDDA = 1.8 V
  2. This is the time measured from V DD = VPOR until the internal reset signal is released.
  3. In the formulas, T = 1 system clock cycle. In full speed mode, T is nominally 125 ns. In slow speed mode, T is nominally 16 μs.

Note: The midpoint is VIL + (VIH – VIL)/2.

4.14 I 2C Timing

includes a master/slave I2C module that should be used only during CPU run mode (ΦD). Figure 12. I2C standard and fast-mode timing

4.14.1 Slave I 2C

4.14.2 Master I 2C Timing

module across frames in which a portion of the time is spent in low-speed mode. Table 13. I2C Speed Ranges

  1. The maximum t HD; DAT must be at least a transmission time less than tVD;DAT or tVD;ACK. For details, see the I2C standard.
  2. Timing met with IFE = 0, DS = 1, and SE = 1. See the “Port Controls” chapter in the MMA955xL Three-Axis Accelerometer Reference Manual

Table 14. Master I2C timing

  1. The master mode I 2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a neg-

ative hold time can result, depending on the edge rates of the SDA and SCL lines.

  1. The maximum t HD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
  2. Setup time in slave-transmitter mode is one IPBus clock period, if the TX FIFO is empty.
  3. A fast-mode I 2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This will automat-

22 Freescale Semiconductor, Inc.

4.15 Slave SPI Timing

Figure 13. SPI slave timing Table 15. Slave SPI timing

1 SCLK period tSCLK 4— t CYCH

4 Clock (SCLK) high or low time tWSCLK 200 — ns

5 Data setup time (inputs) tSU 15 — ns

6 Data-hold time (inputs) tHI 25 — ns

7 Access time ta —2 5n s

8 SDO-disable time tdis —2 5n s

9 Data valid (after SCLK edge) tv —2 5n s

10 Data-hold time (outputs) tHO 0— n s

  1. Not defined but normally MSB of character just received.

4.16 Flash Parameters

memory. Chip supply voltage of 1.8V is sufficient for the flash programming voltage. block of memory that can be programmed is 128 bytes and the block must start at a 128-byte boundary. Flash programming blocks must start on a 4-byte boundary and cannot cross a 128-byte page boundary.

5 Package Information

Figure 14. Flash memory map for devices Table 16. Flash parameters

14.5 KB(1 )

24 Freescale Semiconductor, Inc.

6 Revision History

date Description of changes 0 06/2011 Initial release of document. 1 10/2011 • Removed MMA9552L device from product family and added the MMA9559L device.

  • Added a features table and a package land diagram figure.
  • Modified block diagram
  • Inserted flash memory map figure

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