MMA9550L

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Document overview

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Technical content

Datasheet sections

• 1 Variations of MMA955xL Device
• 2 Typical Applications
• 3 General Description
• 3.2.1 Package diagrams
• 3.2.2 Sensing Direction and Output Response
• 3.2.3 Pin Functions
• 3.4.1 Power Sequencing
• 3.4.2 Layout Recommendations
• 3.4.3 MMA955xL Platform as an Intelligent Sl ave
• 3.4.4 MMA955xL Platform as a Sensor Hub
• 4 Mechanical and Electrical Specifications
• 4.13.1 Slave I2C
• 4.13.2 Master I2C Timing
• 5 Package Information
• 6 Revision History

Freescale Semiconductor Document Number: MMA955xL Data Sheet: Technical Data Rev. 3.1, 5/2015 An Energy Efficient Solution by Freescale © 2011, 2013, 2015 Freescale Semiconductor, Inc. All rights reserved. MMA955xL Intelligent Motion-Sensing Platform The MMA955xL device an intelligent sensor, incorporating dedicated accelerometer MEMS transducers, signal conditioning, data conversion, and a 32-bit programmable microcontroller. This unique blend transforms Freescale’s MMA955xL into an intelligent, high- precision, motion-sensing platform able to manage multiple sensor inputs. This device can make system-level decisions required for sophisticated applications such as gesture recognition, pedometer functionality, tilt compensation and calibration, and activity monitoring. The MMA955xL device is programmed and configured with the CodeWarrior Development Studio for Microcontrollers software, version 10.1 or later. This standard integrated design environment enables customers to quickly implement custom algorithms and features to exactly match their application needs. Using the master I 2C port, the MMA955xL device can manage secondary sensors, such as pressure sensors, magnetometers, or gyroscopes. This allows sensor initialization, calibration, data compensation, and computation functions to be off-loaded from the system application processor. The MMA955xL device also acts as an intelligent sensing hub and a highly configurable decision engine. Total system power consumption is significantly reduced because the application processor stays powered down until absolutely needed. Hardware Features

• Three accelerometer operating ranges: –± 2 g suits most hand gestures (orientation detection and tilt control) and freefall. For tap detection, ±4 g and ±8 g are supported. –± 4 g covers most regular human dynamics (walking and jogging) –± 8 g detects most abrupt activities (gaming)
• Integrated temperature sensor
• One slave SPI or I 2C interface operating at up to 2 Mbps, dedicated to communication with the host processor. Default value of the I2C, 7-bit address is 0x4C. (This can be customized by firmware.)
• One master I 2C interface operating at up to 400 kbps that can be used to communicate with external sensors
• Eight selectable output data rates (ODR), from 488 Hz to 3.8 Hz (extending farther from 3906 Hz to 0.24 Hz with MMA9559L Firmware version)
• 10, 12, 14, and 16-bit trimm ed ADC data formats available
• 1.8 V supply voltage
• 32-bit CPU with MAC unit
• Extensive set of power-management features and low-power modes
• Integrated 16-bit resolution ADC can be used to convert external analog signals
• Single-Wire, Background-Debug Mode (BDM) pin interface
• 16-KB flash memory
• 2-KB Random Access Memory
• ROM-based flash controller and sl ave-port, command-line interpreter
• Two-channel timer with in put capture, output capture, or edge-aligned PWM
• Programmable delay block for scheduling events relative to start of frame
• A 16-bit, modulo timer for scheduling periodic events
• Minimal external component requirements
• RoHS compliant (–40ºC to +85ºC), 16-pin, 3 x 3 x 1-mm LGA package 16-pin LGA 3 mm x 3 mm x 1 mm Case 2094-01 MMA9550L MMA9551L MMA9553L MMA9559L Top and bottom view Top view Pin connections 678 16 15 14 VDD RGPIO7/AN1/ TPMCH1 RGPIO8/PDB_B SDA0/RGPIO1/SDI BKGD-MS /RGPIO9 RESETB SCL0/RGPIO0 SCLK VSS RGPIO2/SCL1/SDO RGPIO3/SDA1/SSB RGPIO6/AN0 TPMCH0 RGPIO5/PDB_A/ INT_O V SS RGPIO4/INT VDDA VSSA

2 Freescale Semiconductor, Inc.

• Orientation detection (portrait/landscape)
• High- g/Low-g threshold detection
• Pulse detection (single, double and directional tap)
• Tilt detection
• Auto wake/sleep
• Embedded, smart FIFO
• Power management
• Pedometer A selection of the software features are included in the factory-programmed firmware for some devices. Users may add their own features with user firmware.The power and flexibility of the embedded ColdFire V1 MCU core associated with the high perfor- mance 3-axis accelerometer give new and unprecedented capabilities to the MMA955xL devices family.

Table 1. Ordering information

4 Freescale Semiconductor, Inc.

1 Variations of MMA955xL Device

pendent of the Freescale firmware versions. The following table lists some of the variations among the MMA955xL-platform devices. Table 2. Features of product-line devices

• Normal mode Yes Yes Yes No
• Legacy mode Yes Yes Yes No
• Streaming mode Yes Yes Yes No Front-end processing
• 100-Hz BW anti-aliasing Yes Yes Yes No
• 50-Hz BW anti-aliasing Yes Yes Yes No
• g-mode-dependent resolution YesY esY esY es
• Absolute value Yes Yes Yes No
• Low-pass filter Yes Yes Yes No
• High-pass filter Yes Yes Yes No
• Data-ready interrupt YesY esY esY es Gesture applications
• High g/Low g No Yes No No
• T i l t No Yes No No
• Portrait/Landscape No Yes No No
• Programmable orientation No Yes No No
• Tap/Double-tap No Yes No No
• Freefall No Yes No No
• M o t i o n No Yes No No

factory. The user still can add custom software using the remaining portion of flash memory. MMA9555L is described on a separate data sheet due to the device’s configuration. interpreter and applications scheduler and can interact directly with the users’ host system. device needs to be programmed with custom user code.

• Data FIFO Yes Yes Yes No
• Event queue Yes Yes Yes No
• Inter-process FIFO No No No Yes Power-control module
• Run and Stop on idle YesY esY esY es
• Run and No stop YesY esY esY es
• S t o p N C YesY esY esY es
• Auto-Wake / Auto-Sleep / Doze Yes Yes Yes No Data-management daemons Yes Yes Yes Yes Pedometer applications
• Step count No No Yes No
• Distance No No Yes No
• Adaptive distance No No Yes No
• Activity monitor No No Yes No

Table 2. Features of product-line devices (Continued)

6 Freescale Semiconductor, Inc.

2 Typical Applications

This low-power, intelligent sensor platform is optimized for use in portable and mobile consumer products such as:

• Tablets/PMPs/PDAs/digital cameras – Orientation detection (portrait/landscape) – Image stability – Tilt-control enabled with higher resolution – Gesture recognition – Tap to control – Auto wake/sleep for low power consumption
• Smartbooks/ereaders/netbooks/laptops – Anti-theft – Freefall detection for hard-disk drives – Orientation detection – Tap detection
• Pedometers
• Gaming and toys
• Activity monitoring in medical applications
• S e c u r i t y – Anti-theft – Shock detection –T i l t
• Fleet monitoring, tracking – System auto-wake on movement – Detection – Shock recording – Anti-theft
• Power tools and small appliances –T i l t – Safety shut-off

3 General Description

3.1 Functional Overview

or a differential analog signal from an external device. Figure 1. Platform block diagram

• The analog subsystem is composed of: – A 3-axis transducer that is an entirely passive block including the MEMS structures. – An Analog Front End (AFE) with the following:
• A capacitance-to-voltage converter (CVC)
• An analog-to-digital converter
• A temperature sensor
• The digital subsyst em is composed of: – A 32-bit, CPU with a Background-Debug Module (BDM) – Memory: RAM, ROM, and flash – Rapid GPIO (RGPIO) port-control logic – Timer functions include:
• Modulo timer module (MTIM16)
• Programmable Delay Timer (PDB) $QDORJ)URQW(QG $)( %'0 ,17& '%* )ODVK 520 5$0 ,&0DVWHU D[LV &WR9 $'& 7HPS 6HQVRU ,&VODYH 63,VODYH &RQWURO DQG PDLOER[&/.*(1 7ZRFKDQQHOELW 7LPHU3:0PRGXOH ELW 0RGXORWLPHUPRGXOH 3URJUDPPDEOH GHOD\\EORFN /EdͺK D[LV D[LV 9'' 966 5(6(7 966 9''$ 966$ 5*3,2 6&/ 5*3,& 6&/. 6'$ 5*3,2 6', 5*3,2 6&/ 6'2 5*3,2 6'$ 66% 5*3,2 ,17 5*3,2 3'% B$,17 B2 5*3,2 $1 730&+ 5*3,2 $1 730&+ 5*3,2 3'% B% %.*' 06 53*3,2 730&+ 730&+ 6&/ 6'$ 3'% B$ 3'% B% 6&/. 6', 6'2 66% 6&/ 6'$ 6,0 %.*' ,17 &ROG)LUH&RUH ZLWK0$&

8 Freescale Semiconductor, Inc.

• General-Purpose Time r/PWM Module (TPM) –I 2C master interface –I 2C or SPI slave interface – System Integration Module (SIM) – Clock-Generation Module The slave interfaces (either SPI or I2C) operate independently of the CPU subsystem. They can be accessed at any time, includ- ing while the device is in low-power, deep-sleep mode.

3.2 Packaging Information

All pins on the device are utilized and many are multiplexed. The following sections describe the pinout. Users can select from multiple pin functions via the SIM pin mux-control registers.

3.2.1 Package diagrams

Figure 2. Device pinout (top view) and package frame convention

3.2.2 Sensing Direction and Output Response

the standard abbreviations or names for the six different orientation modes: portrait up/down, landscape left/right and back/front. Figure 3. Sensing direction and output response

3.2.3 Pin Functions

The following table summarizes functional options for each pin on this device. Table 3. Pin functions

1. Pin function #1 represents the reset state of the hardware. Pin functions can be changed via the SIM pin, mux-control registe rs in Freescale or user firmware.

1 VDD Digital power supply

2 BKGD/MS RGPIO9 Background-debug / Mode select / RGPIO9

3 RESETB(2)

1. RESETB is an open-drain, bidirectional pin. Reset must be pulled high at startup. After startup, Reset may be asserted to res et the device.

4 SCL0 RGPIO0 SCLK Serial clock for slave I2C / RGPIO0 / Serial clock for slave SPI

5 VSS Digital ground

6 SDA0 RGPIO1 SDI Serial data for slave I2C / RGPIO1 / SPI serial data input

9 RGPIO4 INT RGPIO4 / Interrupt input

10 RESERVED (Connect to V SS) Must be grounded externally

11 RGPIO5 PDB_A INT_O

12 RGPIO6 AN0 TPMCH0 RGPIO6 / ADC Input 0 / TPM Channel 0

13 RGPIO7 AN1 TPMCH1 RGPIO7 / ADC Input 1 / TPM Channel 1

15 RGPIO8 PDB_B RGPIO8 / PDB_B

16 V SSA Analog ground

10 Freescale Semiconductor, Inc.

3.3 Pin Function Descriptions

This section provides a brief description of the various pin functions available on the MMA955xL platform. Ten of the device pins are multiplexed with Rapid GPIO (RGPIO) functions. The “Pin Function #1” column in Table 3 on page 9 lists which function is active when the hardware exits the Reset state. Freescale or user firmware can use the pin mux-control registers in the System Integration Module (SIM) to change pin assignments for each pin after reset. For detailed information about these registers, see the MMA955xL Three-Axis Accelerometer Reference Manual (MMA955xLRM). VDD and VSS: Digital power and ground. VDD is nominally 1.8 V. VDDA and VSSA: Analog power and ground. VDDA is nominally 1.8 V. To optimize performance, the VDDA line can be filtered to remove any digital noise that can be present on the 1.8 V supply. (See Figure 5 and Figure 6 on page 16.) RESETB: The RESETB pin is an open-drain, bidirectional pin with an internal, weak, pullup resistor. At start-up, it is configured as an input pin, but also can be programmed to become bidirectional. Using this feature, the MMA955xL device can reset external devices for any purpose other than power-on reset. Reset must be pulled high at power up to boot to Application code space. If low, it will boot to ROM code. After startup, Reset may be asserted to reset the device. The total external capacitance to ground has to be limited when using RESETB-pin, output-drive capability. For more details, see the “System Integration Module” chapter of the MMA955xL Three-Axis Accelerometer Reference Manual (MMA955xLRM). Slave I2C port: SDA0 and SCL0: These are the slave-I2C data and clock signals, respectively. The MMA955xL device can be controlled via the serial port or via the slave SPI interface. Master I2C: SDA1 and SCL1: These are the master-I2C data and clock signals, respectively. Analog-to-Digital Conversion: AN0, AN1: The on-chip ADC can be used to perform a differential, analog-to-digital conversion based on the voltage present across pins AN0(-) and AN1(+). Conversions for these pins are at the same Output Data Rate (ODR) as the MEMS transducer signals. Input levels are limited to 1.8 V differential. Rapid General Purpose I/O: RGPIO[9:0]: The CPU has a feature called Rapid GPIO (RGPIO). This is a 16-bit, input/output port with single-cycle write, set, clear, and toggle functions available to the CPU. The MMA955xL device brings out the lower 10 bits of that port as pins of the device. At reset, All of the RGPIO pins are configured as input pins, although pin muxing does reassign some pins to non-RGPIO function blocks. Pull-ups are disabled. RGPIO[9] is connected to BKGD/MS. RGPIO[9:6] can be set as interrupt pins for most interrupt sources. RGPIO[1:0] SDA0 and SCL0 are connected at reset. Interrupts: INT: This input pin can be used to wake the CPU from a deep-sleep mode. It can be programmed to trigger on either rising or falling edge, or high or low level. This pin operates as a Level-7 (high-priority) interrupt. Debug/Mode Control: BKGD/MS: At start-up, this pin operates as mode select. If this pin is pulled high during start up, the CPU will boot normally and run code. If this pin is pulled low during start-up, the CPU will boot into active Background-Debug Mode (BDM). In BDM, this pin operates as a bidirectional, single-wire, background-debug port. It can be used by development tools for downloading code into on-chip RAM and flash and to debug that code. There is an internal pullup resistor on this pin. It may be left floating. Timer: PDB_A and PDB_B: These are the two outputs of the programmable delay block. Slave SPI Interface: SCLK, SDI, SDO and SSB: These pins control the slave SPI clock, data in, data out, and slave-select signals, respectively. The MMA955xL platform can be controlled via this serial port or via the slave-I 2C interface. SSB has a spe- cial function at startup that selects the Slave interface mode. Low at startup selects SPI and high selects I2C. INT_O: The slave-port output interrupt pin. This pin can be used to flag the host when a response to a command is available to read on the slave port. This Interrupt pin can only output the COCO bit interrupt. Other than for the MMA9559, use RGPIO6– RGPIO9 for full interrupt capability. TPMCH0 and TPMCH1: The I/O pin associated with 16-bit, TPM channel 0 and 1.

3.4 System Connections

3.4.1 Power Sequencing

An internal circuit powered by VDDA provides the device with a power-on-reset signal. In order for this signal to be properly rec- ognized, it is important that VDD is powered up before or simultaneously with VDDA. The voltage potential between VDD and VDDA must not be allowed to exceed the value specified in Table 7 on page 16. 3. RGPIO3/SDA1/SSB = Low at startup selects SPI. High at startup selects I 2C. This is a function of the application boot code, not of the hardware.

Freescale Semiconductor, Inc. 11

3.4.2 Layout Recommendations

• Provide a low-impedance path from the board power supply to each power pin (V DD and VDDA) on the device and from the board ground to each ground pin (VSS and VSSA).
• Place 0.01 to 0.1 µF capacitors as close as possible to the package supply pins to meet the minimum bypass requirement. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs. VDDA/VSSA ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated printed-circuit traces that connect to the chip V DD and VSS (GND) pins are as short as possible.
• Bypass the power and ground with a capacitor of approxim ately 1 µF and a number of 0.1-µF ceramic capacitors.
• Minimize PCB trace lengths for hi gh-frequency signals. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimi ze noise levels on the VDDA and VSSA pins.
• Use separate power planes for V DD and VDDA and separate ground planes for VSS and VSSA. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuits are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in series with both the VDDA and VSSA traces.
• Physically separate the analog components from noisy digita l components by ground planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces.
• Provide an interface to the BKGD/MS pin if in-circuit debug capability is desired.
• Ensure that resistors R P1 and RP2, in the following figure, match the requirements stated in the I2C standard. For the shown configuration, the value of 4.7 kΩ would be appropriate.

3.4.3 MMA955xL Platform as an Intelligent Slave

I2C pullup resistors, a ferrite bead, and a few bypass capacitors are all that are required to attach this device to a host platform. The basic configurations are shown in the following two figures. In addition, the RGPIO pins can be programmed to generate interrupts to a host platform in response to the occurrence of real-time application events. In this case, the pins should be routed to the external interrupt pins of the CPU. NOTE Immediately after a device reset, the state of pin number 8 (RGPIO3/SDA1/SSB functions) is used to select the slave port inter- face mode. This implies important rules in the way the host controller or, more generally, the complete system should be handling this pin. First of all, whenever a reset occurs on the MMA955xL, the RGPIO3 pin level shall be consistent with the interface mode of op- eration. This is particularly important if this pin is driven from external devices. If the RGPIO3 level does not match the current mode of operation, an alternate mode is selected and communication with the host is lost. If I2C mode is used, a good practice is to tie RGPIO3 to a pull-up resistor so that it defaults to high level. Note that such a con- nection exists when the Master I2C interface is used (SDA1 function for pin 8). When using I2C mode for the slave interface, the RGPIO3 pin plays two roles: RGPIO3 and mode selection. When the MMA955xL is powered on and the mode selection is I2C, the RGPIO3 pin is released as a GPIO pin. The default setting of RGPIO3 is as an output pin and output low. In order to reduce the leakage current on the pull-up resistor, a large resistor value can be used or RGPIO3 can be set as an input pin. When using SPI mode for the slave interface, the situation is more complex as the same pin plays two roles: SSB and mode selection. Moreover, after a SPI read or write operation, the SSB line returns to high level. Consequently, if the host is sending a command to the MMA955xL that induces a subsequent reset, immediately after the write transaction, the host shall force the SSB line to low level so that SPI mode is still selected after reset. Keeping the duration for the SSB line low typically depends on the latency between the write transaction and the execution of the reset command. Such latency can be significant for the MMA9553L pedometer firmware as the Command Interpreter and Scheduler Application are running at 30 Hz, which gives a 33 ms typical latency. The MMA9550L and MMA9551L firmware, on the other hand, operate the Command Interpreter and Sched- uler Applications at 488 Hz, which gives a 2 ms typical latency. The rule obviously applies also when a hardware reset is issued by the host through MMA955xL pin number 3 (RESETB active low). Again the host has to drive the SSB line low prior to release of the hardware reset line to high level, which triggers immediate MMA955xL reset and boot sequence. Keeping the SSB line low for a 1 ms duration (after RESETB is released) is enough for the MMA955xL slave device to reboot into SPI mode.

12 Freescale Semiconductor, Inc. Figure 4. Platform as an I2C slave

Figure 5. Platform as an SPI slave

14 Freescale Semiconductor, Inc.

3.4.4 MMA955xL Platform as a Sensor Hub

• a powerful 32-bit CPU
• a second I 2C bus
• one external analog input These features can all be monitored using the on-chip ADC. The combination of low power consumption and powerful features means that the MMA955xL platform can effectively operate as a power controller for handheld units such as industrial scanners, PDAs, and games. The host platform can put itself to sleep with confidence that the MMA955xL device will issue a wake request should any external event require its attention. The following figure illustrates the MMA955xL device being used in this configuration. Observe how all that is required is a few bypass capacitors, a ferrite bead, and some pullup resistors for the I 2C buses.

Figure 6. Platform as sensor hub

4 Mechanical and Electrical Specifications

information on power considerations, DC/AC electrical characteristics, and AC timing specifications.

4.1 Definitions

sensitivity varies with the direction of cross acceleration and is primarily due to misalignment. calibrated during factory test using a least-squares fit of the raw sensor data. Linearity error The deviation of the sensor output from a least-squares linear fit of the input/output data. Nonlinearity The systematic deviation from the straight line that defines the nominal input/output relationship. data sheet parameters. Pin groups are defined in Section 4.2, “Pin Groups”. set calibration features—improve sensor performance. documented operating conditions.

4.2 Pin Groups

The following pin groups are used throughout the remainder of this section.

4.3 Absolute Maximum Ratings

ditions for extended periods may affect reliability. Table 4. Absolute maximum ratings

16 Freescale Semiconductor, Inc.

4.4 Operating Conditions

4.5 Electrostatic Discharge (ESD) a nd Latch-up Protection Characteristics

4.6 General DC Characteristics

Table 5. Nominal operating conditions Table 6. ESD and latch-up protection characteristics Table 7. DC characteristics(1) 1.All conditions at nominal supply: VDD = VDDA = 1.8 V. 2.Pin groups are defined in “Pin Groups” on page 15.

• Low-drive strength
• High-drive strength VOH Pin Groups 1 and 3 ILOAD = –2 mA ILOAD = –3 mA VDD – 0.5 — — V Output voltage low
• Low-drive strength
• High-drive strength VOL Pin Groups 1 and 3 ILOAD = 2 mA ILOAD = 3 mA —— 0 . 5V Output-low current Max total IOL for all ports IOLT —— 2 4 m A Output-high current Max total I OH for all ports IOHT —— 2 4 m A Input-leakage current |IIN| Pin Group 2 Vin = VDD or VSS —0 . 1 1 µ A Hi-Z (off-state) leakage current |IOZ| Pin Group 3 input resistors disabled Vin = VDD or VSS —0 . 1 1 µ A Pullup resistor RPU when enabled 17.5 52.5 K Ω Power-on-reset voltage VPOR — — 1.50 — V Power-on-reset hysteresis VPOR-hys — — 100 — mV Input-pin capacitance CIN —— 7 — p F Output-pin capacitance COUT —— 7 — p F

4.7 Supply Current Characteristics

4.8 Accelerometer Transducer Mechanical Characteristics

4.9 ADC Characteristics

Table 8. Supply current characteristics(1)

1. All conditions at nominal supply: V DD = VDDA = 1.8V.
2. Total current with the analog section active, 16 bits ADC reso lution selected, MAC unit used and all peripheral clocks enabled.

Table 9. Accelerometer characteristics Table 10. ADC characteristics(1)

18 Freescale Semiconductor, Inc.

4.10 ADC Sample Rates

• 488.28 frames per second (fps)
• 244.14 fps
• 122.07 fps
• 61.04 fps
• 30.52 fps
• 15.26 fps
• 7 . 6 3 f p s
• 3 . 8 1 f p s In addition to the previous list, additional sample rates are available with the MMA9559L device.
• 3906.25 fps (for 10- and 12-bit mode only)
• 1953.13 fps
• 976.56 fps
• 1 . 9 1 f p s
• 0 . 9 5 f p s
• 0 . 4 8 f p s
• 0 . 2 4 f p s Note: The highest rate has a restriction in terms of ADC resolution selection as time available for data conversion is much reduced. Differential nonlinearity DNL — — ±2 — LSB Input leakage IIA —— — ± 2 µ A 1. All conditions at nominal supply: V DD = VDDA = 1.8 V and RES = 14, unless otherwise noted.

4.11 AC Electrical Characteristics

points, as shown in the following figure. Figure 7. Input signal measurement references

• Active state, when a bus or signal is driven and enters a low-impedance state
• Three-stated, when a bus or signal is placed in a high-impedance state
• Data Valid state, when a signal level has reached V OL or VOH
• Data Invalid state, when a signal level is in transition between V OL and VOH

Figure 8. Signal states

4.12 General Timing Control

Table 11. General timing characteristics(1)

1. All conditions at nominal supply: V DD = VDDA = 1.8 V
2. This is the time measured from V DD = VPOR until the internal reset signal is released.
3. In the formulas, T = 1 system clock cycle. In full speed mode, T is nominally 125 ns. In slow speed mode, T is nominally 16 μs.

Note: The midpoint is VIL + (VIH – VIL)/2.

20 Freescale Semiconductor, Inc.

4.13 I 2C Timing

includes a master/slave I2C module that should be used only during CPU run mode (ΦD). Figure 9. I2C standard and fast-mode timing

4.13.1 Slave I 2C

4.13.2 Master I 2C Timing

across frames when a portion of time is spent in low speed mode. Table 12. I2C Speed Ranges

1. The maximum t HD; DAT must be at least a transmission time less than tVD;DAT or tVD;ACK. For details, see the I2C standard.
2. Timing met with IFE = 0, DS = 1, and SE = 1. See the “Port Controls” chapter in the MMA955xL Three-Axis Accelerometer Reference Manual

Table 13. Master I2C timing

1. The master mode I 2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a neg-

ative hold time can result, depending on the edge rates of the SDA and SCL lines.

1. The maximum t HD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
2. Setup time in slave-transmitter mode is one IPBus clock period, if the TX FIFO is empty.
3. A fast-mode I 2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This will automat-

4.14 Slave SPI Timing

Figure 10. SPI slave timing Table 14. Slave SPI timing

1 SCLK period tSCLK 4— t CYCH

4 Clock (SCLK) high or low time tWSCLK 200 — ns

5 Data-setup time (inputs) tSU 15 — ns

6 Data-hold time (inputs) tHI 25 — ns

7 Access time ta —2 5n s

8 SDO-disable time tdis —2 5n s

9 Data valid (after SCLK edge) tv —2 5n s

10 Data-hold time (outputs) tHO 0— n s

1. Not defined but normally MSB of character just received.

22 Freescale Semiconductor, Inc.

4.15 Flash Parameters

programming of that memory. Chip supply voltage of 1.8 V is sufficient for the flash programming voltage. The lower portion of the flash memory is occupied by Freescale factory firmware and is protected so that a user cannot erase it. block of memory that can be programmed is 128 bytes and the block must start at a 128-byte boundary. Flash programming blocks must start on a 4-byte boundary and cannot cross a 128-byte page boundary. Figure 11. Flash memory map for devices Table 15. Flash parameters

5 Package Information

5.1 Footprint and pa ttern information

Figure 12. Package bottom view Figure 13. Package overlaid on PCB footprint diagram (top view)

24 Freescale Semiconductor, Inc. Figure 14. Recommended PCB footprint

5.2 Marking

5.3 Tape and reel information

Figure 15. Tape dimensions The devices are oriented on the tape as shown in Figure 16. The dot marked on each device indicates pin 1. Figure 16. Tape and reel orientation

26 Freescale Semiconductor, Inc.

6 Revision History

date Description of changes 0 06/2011 Initial release of document. 1 10/2011 • Added the MMA9559L device.

• Added a features table and a package land diagram figure.
• Modified block diagram
• Inserted flash memory map figure 2 5/2013 • Removed MMA9550LT and MMA9551LT from Ordering Information table
• Added Pedometer to MMA9553LR throughout
• Added list of links to Related Documentation
• User RAM available for MMA9553 was 200 bytes
• Removed mobile phones from Typical Applications
• Removed Dead reckoning from Typical Applications/Fleet monitoring, tracking
• Added a pull-up resistor to Pin 2 of Figures 7, 8, and 9
• Removed the Conditions column from Table 5 3 9/2013 • Added Marking, Tape and reel, and Package dimensions
• Moved Footprint and pattern information from Package diagrams to Package Information 3.1 5/2015 • Changed part number from MMA955xL to MMA9550L, MMA9551L, MMA9553L, and MMA9559L
• Table 2, MMA9553L, User flash available changed from 1.5 KB to 1.0 KB
• Table 2, MMA9553L, changed 304 bytes to 420 bytes in user RAM available
• Section 1, Added sentence stating that MMA9555L data and functions are in a separate data sheet
• Figures 4, 5, and 6, Changed SBB to SSB
• Section 3.4.3, added note

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