MMA8653FC

MMA8653FC FREESCALE | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Block Diagram and Pin Descriptions
• 1.1 Block diagram
• 1.2 Pin descriptions
• 1.3 Orientation definitions
• 1.4 Recommended application diagram
• 2 Mechanical and Electrical Specifications
• 2.1 Absolute maximum ratings
• 2.2 Mechanical characteristics
• 2.3 Electrical characteristics
• 2.4 I2C interface characteristics
• 3 Terminology
• 3.1 Sensitivity
• 3.2 Zero-g offset
• 3.3 Self-Test
• 4 Modes of Operation
• 5 Functionality
• 5.1 Device calibration
• 5.4 Auto-WAKE/SLEEP mode
• 5.5 Freefall detection
• 5.6 Orientation detection
• 5.7 Interrupt register configurations
• 5.8 Serial I2C interface
• 6 Register Descriptions
• 6.1 Register address map
• 6.2 Register bit map
• 6.3 Data registers
• 6.4 System Registers
• 6.5 Portrait/Landscape Embedded Function Registers
• 6.6 Motion and Freefall Embedded Function Registers
• 6.7 Auto-WAKE/SLEEP Detectio n
• 6.8 Control Registers
• 6.9 Data calibration registers
• 7 Mounting Guidelines
• 7.1 Overview of soldering considerations
• 7.2 Halogen content
• 7.3 PCB mounting/soldering recommendations
• 8 Tape and Reel
• 8.1 Tape dimensions
• 8.2 Device orientation
• 9 Package Dimensions
• 10 Revision History

Features

• 1.95V to 3.6V supply voltage
• 1.62V to 3.6V digital interface voltage
• ±2g, ±4g, and ±8g dynamically selectable full-scale ranges
• Output Data Rates (ODR) from 1.56 Hz to 800 Hz
• 10-bit digital output
• I 2C digital output interface with programmable interrupts
• One embedded channel of configurable motion detection (Freefall)
• Orientation (Portrait/Landscape) detection with default hysteresis
• Automatic ODR change triggered by the Auto-Wake / Sleep state change
• S e l f - T e s t Typical Applications
• eCompass applications tilt compensation
• Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/ Front position identification)
• Notebook, eReader, and Laptop Tumble and Freefall Detection
• Real-time orientation detection (virtual reality and gaming 3D user position feedback)
• Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)
• Motion detection for portab le product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)
• Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)
• User interface (menu scrolling by orientation change)

ORDERING INFORMATION

Part Number Temperature Range Package Description Shipping MMA8653FCR1 -40°C to +85°C DFN-10 Tape and Reel MMA8653FC Top View Pin Connections VDD SCL INT1 BYP INT2 SDA GND GND VDDIO GND 10-PIN DFN 2 mm x 2 mm x 1 mm CASE 2162 Top and Bottom View MMA8653FC MMA8653FC

2 Freescale Semiconductor, Inc. Feature comparison of the MMA8653FC devices Feature List MMA8652FC MMA8653FC Digital Resolution (Bits) 12 10 Digital Sensitivity in 2g mode (Counts/g) 1024 256 Low-Power Mode Yes Yes Auto-WAKE Yes Yes Auto-SLEEP Yes Yes 32-Level FIFO Yes No Low-Pass Filter Yes Yes High-Pass Filter Yes No Transient Detection with High-Pass Filter Yes No Orientation Detection Portrait to Landscape = 30°, Landscape to Portrait = 60°, and Fixed 45° Threshold Yes Yes Programmable Orientation Detection Yes No Data-Ready Interrupt Yes Yes Single-Tap Interrupt Yes No Double-Tap Interrupt Yes No Directional Tap Interrupt Yes No Freefall/Motion Interrupt Yes Yes Transient Interrupt with Direction Yes No

4 Freescale Semiconductor, Inc.

1 Block Diagram and Pin Descriptions

1.1 Block diagram

Figure 1. MMA8653 block diagram

1.2 Pin descriptions

Figure 2. Direction of the detectable accelerations

1.3 Orientation definitions

orientation detection and are described in detail in the register setting section. Figure 3. Landscape/Portrait orientation

10 VDD

6 Freescale Semiconductor, Inc.

1.4 Recommended application diagram

Figure 4. Application diagram Table 1. Pin descriptions

1 VDD Power supply

7-bit I2C device address is 0x1D. 2C connections are open drain, and therefore usually require a pullup resistor.

3 INT1 Interrupt 1 The interrupt source and pin settings are user-programmable through the I2C

4 BYP Internal regulator output

5 INT2 Interrupt 2 See INT1.

6 GND Ground

7 GND Ground

8 VDDIO Digital Interface Power supply

9 GND Ground

10 SDA I 2C Serial Data See SCL. are only needed for open-drain.

2 Mechanical and Electr ical Specifications

2.1 Absolute maximum ratings

rating conditions for extended periods may affect device reliability. Table 2. Maximum ratings Table 3. ESD and latch-up protection characteristics cause the part to otherwise fail. This part is ESD-sensitive. Improper handling can cause perman ent damage to the part.

8 Freescale Semiconductor, Inc.

2.2 Mechanical characteristics

Table 4. Mechanical characteristics at VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted

1. Post-board mount offset specifications are based on an 8-layer PCB, relative to 25°C.
2. Self-Test is one direction only.

2 MHz Clock -20 +20 %

2.3 Electrical characteristics

Table 5. Electrical characteristics at VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted

1. There is no requirement for power supply sequencing. The VDDIO input voltage can be higher than the VDD input voltage.

10 Freescale Semiconductor, Inc.

2.4 I 2C interface characteristics

Figure 5. I2C slave timing

1. Note that the first sample is typically not very precise; only the second or third or fourth sample (depending on ODR/MODS settings) has full

Table 6. I2C slave timing values(1)

1. All values referred to VIH (min) and VIL (max) levels.
2. This device does not stretch the LOW period (t LOW) of the SCL signal.
3. t VD;DAT = time for Data signal from SCL LOW to SDA output.
4. t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
5. C b = total capacitance of one bus line in pF.

Freescale Semiconductor, Inc. 11

3 Terminology

3.1 Sensitivity

The sensitivity is represented in counts/g.

• In 2g mode, sensitivity = 256 counts/g.
• In 4g mode, sensitivity = 128 counts/g.
• In 8g mode, sensit ivity = 64 counts/g.

3.2 Zero-g offset

Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0g in X-axis and 0g in Y -axis, whereas the Z-axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT Registers 0x00, data expressed as a 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress on the MEMS sensor, and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.

3.3 Self-Test

Self-T est can be used to verify the transducer and signal chain functionality without the need to apply external mechanical stimulus. When Self-T est is activated:

• An electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case, the sensor outputs w ill exhibit a change in their DC levels which, are related to the selected full scale through the device sensitivity .
• The device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force.

12 Freescale Semiconductor, Inc.

4 Modes of Operation

Figure 6. Operating modes for MMA8653FC how to transition between these modes, see Section 5, “Functionality”. Table 7. Operating modes

• The device is powered off.
• All analog and digital blocks are shutdown.
• I 2C bus inhibited. STANDBY I2C communication with MMA8653FC is possible ON VDDIO = High VDD = High ACTIVE bit is cleared
• Only digital blocks are enabled.
• Analog subsystem is disabled.
• Internal clocks disabled. ACTIVE (WAKE/SLEEP) I 2C communication with MMA8653FC is possible ON VDDIO = High VDD = High ACTIVE bit is set All blocks are enabled (digital, analog). SLEEP WAKESTANDBYOFF ACTIVE

5 Functionality

used to detect events and notify an external microprocessor over interrupt lines.

• 8-bit or 10-bit data
• Four different oversampling options that allow for the optimum resolution vs. current consumption trade-off to be made for a given application
• Low power and au to-WAKE/SLEEP modes for reducing current consumption
• Freefall/Motion detection (1 channel)
• Single default angle for portrait landscape detecti on algorithm, for addressing screen orientation
• Two independent interrupt out put pins that are programmable among 4 interrupt sources (Data Ready, Freefall/Motion, Orientation, Auto-WAKE) All functionality is available in 2g, 4g or 8g dynamic measurement ranges. There are many configuration settings for enabling all of the different functions. Separate application notes are available to help configure the device for each embedded functionality .

5.1 Device calibration

changing the default offset values. The user offset adjustments are stored in 3 volatile 8-bit registers (OFF_X, OFF_Y, OFF_Z). be set. When the F_READ bit is cleared, the fast read mode is disabled.

• When the full-scale is set to 2g, the measurement range is -2g to +1.996g, and each count corresponds to (1/256)g (3.8mg) at 10-bit resolution.
• When the full-scale is set to 4g, the measurement range is -4g to +3.992g, and each count corresponds to (1/128)g
• (7.8mg) at 10-bit resolution.
• When the full-scale is set to 8g, the measurement range is -8g to +7.984g, and each count corresponds to (1/64)g (15.6 mg) at 10-bit resolution.
• If only the 8-bit results are used, then the resolution is reduced by a factor of 16. For more information about the data manipulation between data formats and modes, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. There is a device driver available that can be used with the Sensor T oolbox demo board (LFSTBEB865xFC) with this application note.

Table 8. Accelerometer 10-bit output data

14 Freescale Semiconductor, Inc. schemes of the data can activated when MODS = 10 in Register 0x2B, which will improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz. reduced. When MODS = 11, the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz.

5.4 Auto-WAKE/SLEEP mode

mode (lower current) when the device does not require higher sampling rates.

• Auto-WAKE refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This may also interrupt the processor to transition from a SLEEP mode to a higher power mode.
• SLEEP mode occurs after the accelerometer has not detected an interrupt for longer than the user-definable timeout period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode, to save on current during this period of inactivity . The interrupts that can WAKE the device from SLEEP are the following: Orientation detection, and Freefall/Motion detection. The interrupts that can keep the device from falling asleep are the same interrupts that can wake the device.

5.5 Freefall detection

MMA8653FC has a flexible interrupt architecture for detecting either a Freefall or a Motion.

• Freefall can be enabled where the set threshold must be less than the configured threshold.
• Motion can be enabled where the set threshold must be greater than the configured threshold. 8-bit Data Range ±2g (15.6 mg) Range ±4g (31.25 mg) Range ±8g (62.5 mg) 0111 1111 1.984g +3.968g +7.937g 0111 1110 1.968g +3.937g +7.875g …… … … 0000 0001 +0.015g +0.031g +0.062g 0000 0000 0.000g 0.000g 0.000g 1111 1111 -0.015g -0.031g -0.062g …… … … 1000 0001 -1.984g -3.968g -7.937g 1000 0000 -2.000g -4.000g -8.000g

Table 9. Accelerometer 8-bit output data Table 8. Accelerometer 10-bit output data (Continued)

configuration does not use the high-pass filter. MMA8653FC has an interrupt architecture for detecting a Freefall.

• Freefall can be enabled where the set threshold must be less than the configured threshold. The freefall configuration does not use a high-pass filter.

5.5.1 Freefall detection

5.6 Orientation detection

The MMA8653FC orientation detection algorithm confirms the reliability of the function with a configurable Z-lockout angle. the “Z-lockout angle”. The device operates at a fixed 29° angle from the flat position, with an accuracy of ± 2°.

• Figure 7 shows the definition of the orientations (PU, PD, LL, LR, BACK, FRONT).
• Figure 8 shows the definitions of the trip angles, going from landscape to portrait and then from portrait to landscape.

Figure 7. Landscape/Portrait orientation

16 Freescale Semiconductor, Inc. Figure 8. Landscape to Portrait transition Figure 9 shows the Z-angle lockout region. Figure 9. Z-Tilt angle lockout transition

5.7 Interrupt register configurations

There are 4 configurable interrupts in the MMA8653FC: Data Ready , Motion/Freefall, Orientation, and Auto-SLEEP events. Figure 10. System interrupt generation flat. This is the only setting available. routed to one of two interrupt pins.

• The MMA8653FC features an interrupt signal that indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device.
• The MMA8653FC may also be configured to generate other interrupt signals accordingly, to the programmable embedded functions of the device for Motion, Freefall, and Orientation.

5.8 Serial I 2C interface

I2C serial interface (Table 10, “Serial Interface pins").

• To enable the I 2C interface, VDDIO line must be tied high (i.e., to the interface supply voltage). If VDD is not present and VDDIO is present, then the MMA8653FC is in OFF mode—and communications on the I 2C interface are ignored.
• T h e I 2C interface may be used for communications between other I2C devices; the MMA8653FC does not affect the I2C bus. The I2C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards (Table 6, “I2C slave timing values"). I2C operation: 1. The transaction on the bus is started through a start condition (ST ART) signal. A ST ART condition is defined as a high-to- low transition on the data line while the SCL line is held high. After ST ART has been transmitted by the Master, the bus is considered busy . 2. The next byte of data transmitted after ST ART contains the slave address in the first 7 bits, and the 8th bit tells whether the Master is receiving data from the slave or is transmitting data to the slave. 3. After a start condition and when an address is sent, each device in the system compares the first 7 bits with its address. If the device’s address matches the sent address, then the device considers itself addressed by the Master. 4. The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it remains stable low during the high period of the acknowledge clock period. 5. A Master may also issue a repeated ST ART during a data transfer. The MMA8653FC expects repeated ST ART s to be used to randomly read from specific registers. 6. A low-to-high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer is always terminated by a STOP. The MMA8653FC's standard slave address is 001 1 101 or 0x01D. The slave addresses are factory programmed; alternate addresses are available upon request.

5.8.1 Single byte read

1. The transmission of an 8-bit command begins on the falling edge of SCL. After the 8 clock cycles are used to send the

timing (I2C)" shows the timing diagram for the accelerometer 8-bit I2C read operation.

1. The Master (or MCU) transmits a start condition (ST) to t he MMA8653FC [slave address (0x1D), with the R/W bit set to

“0” for a write], and the MMA8653FC sends an acknowledgement. Table 10. Serial Interface pins

• SDA is a bidirectional line used for sending and receiving the data to/from the interface.
• External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus is free, both SCL and SDA lines are high. SDA I 2C Serial Data

Table 11. I2C Device address sequence

18 Freescale Semiconductor, Inc.

1. Next the Master (or MCU) transmits the address of the register to read, and the MMA8653FC sends an
2. The Master (or MCU) transmits a repeated start conditio n (SR) and then addresses the MMA8653FC (0x1D), with the R/

W bit set to “1” for a read from the previously selected register.

1. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge

(NAK) the transmitted data, but transmits a stop condition to end the data transfer. Figure 11. Single Byte Read timing (I2C) For the following subsections, use the following legend.

5.8.2 Multiple byte read

1. When performing a multi-byte read or “burst read”, t he MMA8653FC automatically increments the received register

address commands after a read command is received.

1. After following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each
2. Until a no acknowledge (NAK) occurs from the Master,
3. Followed by a stop condition (SP), which signals the end of transmission.

Figure 12. Multiple Byte Read timing (I2C)

5.8.3 Single byte write

1. T o start a write command, the Master transmits a start condition (ST) to the MMA8653FC, slave address ($1D) with the
2. The MMA8653FC sends an acknowledgement.
3. Next the Master (MCU) transmits the address of the register to write to, and the MMA8653FC sends an
4. Then the Master (or MCU) transmits the 8-bit data to wr ite to the designated register, and the MMA8653FC sends an

condition (SP) to the data transfer. The data sent to the MMA8653FC is now stored in the appropriate register.

Figure 13. Single Byte Write timing (I2C)

5.8.4 Multiple byte write

1. After a write command is received, the MMA8653FC automatically increments the received register address
2. Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers

after each MMA8653FC acknowledgment (ACK) is received. Figure 14. Multiple Byte Write timing (I2C)

20 Freescale Semiconductor, Inc.

6 Register Descriptions

6.1 Register address map

Note: Auto-increment addresses that are not a simple increment are highlighted in bold. The auto-increment addressing is only enabled when device registers are read using I2C burst read mode. The internally stored auto-increment address is cleared whenever an I2C STOP condition is detected. Table 12. MMA8653FC Register Address Map

1. The register data is only valid in ACTIVE mode.
2. Register contents are reset when transition from STANDBY to ACTIVE mode occurs.

OUT_X_MSB(1) R 0x01 0x02 0x03 Output — [7:0] are 8 MSBs of 10-bit sample. Reserved R 0x07–0x0A — 00000000 0x00 Reserved. Read return 0x00.

1. Register contents are preserved when transit ion from ACTIVE to STANDBY mode occurs.
2. Modification of this register’s content can only occur when device is in STANDBY mode, except CTRL_REG1 ACTIVE bit and CTRL_REG2 RST bit.

Reserved R 0x0F — 00000000 0x00 Reserved. Read return 0x00. PL_CFG(3)(4) R/W 0x11 0x12 10000000 0x80 Landscape/Portrait configuration. Reserved R 0x19–0x28 — 00000000 0x00 Reserved. Read return 0x00. CTRL_REG1(3)(4) R/W 0x2A 0x2B 00000000 0x00 Data Rates, ACTIVE Mode.

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6.2 Register bit map

Note: Bits showing “—” can read as either 0 or 1, and these bits have no definition. Reg Field Definition Typ e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR

01 OUT_X_MSB 10-bit X Data R XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2

02 OUT_X_LSB 10-bit X Data R XD1 XD0 0 0 0 0 0 0

03 OUT_Y_MSB 10-bit Y Data R YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2

04 OUT_Y_LSB 10-bit Y Data R YD1 YD0 0 0 0 0 0 0

05 OUT_Z_MSB 10-bit Z Data R ZD9 ZD8 ZD7 ZD6 ZD5 ZD4 ZD3 ZD2

06 OUT_Z_LSB 10-bit Z Data R ZD1 ZD0 0 0 0 0 0 0

07– 0A Reserved — R 0 0 0 0 0 0 0 0 0B SYSMOD System Mode R 0 0 0 0 0 0 SYSMOD1 SYSMOD0 0C INT_SOURCE Interrupt Status R SRC_ASLP 0 0 SRC_LNDPRT 0 SRC_FF_MT 0 SRC_DRDY 0D WHO_AM_I ID Register R 0 1 0 1 1 0 1 0 0E XYZ_DATA_CFG Data Config R/ W 00 0 0 0 0F S1 F S0

10 PL_STATUS Portrait Landscape

Status R NEWLP LO 0 0 0 LAPO[1] LAPO[0] BAFRO

11 PL_CFG Portrait Landscape

W DBCNTM PL_EN 0 0 0 0 0 0

12 PL_COUNT Portrait Landscape

W DBNCE[7] DBNCE[6] DBNCE[5] DBNCE[4] DBNCE[3] DBNCE[2] DBNCE[1] DBNCE[0]

13 PL_BF_ZCOMP Portrait Landscape

Back/Front Z Comp R0 1 0 0 0 1 0 0

14 PL_THS_REG Portrait Landscape

Threshold R1 0 0 0 0 1 0 0

15 FF_MT_CFG Freefall/Motion Config R/

W ELE OAE ZEFE YEFE XEFE 0 0 0

16 FF_MT_SRC Freefall/Motion Status R EA 0 ZHE ZHP YHE YHP XHE XHP

17 FF_MT_THS Freefall/Motion Threshold R/

W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0

18 FF_MT_COUNT Freefall/Motion

19–

29 ASLP_Count Counter setting for

2A CTRL_REG1 Control Reg1 R/ W ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 0 F_READ ACTIVE 2B CTRL_REG2 Control Reg2 R/ W ST RST — SMODS1 SMODS0 SLPE MODS1 MODS0 2C CTRL_REG3 Control Reg3 R/ W — — WAKE_LNDPRT — WAKE_FF_MT 0 IPOL PP_OD 2D CTRL_REG4 Control Reg4 R/ W INT_EN_ASLP — — INT_EN_LNDPRT — INT_EN_FF_MT 0 INT_EN_DRDY 2E CTRL_REG5 Control Reg5 R/ W INT_CFG_ASLP — — INT_CFG _LNDPRT — INT_CFG_FF_MT 0 INT_CFG_DRD Y 2F OFF_X X 8-bit offset R/ W D7 D6 D5 D4 D3 D2 D1 D0

30 OFF_Y Y 8-bit offset R/

31 OFF_Z Z 8-bit offset R/

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6.3 Data registers

This register contains the X, Y, Z data overwrite and data ready flags. Figure 15. 0x00: STATUS, Data Status Register (Read Only) Table 13. STATUS register bits occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been overwritten. sample. When this occurs the previous sample is overwritten. ZOW is cleared anytime OUT_Z_MSB register is read. sample. When this occurs the previous sample is overwritten. YOW is cleared anytime OUT_Y_MSB register is read. sample. When this occurs the previous sample is overwritten. XOW is cleared any time OUT_X_MSB register is read. the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the channels are read.

24 Freescale Semiconductor, Inc.

6.4 System registers

should use this register to synchronize the application with the device operating mode transitions. Figure 22. 0x0B: SYSMOD, System Mode Register (Read Only) Table 14. SYSMOD register System Mode. Default value: 00.

appropriate interrupt source register. Figure 23. 0x0C: INT_SOURCE, System Interrupt Status Register (Read Only) Table 15. INT_SOURCE register Auto-SLEEP/WAKE interrupt status bit. Default value: 0.

• Logic ‘1’ indicates that an interrupt event that can cause a WAKE to SLEEP or SLEEP to WAKE system mode transition has occurred.
• Logic ‘0’ indicates that no WAKE to SLEEP or SLEEP to WAKE system mode transition interrupt event has occurred. WAKE to SLEEP transition occurs when no interrupt occurs for a time period that exceeds the user specified limit (ASLP_COUNT). This causes the system to transition to a user specified low ODR setting. SLEEP to WAKE transition occurs when the user specified interrupt event has woken the system; thus causing the system to transition to a user specified high ODR setting.
• Reading the SYSMOD register clears the SRC_ASLP bit. SRC_LNDPRT Portrait/Landscape Orientation interrupt status bit. Default value: 0. Logic ‘1’ indicates that an interrupt was generated due to a change in the device orientation status. Logic ‘0’ indicates that no change in orientation status was detected.
• This bit is asserted whenever “NEWLP” bit in the PL_STATUS is asserted and the interrupt has been enabled.
• This bit is cleared by reading the PL_STATUS register. SRC_FF_MT Freefall/Motion interrupt status bit. Default value: 0. Logic ‘1’ indicates that the Freefall/Motion function interrupt is active. Logic ‘0’ indicates that no Freefall or Motion event was detected.
• This bit is asserted whenever “EA” bit in the FF_MT_SRC register is asserted and the FF_MT interrupt has been enabled.
• This bit is cleared by reading the FF_MT_SRC register. SRC_DRDY Data Ready Interrupt bit status. Default value: 0. Logic ‘1’ indicates that the X, Y , Z data ready interrupt is active indicating the presence of new data and/or data overrun. Otherwise if it is a logic ‘0’ the X, Y , Z interrupt is not active.
• This bit is asserted when the ZYXOW and/or ZYXDR is set and the interrupt has been enabled.
• This bit is cleared by reading the X, Y, and Z data. It is not cleared by simply reading the Status Register (0x00).

26 Freescale Semiconductor, Inc. factory for custom alternate values. Figure 24. 0x0D: WHO_AM_I, Device ID Register (Read Only)

The XYZ_DATA_CFG register sets the dynamic range. Figure 25. 0x0E: XYZ_DATA_CFG Register (Read/Write) The default full scale value range is 2g. Table 16. XYZ_DATA_CFG register FS[1:0] Output buffer data format full scale. Default value: 00 (2g). Table 17. Full Scale Range

28 Freescale Semiconductor, Inc.

6.5 Portrait/Landscape embedded function registers

Figure 26. 0x10: PL_STATUS, Portrait/Landscape Status Register (Read Only)

• NEWLP is set to 1 after the first orientation detection afte r a STANDBY to ACTIVE transition, and whenever a change in LO, BAFRO, or LAPO occurs.
• NEWLP bit is cleared anytime PL_STATUS register is read.
• The Orientation mechanism state change is limited to a maximum 1.25g.
• LAPO BAFRO and LO continue to change when NEWLP is set.
• The current position is locked if the absolute value of the acce leration experienced on any of the three axes is greater than 1.25g. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NEWLP LO 0 0 0 LAPO[1] LAPO[0] BAFRO

Table 18. PL_STATUS register Portrait/Landscape status change flag. Default value: 0. Z-Tilt Angle Lockout. Default value: 0. 1: Z-Tilt lockout trip angle has been exceeded. Lockout has been detected.

1. The default power up state is BAFRO = 0, LAPO = 0, and LO = 0.

This register enables the Portrait/Landscape function and sets the behavior of the debounce counter. Figure 27. 0x11: PL_CFG, Portrait/Landscape Configuration Register (Read/Write) Table 19. PL_CFG register 1: Clears counter whenever condition of interest is no longer valid.

30 Freescale Semiconductor, Inc. versa resets the internal Landscape/Portrait debounce counter. step value for all sample rates and all Oversampling modes. Figure 28. 0x12: PL_COUNT, Portrait/Landscape Debounce Counter Register (Read/Write) Table 20. PL_COUNT register DBCNE[7:0] Debounce Count value. Default value: 0000_0000. Table 21. PL_COUNT Relationship with the ODR

power up. The Back to Front trip angle is fixed to ±75°. Figure 29. 0x13: PL_BF_ZCOMP, Back/Front and Z Compensation Register (Read Only) Table 22. PL_BF_ZCOMP register

32 Freescale Semiconductor, Inc. to Landscape and Landscape to Portrait. This register includes a value for the hysteresis. Figure 30. 0x14: PL_THS_REG, Portrait/Landscape Threshold and Hysteresis Register (Read Only) Table 23. PL_THS_REG register

Freescale Semiconductor, Inc. 33

6.6 Motion and Freefall embe dded function registers

The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15: FF_MTG_CFG, bit 6). The freefall/motion detection block can be disabled by setting all three bits ZEFE, YEFE, and XEFE to zero. Depending on the register bits ELE (0x15: FF_MTG_CFG, bit 7) and OAE (0x15: FF_MTG_CFG, bit 6), each of the freefall and motion detection block can operate in four different modes:

6.6.1 Motion and freefall mode

6.6.1.1 Mode 1: Freefall Detection with ELE = 0, OAE = 0

In this mode, the EA bit (0x16: FF_MTG_SRC, bit 7) indicates a freefall event after the debounce counter is complete. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. Once the EA bit is set, and DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. This is because the counter is in decrement mode. If DBCNTM = 1, the EA bit is cleared as soon as the freefall condition disappears, and will not be set again before the delay specified by FF_MT_COUNT has passed. Reading the FF_MT_SRC register does not clear the EA bit. The event flags (0x16) ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e. high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set.

6.6.1.2 Mode 2: Freefall Detection with ELE = 1, OAE = 0

In this mode, the EA event bit indicates a freefall event after the debounce counter . Once the debounce counter reaches the time value for the set threshold, the EA bit is set, and remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, the EA bit and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. While EA = 0, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP are latched when the EA event bit is set. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP will start changing only after the FF_MT_SRC register has been read.

6.6.1.3 Mode 3: Motion Detection with ELE = 0, OAE = 1

In this mode, the EA bit indicates a motion event after the debounce counter time is reached. The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the EA bit is set, and DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. If DBCNTM = 1, the EA bit is cleared as soon as the motion high g condition disappears. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Reading the FF_MT_SRC does not clear any flags, nor is the debounce counter reset.

6.6.1.4 Mode 4: Motion Detection with ELE = 1, OAE = 1

In this mode, the EA bit indicates a motion event after debouncing. The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the debounce counter reaches the threshold, the EA bit is set, and remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, all register bits are cleared and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT. While the bit EA is zero, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. When the EA bit is set, these bits keep their current value until the FF_MT_SRC register is read.

INT_CFG_FF_MT register bits to generate the freefall/motion interrupts. threshold value defined in the FF_MT_THS register. Figure 33. 0x16: FF_MT_SRC, Freefall and Motion Source Status Register (Read Only) Table 25. FF_MT_SRC register Event Active Flag. Default value: 0. 1: One or more event flag has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. Z Motion Flag. Default value: 0. Z Motion Polarity Flag. Default value: 0. Y Motion Flag. Default value: 0.

36 Freescale Semiconductor, Inc. FF_MT_THS is the threshold register used to detect freefall motion events.

• The unsigned 7-bit FF_MT_THS threshold register holds the threshold for the freefall detection where the magnitude of the X and Y and Z acceleration values is lower than the threshold value.
• Conversely, the FF_MT_THS also holds the threshold for the motion detection where the magnitude of the X or Y or Z acceleration value is higher than the threshold value.

Figure 34. 0x17: FF_MT_THS, Freefall and Motion Threshold Register (Read/Write) The threshold resolution is 0.063g/LSB and the threshold register has a range of 0 to 127 counts. The maximum range is to 8g. Note that even when the full scale value is set to 2g or 4g the motion detects up to 8g. DBCNTM bit configures the way in which the debounce counter is reset when the inertial event of interest is momentarily not true.

• When DBCNTM bit is ‘1’, the debounce counter is cleared to 0 whenever the inertial event of interest is no longer true as shown in Figure 36 "DBCNTM bit function", (b).
• While the DBCNTM bit is set to logic ‘0’, the debounce counter is decremented by 1 whenever the inertial event of interest is no longer true (Figure 36 "DBCNTM bit function", (c)) until the debounce counter reaches 0 or the inertial event of interest becomes active. Decrementing the debounce counter acts as a median enabling the system to filter out irregular spurious events which might impede the detection of inertial events. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 26. FF_MT_THS Bit Descriptions DBCNTM Debounce counter mode selection. Default value: 0. 0: increments or decrements debounce, 1: increments or clears counter. THS[7:1] Freefall /Motion Threshold: Default value: 000_0000.

This register sets the number of debounce sample counts for the event trigger. Figure 35. 0x18 FF_MT_COUNT, Debounce Register (Read/Write) selected for the freefall, motion event. ODR chosen and the Oversampling mode as shown in Table 28, “FF_MT_COUNT Relationship with the ODR". Table 27. FF_MT_COUNT register Table 28. FF_MT_COUNT Relationship with the ODR

38 Freescale Semiconductor, Inc. Figure 36. DBCNTM bit function

6.7 Auto-WAKE/SLEEP Detection

to trigger the “return to SLEEP” event. Figure 37. 0x29: ASLP_COUNT Auto-WAKE/SLEEP Detection Register (Read/Write) depend on the ODR chosen as shown in Table 30, “ASLP_COUNT Relationship with ODR". selected for WAKE from SLEEP will WAKE the device. MMA8653FC has 2 functions that can be used to keep the sensor from falling asleep namely , Orientation, and Motion/Freefall. Freefall. The Auto-WAKE/SLEEP interrupt does not affect the WAKE/SLEEP , nor does the data ready interrupt. is enabled, transitioning from ACTIVE mode to Auto-SLEEP mode and vice versa generates an interrupt. Table 29. ASLP_COUNT register D[7:0] Duration value. Default value: 0000_0000. Table 30. ASLP_COUNT Relationship with ODR

200 Hz 0 to 81s 5 ms 320 ms

100 Hz 0 to 81s 10 ms 320 ms

50 Hz 0 to 81s 20 ms 320 ms

12.5 Hz 0 to 81s 80 ms 320 ms

6.25 Hz 0 to 81s 160 ms 320 ms

1.56 Hz 0 to 162s 640 ms 640 ms

Table 31. SLEEP/WAKE Mode Gates and Triggers

40 Freescale Semiconductor, Inc.

6.8 Control registers

of the fields within CTRL_REG1 (0x2A). Figure 38. 0x2A: CTRL_REG1, System Control 1 Register (Read/Write) Table 32. CTRL_REG1 register ASLP_RATE[1:0] Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode. Default value: 00. See Table 33, “SLEEP Mode Rates". DR[2:0] Data rate selection. Default value: 000. See Table 34, “System Output Data Rate Selection". Fast Read mode: Data format limited to single Byte Default value: 0. STANDBY/ACTIVE selection. Default value: 00. Table 33. SLEEP Mode Rates by the data rate set by the ASLP_RATE field. Table 34. System Output Data Rate Selection

ACTIVE bit selects between STANDBY mode and ACTIVE mode. Table 35. Full Scale Selection

0 STANDBY (default)

42 Freescale Semiconductor, Inc. WAKE mode power scheme selection. Figure 39. 0x2B: CTRL_REG2, System Control 2 Register (Read/Write) resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode. The I2C communication system is reset to avoid accidental corrupted data access. At the end of the boot process the RST bit is de-asserted to 0. Reading this bit will return a value of zero. Oversampling modes are available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0]. Table 36. CTRL_REG2 register Self-Test Enable. Default value: 0. reset. The reset mechanism can be enabled in STANDBY and ACTIVE mode. Software Reset. Default value: 0. SLEEP mode power scheme selection. Default value: 00. Auto-SLEEP enable. Default value: 0. WAKE mode power scheme selection. Default value: 00. Table 37. MODS Oversampling Modes

00 N o r m a l

Table 38. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR

1.56 Hz TBD 128 TBD 32 TBD 1024 TBD 16

6.25 Hz TBD 32 TBD 8 TBD 256 TBD 4

12.5 Hz TBD 16 TBD 4 TBD 128 TBD 2

50 Hz TBD 4 TBD 4 TBD 32 TBD 2

Note: TBD current values will be added later.

100 Hz TBD 4 TBD 4 TBD 16 TBD 2

200 Hz TBD 4 TBD 4 TBD 8 TBD 2

400 Hz TBD 4 TBD 4 TBD 4 TBD 2

800 Hz TBD 2 TBD 2 TBD 2 TBD 2

Table 38. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR (Continued)

44 Freescale Semiconductor, Inc. wake up. This register also configures the interrupt pins INT1 and INT2. Figure 40. 0x2C CTRL_REG3, System Control 3 Register (Read/Write) Table 39. CTRL_REG3 register WAKE_LNDPRT 0: Orientation function is bypassed in SLEEP mode. Default value: 0. WAKE_FF_MT 0: Freefall/Motion function is bypassed in SLEEP mode. Default value: 0. Interrupt polarity ACTIVE high, or ACTIVE low. Default value: 0. Push-Pull/Open Drain selection on interrupt pad. Default value: 0.

This register enables the following interrupts: Auto-WAKE/SLEEP , Orientation detection, Freefall/Motion, and Data Ready. Figure 41. 0x2D: CTRL_REG4, Interrupt Enable Register (Read/Write) Table 40. CTRL_REG4 register detection flags to the system’s interrupt controller. functional block interrupt to the INT1 or INT2 pin.

46 Freescale Semiconductor, Inc. This register maps the desired interrupts to INT2 or INT1. Figure 42. 0x2E: CTRL_REG5, Interrupt Configuration Register determine the appropriate sources of the interrupt. Table 41. CTRL_REG5 register

0 Interrupt is routed to INT2 pin (default)

1 Interrupt is routed to INT1 pin

6.9 Data calibration registers

in an offset compensation range ±250 mg for each ax is. 0x2F: OFF_X, Offset Correction X Register. Figure 43. 0x2F: OFF_X, Correction X Register (Read/Write) Figure 44. 0x30: OFF_Y, Offset Correction Y Register (Read/Write) Figure 45. 0x31: OFF_Z, Offset Correction Z Register (Read/Write) Table 42. OFF_X register D[7:0] X-axis offset value. Default value: 0000_0000. Table 43. OFF_Y register D[7:0] Y-axis offset value. Default value: 0000_0000. Table 44. OFF_Z register D[7:0] Z-axis offset value. Default value: 0000_0000.

48 Freescale Semiconductor, Inc.

7 Mounting Guidelines

Surface mount printed circuit board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The MMA865xFC digital output accelerometers use the DFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications.

7.1 Overview of sold ering considerations

Information provided here is based on experiments executed on DFN devices. They do not represent exact conditions present at a customer site. Therefore, this information should be used as guidance only and process and design optimizations are recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process.

7.2 Halogen content

This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight.

7.3 PCB mounting/sold ering recommendations

1. The PCB land should be designed as Non Solder Mask Defined (NSMD) as shown in Figure 46 "Package mounting measurements". 2. No additional via pattern underneath package. 3. PCB land pad is 0.6 mm x 0.225 mm as shown in Figure 46 "Package mounting measurements". 4. Solder mask opening = PCB land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm 6. Stencil thickness is 100 or 125 um. 7. Do not place any components or vias at a distance le ss than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area. 8. Signal traces connected to pads are as symmetric as possi ble. Put dummy traces on NC pads, to have same length of exposed trace for all pads. 9. Use a standard pick and place process and equipment. Do not use a hand soldering process. 10. Use caution when putting an assembled PCB into an en closure, noting where the screw-down holes are and if any press-fitting is involved. It is important that the assembled PCB remain flat after assembly, to ensure optimal electronic operation of the device. 11. The PCB should be rated for the multiple lead- free reflow condition with max 260°C temperature. 12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale DFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices.

Figure 46. Package mounting measurements Table 45. Board mounting guidelines

50 Freescale Semiconductor, Inc.

8 Tape and Reel

8.1 Tape dimensions

Figure 47. Carrier tape

8.2 Device orientation

Figure 48. Device orientation on carrier tape

9 Package Dimensions

Figure 49. CASE 2162-02, ISSUE O, 10-Lead DFN—page 1

52 Freescale Semiconductor, Inc. Figure 50. CASE 2162-02, ISSUE O, 10-Lead DFN—page 2

Figure 51. CASE 2162-02, ISSUE O, 10-Lead DFN—page 3

54 Freescale Semiconductor, Inc. Figure 52. CASE 2162-02, ISSUE O, 10-Lead DFN—page 4

Table 46. Revision history MMA8653FC

Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and V ortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV , MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Document Number: MMA8653FC Rev. 0