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Technical content
Features
- 1.95 V to 3.6 V supply voltage
- 1.62 V to 3.6 V digital interface voltage
- ±2 g, ±4 g, and ±8 g dynamically selectable full-scale ranges
- Output Data Rates (ODR) from 1.56 Hz to 800 Hz
- 12-bit digital output 2C digital output interface with programmable interrupts
- Four embedded channels of configurable motion detection (Freefall, Motion, Pulse, Transient)
- Orientation (Portrait/Landscape) de tection with programmable hysteresis
- Configurable automatic ODR change triggered by the Auto-Wake/Sleep state change
- 32-sample FIFO
- High-Pass Filter Data available per sample and through the FIFO
- S e l f - T e s t Typical applications
- Tilt compensation in e-compass applications
- Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/ Front position identification)
- Notebook, tablet, e-reader, and l aptop tumble and freefall detection
- Real-time orientation detection (virtual reality and gaming 3D user orientation feedback)
- Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)
- Motion detection for portab le product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)
- Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)
- User interface (tilt menu scrolling, tap detection for button replacement)
ORDERING INFORMATION
Part Number Temperature Range Package Description Shipping MMA8652FCR1 -40°C to +85°C DFN-10 Tape and Reel MMA8652FC Top View Pin Connections VDD SCL INT1 BYP INT2 SDA GND GND VDDIO GND 10-pin DFN 2 mm x 2 mm x 1 mm Case 98ASA00301D Top and Bottom View
2 Freescale Semiconductor, Inc. Table 1. Feature comparison of the MMA865xFC devices
The MMA8652FC device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at: http://www.freescale.com/ 2. In the Keyword search box at the top of the page, enter the device number MMA8652FC. 3. In the Refine Your Result pane on the left, click on the Documentation link. MMA8652FC Sensors Freescale Semiconductor, Inc. 3
Contents
4 Freescale Semiconductor, Inc.
1 Block Diagram and Pin Descriptions
1.1 Block diagram
Figure 1. MMA8652FC block diagram
32 Data Point
6 Freescale Semiconductor, Inc.
1.2 Pin descriptions
Figure 2. Pin connections (bottom view)
1.3 Typical application circuit
Figure 3. Typical application circuit Table 1. Pin descriptions should be placed as close as possible to pin 1 and pin 8 of the device.
- The control signals SCL and SDA are not tolerant of voltages higher than VDDIO + 0.3 V. If VDDIO is removed, then the control signals SCL
therefore require a pullup resistor to VDDIO. I2C Serial Clock 7-bit I2C device address is 0x1D. 3 INT1 Interrupt 1 output The interrupt source and pin settings are user-programmable through the I 2C interface.
4 BYP Internal regulator output
5 INT2 Interrupt 2 output See INT1.
6 GND Ground
7 GND Ground
8 VDDIO Digital Interface Power supply
9 GND Ground
10 SDA
(1) I2C Serial Data See SCL.
10 VDD
Note: 4.7 kΩ Pullup resistors on INT1/INT2 can be added for open-drain operation.
2 Mechanical and Electr ical Specifications
2.1 Absolute maximum ratings
rating conditions for extended periods may affect device reliability. Table 2. Maximum ratings Table 3. ESD and latch-up protection characteristics This device is sensitive to mechanical shock. Improper handling can cause permanent damage to the part. This part is ESD-sensitive. Improper handling can cause permanent damage to the part.
8 Freescale Semiconductor, Inc.
2.2 Mechanical characteristics
Table 4. Mechanical characteristics at VDD = 2.5 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted
- Post-board mount offset specifications are based on an 8-layer PCB, relative to 25°C.
2.3 Electrical characteristics
Table 5. Electrical characteristics at VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C, unless otherwise noted
10 Freescale Semiconductor, Inc.
2.4 I 2C interface characteristic
Figure 4. I2C slave timing diagram Table 6. I2C slave timing values (1)
- All values referred to VIH(min) (0.3 VDD) and VIL(max) (0.7 VDD) levels.
- This device does not stretch the LO W period (tLOW) of the SCL signal.
- C b = total capacitance of one bus line in pF.
- t VD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
- t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
Freescale Semiconductor, Inc. 11
3 Terminology
3.1 Sensitivity
The sensitivity is represented in counts/g.
- In ±2 g mode, sensitivity = 1024counts/g.
- In ±4 g mode, sensitivity = 512counts/g.
- In ±8 g mode, sensitivity = 256counts/g.
3.2 Zero-g offset
Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0 g in X-axis and 0 g in Y -axis, whereas the Z-axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT Registers 0x00, data expressed as a 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress on the MEMS sensor, and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
3.3 Self-Test
Self-T est can be used to verify the transducer and signal chain functionality without the need to apply external mechanical stimulus. When Self-T est is activated:
- An electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case, the sensor outputs w ill exhibit a change in their DC levels which, are related to the selected full scale through the device sensitivity .
- The device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force.
12 Freescale Semiconductor, Inc.
4 Modes of Operation
Figure 5. Operating modes for MMA8652FC how to transition between these modes, see Section 5. Table 7. Operating modes
- The device is powered off.
- All analog and digital blocks are shutdown.
- I 2C bus inhibited. STANDBY I2C communication with MMA8652FC is possible ON VDDIO = High VDD = High ACTIVE bit is cleared
- Only digital blocks are enabled.
- Analog subsystem is disabled.
- Internal clocks disabled. ACTIVE (WAKE/SLEEP) I 2C communication with MMA8652FC is possible ON VDDIO = High VDD = High ACTIVE bit is set All blocks are enabled (digital, analog). SLEEP WAKESTANDBYOFF ACTIVE
5 Functionality
events and notify an external microprocessor over interrupt lines.
- 8-bit or 12-bit data, high-pass filtered data, 8-bit or 12-bit configurable 32-sample FIFO
- Four different oversampling options that allow for the optimum resolution vs. current consumption trade-off to be made for a given application
- Low-power and auto-WAKE/SLEEP modes for reducing current consumption
- Single/double tap with directio nal information (one channel)
- Motion detection with directional information or Freefall (one channel)
- Transient/jolt detection based on a high-pass filter, with a se ttable threshold for detecting the change in acceleration above a threshold with directional information (one channel)
- Flexible user-configurable portrait landscape det ection algorithm, for addressing screen orientation
- Two independent interrupt output pins that are programmable among seven interrupt sources (Data Ready, Motion/Freefall, Tap, Orientation, Transient, FIFO, Auto-WAKE) All functionality is available in ±2 g, ±4 g or ±8 g dynamic measurement ranges. There are many configuration settings for enabling all of the different functions. Separate application notes are available to help configure the device for each embedded functionality .
5.1 Device calibration
be set. When the F_READ bit is cleared, the fast read mode is disabled.
- When the full-scale is set to ±2 g, the measurement range is –2 g to +1.999 g, and each count corresponds to (1/1024) g (0.98 mg) at 12-bit resolution.
- When the full-scale is set to ±4 g, the measurement range is –4 g to +3.998 g, and each count corresponds to (1/512) g
- (1.96 mg) at 12-bit resolution.
- When the full-scale is set to ±8 g, the measurement range is –8 g to +7.996 g, and each count corresponds to (1/256) g (3.9 mg) at 12-bit resolution.
- If only the 8-bit results are used, then the resolution is reduced by a factor of 16. For more information about the data manipulation between data formats and modes, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. There is a device driver available that can be used with the Sensor T oolbox demo board (LFSTBEB865xFC) with this application note.
Table 8. Accelerometer 12-bit output data
14 Freescale Semiconductor, Inc.
5.3 Internal FIFO data buffer
the data (up to 32 samples per axis). The FIFO can run at all output data rates. There are options for accessing the full 12-bit data or for accessing only the 8-bit data. When access speed is more important than high resolution, the 8-bit data read is a better option.
- Fill Buffer mode collects the first 32 samples and asserts the overflow flag when the buffer is full and another sample arrives. It does not collect any more data until the buffer is read. This benefits data logging applications where all samples must be collected.
- Circular Buffer mode allows the buffer to be filled and then new data replaces the oldest sample in the buffer. The most recent 32 samples will be stored in the buffer. This benefits situations where the processor is waiting for an specific interrupt to signal that the data must be flushed to analyze the event.
- Trigger mode will hold the last data up to the point when the trigger occurs, and can be set to keep a selectable number of samples after the event occurs. The MMA8652FC FIFO Buffer has a configurable watermark, allowing the processor to be triggered after a configurable number of samples has filled in the buffer (1 to 32). 5.4 Low power modes vs. high resolution modes The MMA8652FC can be optimized for lower power modes or for higher resolution of the output data. One of the oversampling schemes of the data can be activated when MODS = 10 in Register 0x2B, which will improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz. There is a trade-off between low power and high resolution. Low power can be achieved when the oversampling rate is reduced. When MODS = 11, the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz. …… … … 1000 0000 0001 –1.999 g –3.998 g –7.996 g 1000 0000 0000 –2.0000 g –4.0000 g –8.0000 g
Table 9. Accelerometer 8-bit output data Table 8. Accelerometer 12-bit output data (Continued)
Freescale Semiconductor, Inc. 15
5.5 Auto-WAKE/SLEEP mode
The MMA8652FC can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. The advantage of using the Auto-WAKE/SLEEP is that the system can automatically transition to a higher sample rate (higher current consumption) when needed, but spends the majority of the time in the SLEEP mode (lower current) when the device does not require higher sampling rates.
- Auto-WAKE refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This may also interrupt the processor to transition from a SLEEP mode to a higher power mode.
- SLEEP mode occurs after the accelerometer has not detected an interrupt for longer than the user-definable timeout period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode, to save on current during this period of inactivity . The Interrupts that can WAKE the device from SLEEP are the following: T ap Detection, Orientation Detection, Motion/Freefall, and Transient Detection. The FIFO can be configured to hold the data in the buffer until it is flushed, if the FIFO Gate bit is set (in Register 0x2C) and if the FIFO cannot WAKE the device from SLEEP . The interrupts that can keep the device from falling asleep are the same interrupts that can wake the device—with the addition of the FIFO. If the FIFO interrupt is enabled and data is being accessed continually servicing the interrupt, then the device will remain in WAKE mode.
5.6 Freefall and motion detection
MMA8652FC has a flexible interrupt architecture for detecting either a Freefall or a Motion.
- Freefall can be enabled where the set threshold must be less than the configured threshold.
- Motion can be enabled where the set threshold must be greater than the configured threshold. The motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset); the freefall configuration does not use the high-pass filter.
5.6.1 Freefall detection
The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user-specified threshold for a user-definable amount of time. Usable threshold levels are typically between ±100 mg and ±500 mg.
5.6.2 Motion detection
Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold, the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event.
- The motion detection function can analyze static acceleration ch anges or faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2 g. This condition would need to occur for a minimum of 100 ms to ensure that the event was not just noise. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for configurable set of time (like 100 ms or longer).
- To detect the direction of the motion, there is also directiona l data available in the source register. This is useful for applications such as directional shake or flick, which assists with the algorithm for various gesture detections.
5.7 Transient detection
The MMA8652FC has a built-in, high-pass filter. Acceleration data goes through the high pass filter, eliminating the offset (DC) and low frequencies. The high-pass filter cutoff frequency can be set to four different frequencies, which depends on the Output Data Rate (ODR). A higher cutoff frequency ensures that the DC data (or slower moving data) will be filtered out, allowing only the higher frequencies to pass. The embedded transient detection function uses the high-pass filtered data, allowing you to set the threshold and debounce counter. The transient detection feature can be used in the same manner as the motion detection feature, by bypassing the high-pass filter. There is an option in the configuration register to do this, which adds more flexibility to accommodate various use cases. Many applications use the accelerometer’s static acceleration readings (like tilt), which measure the change in acceleration due to gravity only . These functions benefit from acceleration data being filtered with a low-pass filter where high frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the acceleration. It is simpler to interpret these functions (which are dependent on dynamic acceleration data) when the static component has been removed.
16 Freescale Semiconductor, Inc. determine the direction of the acceleration (either positive or negative).
5.8 Tap detection
The MMA8652FC has embedded single/double and directional tap detection.
- The tap detection function has various customizing timers, fo r setting the pulse time width and the latency time between pulses. There are programmable thresholds for all three axes.
- The tap detection can be configured to run through the high- pass filter and also through a low-pass filter, which provides more customizing and tunable tap detection schemes.
- The status register provides updates on the axes wher e the event was detected and the direction of the tap.
5.9 Orientation detection
Figure 6. The embedded algorithm uses configurable trip points, allowing the selection of the desired midpoint and hysteresis Figure 6. Sensitive axes orientation
18 Freescale Semiconductor, Inc.
5.10 Interrupt regist er configurations
FIFO events, and Auto-SLEEP events. Figure 9. System interrupt generation
- The MMA8652FC features an interrupt signal that indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device.
- The MMA8652FC may also be configured to generate other interrupt signals accordingly, to the programmable embedded functions of the device for Motion, Freefall, Transient, Orientation, and T ap.
5.11 Serial I 2C interface
I2C serial interface (Table 10).
- To enable the I 2C interface, VDDIO line must be tied high (to the interface supply voltage). If VDD is not present and VDDIO is present, then the MMA8652FC is in OFF mode—and communications on the I 2C interface are ignored.
- T h e I 2C interface may be used for communications between other I2C devices; the MMA8652FC does not affect the I2C bus. The I2C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards (Table 11). I2C operation: 1. The transaction on the bus is started through a start condition (ST ART) signal. A ST ART condition is defined as a high-to- low transition on the data line while the SCL line is held high. After ST ART has been transmitted by the Master, the bus is considered busy . 2. The next byte of data transmitted after ST ART contains the slave address in the first seven bits. The eighth bit tells whether the Master is receiving data from the slave or is transmitting data to the slave. 3. After a start condition and when an address is sent, each device in the system compares the first seven bits with its address. If the device’s address matches the sent address, then the device considers itself addressed by the Master.
Table 10. Serial Interface pins
- SDA is a bidirectional line used for sending and receiving the data to/from the interface.
- External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus is free, both SCL and SDA lines are high. SDA I 2C Serial Data Interrupt Controller Data Ready Motion/Freefall Tap (Pulse) Orientation Transient FIFO Auto-SLEEP INT ENABLE INT CFG INT1 INT2 Configurable interrupts These seven interrupt sources can be routed to one of two interrupt pins. The interrupt source must be enabled and configured. If the event flag is asserted because the event condition is detected, then the corresponding interrupt pin (INT1 or INT2) will assert.
- The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The
remains stable low during the high period of the acknowledge clock period.
- A Master may also issue a repeated ST ART during a data transfer. The MMA8652FC expects repeated STARTs to be
used to randomly read from specific registers.
- A low-to-high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer
is always terminated by a STOP. The MMA8652FC's standard slave address is 001 1 101 or 0x01D.
5.11.1 Single-byte read
- The transmission of an 8-bi t command begins on the falling edge of SCL. After the eight clock cycles are used to send
timing diagram for the accelerometer 8-bit I2C read operation.
- The Master (or MCU) transmits a start condition (ST) to t he MMA8652FC [slave address (0x1D), with the R/W bit set to
“0” for a write], and the MMA8652FC sends an acknowledgement.
- Next the Master (or MCU) transmits the address of the register to read, and the MMA8652FC sends an
- The Master (or MCU) transmits a repeated start conditio n (SR) and then addresses the MMA8652FC (0x1D), with the
R/W bit set to “1” for a read from the previously selected register.
- The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge
(NAK) the transmitted data, but transmits a stop condition to end the data transfer. Figure 10. Single-Byte Read timing (I2C) For the following subsections, use the following legend.
5.11.2 Multiple byte read
- When performing a multi-byte read or “burst read”, t he MMA8652FC automatically increments the received register
address commands after a read command is received.
- After following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each
- Until a no acknowledge (NAK) occurs from the Master,
- Followed by a stop condition (SP), which signals the end of transmission.
Table 11. I2C Device address sequence
20 Freescale Semiconductor, Inc. Figure 11. Multiple Byte Read timing (I2C)
5.11.3 Single byte write
- T o start a write command, the Master transmits a start condition (ST) to the MMA8652FC, slave address ($1D) with the
- The MMA8652FC sends an acknowledgement.
- Next the Master (MCU) transmits the address of the register to write to, and the MMA8652FC sends an
- Then the Master (or MCU) transmits the 8-bit data to wr ite to the designated register, and the MMA8652FC sends an
condition (SP) to the data transfer. The data sent to the MMA8652FC is now stored in the appropriate register. Figure 12. Single Byte Write timing (I2C)
5.11.4 Multiple byte write
- After a write command is received, the MMA8652FC automatically increments the received register address
- Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers
after each MMA8652FC acknowledgment (ACK) is received. Figure 13. Multiple Byte Write timing (I2C)
6 Register Descriptions
6.1 Register address map
Table 12. MMA8652FC register address map 0x08 — — — — — — Reserved. Read return 0x00. PL_CFG(1)(4) R/W 0x11 0x12 10000000 0x80 Landscape/Portrait configuration. — — — — — — Reserved. Read return 0x00.
22 Freescale Semiconductor, Inc. stored auto-increment address is cleared whenever an I2C STOP condition is detected.
- Register contents are preserved when a trans ition from ACTIVE to STANDBY mode occurs.
- Register contents are reset when a transit ion from STANDBY to ACTIVE mode occurs.
- Register contents can be modified at any time in either STANDBY or ACTIVE mode. A write to this register will cause a reset of the
corresponding internal system debounce counter.
- Register contents can only be modified while the device is in STANDBY mode; the only exceptions to this are the CTRL_REG1[ACTIVE] and
Table 12. MMA8652FC register address map (Continued)
6.2 Register bit map
Table 13. MMA8652FC register bit map
00 STATUS/F_STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR
01 OUT_X_MSB 12-bit X Data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4
02 OUT_X_LSB 12-bit X Data R XD3 XD2 XD1 XD0 0 0 0 0
03 OUT_Y_MSB 12-bit Y Data R YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4
04 OUT_Y_LSB 12-bit Y Data R YD3 YD2 YD1 YD0 0 0 0
05 OUT_Z_MSB 12-bit Z Data R ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4
06 OUT_Z_LSB 12-bit Z Data R ZD3 ZD2 ZD1 ZD0 0 0 0 0
09 F_SETUP FIFO Setup R/W F_MODE1 F_MODE0 F_WMRK5 F_WMRK4 F_WMRK3 F_WMRK2 F_WMRK1 F_WMRK0
10 PL_STATUS PL Status R NEWLP LO — — — LAPO[1] LAPO[0] BAFRO
11 PL_CFG PL Configuration R/W DBCNTM PL_EN — — — — — —
12 PL_COUNT PL DEBOUNCE R/W DBNCE[7] DBNCE[6] DBNCE [5] DBNCE[4] DBNCE[3] DB NCE[2] DBNCE[1] DBNCE[0]
13 PL_BF_ZCOMP PL Back/Front Z Comp R/W BKFR[1] BKFR[0] — — — ZLOCK[2] ZLOCK[1] ZLOCK[0]
15 FF_MT_CFG Freefall/Motion Config R/W ELE OAE ZEFE YEFE XEFE — — —
16 FF_MT_SRC Freefall/Motion Source R EA — ZHE ZHP YHE YHP XHE XHP
17 FF_MT_THS Freefall/Motion Threshold R/W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0
18 FF_MT_COUNT Freefall/Motion Debounce R/W D7 D6 D5 D4 D3 D2 D1 D0
20 TRANSIENT_COUNT Transient Debounce R/W D7 D6 D5 D4 D3 D2 D1 D0
21 PULSE_CFG Pulse Config R/W DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE
22 PULSE_SRC Pulse Source R EA AxZ AxY AxX DPE Pol_Z Pol_Y Pol_X
23 PULSE_THSX Pulse X Threshold R/W — THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0
24 PULSE_THSY Pulse Y Threshold R/W — THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0
25 PULSE_THSZ Pulse Z Threshold R/W — THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0
26 PULSE_TMLT Pulse First Timer R/W TMLT7 TMLT6 TMLT5 TMLT4 TMLT3 TMLT2 TMLT1 TMLT0
27 PULSE_LTCY Pulse Latency R/W LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0
28 PULSE_WIND Pulse 2nd Window R/W WIND7 WIND6 WIND5 WIND4 WIND3 WIND2 WIND1 WIND0
29 ASLP_COUNT Auto-SLEEP Counter R/W D7 D6 D5 D4 D3 D2 D1 D0
24 Freescale Semiconductor, Inc.
30 OFF_Y Y-axis 0 g offset R/W D7 D6 D5 D4 D3 D2 D1 D0
31 OFF_Z Z-axis 0 g offset R/W D7 D6 D5 D4 D3 D2 D1 D0
Table 13. MMA8652FC register bit map (Continued)
6.3 Data registers
MMA8652FC, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers.
- When the F_MODE bits (F_SETUP register 0x09, bit 6 and 7) ar e cleared, the FIFO is not ON. Register 0x00 reflects the real-time status information of the X, Y and Z sample data.
- When the F_MODE value is greater than zero, then the FIFO is ON (in either Fill, Cir cular, or Trigger mode). In this case, register 0x00 will reflect the status of the FIFO. It is expected that when the FIFO is ON, the user will access the data from register 0x01 (X_MSB) for either the 12-bit or 8-bit data.
- When accessing the 8-bit data, the F_READ bit (register 0x2A) is set, which modifies the auto-incrementing to skip over the LSB data.
- When the F_READ bit is cleared, the 12-bit data is read , accessing all 6 bytes sequentially (X_MSB, X_LSB, Y_MSB, Y_LSB, Z_MSB, Z_LSB). 6.3.1 0x00: STATUS Data Status register (F_MODE = 00) When F_MODE = 0, register 0x00 reflects the real-time status information of the X, Y and Z sample data; it contains the X, Y , and Z data overwrite and data ready flag. These registers contain the X-axis, Y-axis, and Z-axis 12-bit output sample data (expressed as 2's complement numbers).
- OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the auto- incrementing address range of 0x01 – 0x06, to reduce reading the status followed by 12-bit axis data to 7 bytes. If the F_READ bit is set (0x2A bit 1), then auto-increment will skip over LSB registers (to access the MSB data only). This will shorten the data acquisition from seven bytes to four bytes.
Table 14. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only) Back to Register Address Map Table 15. STATUS register bits
- Set whenever a new acceleration data is produced before completing the retrieval of the previous set. This event occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been overwritten.
- Cleared when the high bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the channels are read.
0 No data overwrite has occurred (default)
- Set whenever a new acceleration sample related to the #-axis is generated before the retrieval of the previous sample. When this occurs, the previous sample is overwritten.
- Cleared whenever the OUT_#_MSB register is read.
1 Previous Z-axis data was overwritten by new #-axis
- Set when a new sample for any of the enabled channels is available.
- Cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the channels are read.
0 No new set of data ready (default)
1 A new set of data is ready
- Set whenever a new acceleration sample related to the #-axis is generated.
- Cleared whenever the OUT_#_MSB register is read. 0N o n e w #-axis data ready (default) 1N e w #-axis data is ready 1Y D R Y-axis new data available 0X D R X-axis new data available
26 Freescale Semiconductor, Inc.
- The LSB registers can only be read immediately followin g the read access of the corresponding MSB register. — A random read access to the L SB registers is not possible. — Reading the MSB register and then the LSB register in sequence ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the MSB and the LSB byte.
- If the FIFO is enabled (F_MODE > 00), then Register 0x01 point s to the FIFO read pointer, while Registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read.
6.4 FIFO registers
Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. of samples stored in the buffer when the FIFO is enabled). or greater than then F_WMRK value.
- If the FIFO overflow flag is cleared and F_MODE = 11, then t he FIFO overflow flag will remain 0 before the trigger event (even if the FIFO is full and overflows).
- If the FIFO overflow flag is set and F_MODE is = 11, then the FIFO has stopped accepting samples. 6.4.2 0x09: F_SETUP FIFO Setup register
Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only) Back to Register Address Map Table 17. FIFO Flag Event 0 — No FIFO overflow events were detected. 1 — FIFO event was detected; the FIFO has overflowed. — 0 No FIFO watermark events were detected. If F_MODE = 11, then a Trigger Event was detected. Table 18. FIFO Sample Count register Indicates the number of acceleration samples currently stored in the FIFO buffer.
- Count 00_0000 indicates that the FIFO is empty. (Default value)
- 00_0001 to 10_0000 indicates that 1 to 32 samples are stored in the FIFO.
Table 19. 0x09 F_SETUP: FIFO Setup register (Read/Write) Back to Register Address Map
28 Freescale Semiconductor, Inc. mode can be switched between Fill mode, Circular mode, and Trigger mode. dictated by the selected system ODR.
- In ACTIVE mode, the ODR is set by the DR bits (CTRL_REG1 register).
- When Auto-SLEEP is active, the ODR is set by the ASLP_RA TE field (CTRL_REG1 register). When a byte is read from the FIFO buffer, the oldest sample data in the FIFO buffer is returned (and also deleted from the front of the FIFO buffer), while the FIFO sample count is decremented by one. It is assumed that the host application will use the I 2C multi- byte read transaction to empty the FIFO. 6.4.3 0x0A: TRIG_CFG Trigger Configuration register The Trigger Configuration register configures which interrupt(s) may trigger the FIFO.
Table 20. F_SETUP register
- Bit field can be written in ACTIVE mode.
- Bit field can be written in STANDBY mode.
01 FIFO contains the most recent samples when overflowed (circular buffer). The oldest sample is discarded and replaced by a new sample. 10 FIFO stops accepting new samples when overflowed. both before and after the trigger event, and it is definable by the watermark setting.
- The FIFO is flushed whenever the FIFO is disabled, during an automatic ODR change (Auto-WAKE/ SLEEP), or transitioning from STANDBY mode to ACTIVE mode.
- Disabling the FIFO (F_MODE = 00) resets the F_OVF, F_WMRK_FLAG, F_CNT to zero.
- A FIFO overflow event (i.e., F_CNT = 32) will assert the F_OVF flag and a FIFO sample count equal to the sample count watermark (i.e., F_WMRK) asserts the F_WMRK_FLAG event flag. 5–0 F_WMRK[5:0] (2) FIFO Event Sample Count Watermark These bits set the number of FIFO samples required to trigger a watermark interrupt. A FIFO watermark event flag is raised when FIFO sample count F_CNT[5:0] ≥ F_WMRK[5:0] watermark.
- Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation.
- Also used to set the number of pre-trigger samples in Trigger mode. 00_0000 (default)
Table 21. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write) Back to Register Address Map Table 22. Trigger Configuration register
- Trigger bits are reset by reading the appropriate source register.
1 This function can trigger the FIFO at its (the function’s) interrupt
0 This function has not asserted its interrupt.
4 Trig_LNDPRT
3 Trig_PULSE Pulse Interrupt Trigger 0
2 Trig_FF_MT Freefall/Motion Trigger 0
6.5 System status and ID registers
- the status of the FIFO gate error
- and the number of samples since the gate error occurred. 6.5.2 0x0C: INT_SOURCE System Interrupt Status register In the interrupt source register, the status of the various embedded features can be determined.
- The bits that are set (logic ‘1’) indicate which function has asserted an interrupt.
- The bits that are cleared (logic ‘0’) indicate which function has not asserted (or has deasserted) an interrupt. INT_SOURCE register bits are set by a low-to-high transition, and are cleared by reading the appropriate interrupt source register. For example, the SRC_DRDY bit is cleared when the ZYXDR bit (STATUS register) is cleared, but the SRC_DRDY bit is not cleared by simply reading the STATUS register (0x00), but is cleared by reading all the X, Y, and Z MSB data.
Table 23. 0x0B SYSMOD: System Mode register (Read-Only) Back to Register Address Map Table 24. SYSMOD register 1 FIFO Gate Error was detected. Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register. Interrupt Control register”. Number of ODR time units since FGERR was asserted. Reset when FGERR bit is cleared.
00 STANDBY mode (default)
01 WAKE mode
30 Freescale Semiconductor, Inc. The device identification register identifies the part. The default value is 0x4A (for MMA8652FC). This value is programmed by Freescale before the part leaves the factory. For custom alternate values, contact Freescale. Table 26. INT_SOURCE register
7 SRC_ASLP
- WAKE-to-SLEEP transition occurs when no interrupt occurs for a time period that exceeds the user- specified limit (ASLP_COUNT). This causes the system to transition to a user-specified low ODR setting.
- SLEEP-to-WAKE transition occurs when the user-specified interrupt event has woken the system; thus causing the system to transition to a user-specified high ODR setting.
- Reading the SYSMOD register clears the SRC_ASLP bit.
1 An interrupt event that can cause a WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition has
6 SRC_FIFO
- FIFO interrupt event generators: FIFO Overflow, or (Watermark: F_CNT = F_WMRK) and the interrupt has been enabled.
- SRC_FIFO bit is cleared by reading the F_STATUS register. 1 A FIFO interrupt event (such as an overflow event or watermark) has occurred. 0 No FIFO interrupt event has occurred. (default)
5 SRC_TRANS
- SRC_TRANS bit is asserted whenever the EA bit (TRANS_SRC register) is asserted and the interrupt has been enabled.
- SRC_TRANS bit is cleared by reading the TRANS_SRC register. 1A n acceleration transient value greater than user-specified threshold has occurred. 0 No transient event has occurred. (default)
4 SRC_LNDPRT
- SRC_LNDPRT bit is asserted whenever the NEWLP bit (PL_STATUS register) is asserted and the interrupt has been enabled.
- SRC_LNDPRT bit is cleared by reading the PL_STATUS register. 1 An interrupt was generated due to a change in the device orientation status. 0 No change in orientation status was detected. (default)
3 SRC_PULSE
- SRC_PULSE bit is asserted whenever the EA bit (PULSE_SRC register) is asserted and the interrupt has been enabled.
- SRC_PULSE bit is cleared by reading the PULSE_SRC register. 1 An interrupt was generated due to single and/or double pulse event. 0 No pulse event was detected. (default)
2 SRC_FF_MT
- SRC_FF_MT bit is asserted whenever the EA bit (FF_MT_SRC register) is asserted and the FF_MT interrupt has been enabled.
- SRC_FF_MT bit is cleared by reading the FF_MT_SRC register. 1 The Freefall/Motion function interrupt is active. 0 No Freefall or Motion event was detected. (default) 1 — Could be 1 or 0.
0 SRC_DRDY
- SRC_DRDY bit is asserted when the ZYXOW and/or ZYXDR bit is set and the interrupt has been enabled.
- SRC_DRDY bit is cleared by reading the X, Y, and Z data. 1 The X, Y, Z data ready interrupt is active (indicating the presence of new data and/or data overrun). 0 The X, Y, Z interrupt is not active. (default)Table 27. 0x0D: WHO_AM_I Device ID register (Read-Only) Back to Register Address Map Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01001 0 1 0
6.6 Data configuration registers
is set, the FIFO and DATA registers both will contain high-pass filtered data. Table 28. 0x0E: XYZ_DATA_CFG register (Read/Write) Back to Register Address Map
000 H PF_OUT 0 0 F S1F S0
Table 29. XYZ Data Configuration register 1 Output data is high-pass filtered. Table 30. Full-Scale Range
32 Freescale Semiconductor, Inc. application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers . Table 31. 0x0F HP_FILTER_CUTOFF: High-Pass Filter register (Read/Write) Back to Register Address Map
00 Pulse_HPF_BY Pulse_LPF_EN 0 0 SEL1 SEL0
Table 32. High-Pass filter cutoff register
5 Pulse_HPF_BYP
0 HPF is enabled for pulse processing (default)
1 HPF is bypassed for pulse processing
4 Pulse_LPF_EN
0 LPF is disabled for pulse processing (default)
1 LPF is enabled for pulse processing
00 Default value, see Table 33
Table 33. High-Pass filter cutoff options
6.7 Portrait/Landscape configur ation and status registers
Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. orientations, see Figure 6. The interrupt is cleared when reading the PL_STATUS register.
- The orientation mechanism state change is limited to a maximum 1.25 g. The current position is locked if the absolute value of the acceleration experienced on any of the three axes is greater than 1.25 g.
- LAPO, BAFRO, and LO continue to change when NEWLP is set.
Table 34. 0x10 PL_STATUS Register (Read-Only) Back to Register Address Map Table 35. PL_STATUS register
- NEWLP is set to 1 after the first orientation detection after a STANDBY-to-ACTIVE transition, and whenever a change in LO, BAFRO, or LAPO occurs.
- NEWLP bit is cleared anytime PL_STATUS register is read.
0 No change (default)
1 BAFRO and/or LAPO and/or Z-Tilt lockout value has changed
0 Lockout condition has not been detected (default)
1 Z-Tilt lockout trip angle has been exceeded.
- The default power-up state is BAF RO = 0, LAPO = 00, and LO = 0.
00 Portrait Up: Equipment standing vertical ly in the normal orientation (default)
01 Portrait Down: Equipment standing vertically in the inverted orientation
10 Landscape Right: Equipment is in landscape mode to the right
11 Landscape Left: Equipment is in landscape mode to the left.
0 BAFRO
0 Front: Equipment is in the front-facing orientation (default)
1 Back: Equipment is in the back-facing orientation
34 Freescale Semiconductor, Inc. transition from WAKE to SLEEP (or SLEEP to Wake) resets the internal Landscape/Portrait debounce counter. Table 36. 0x11 PL_CFG register (Read/Write) Back to Register Address Map Table 37. PL_CFG register 0 Decrements debounce whenever the conditi on of interest is no longer valid.
6 PL_EN
1 Portrait/Landscape Detection is enabled. Table 38. 0x12 PL_COUNT register (Read/Write) Back to Register Address Map Table 39. PL_COUNT register Table 40. PL_COUNT relationship with the ODR
a range of 65° to 80° (with 5° step increments). to Landscape mode and from Landscape to Portrait mode. This register includes a value for the hysteresis. Table 41. 0x13: PL_BF_ZCOMP register (Read/Write) Back to Register Address Map Table 42. PL_BF_ZCOMP register
- Step size = 5°
- Range = ±(65° to 80°) 1. All angles are accurate to ±2°. 01 ≥ ±75° (default) 5–3 — Can be 0 or 1. 2–0 ZLOCK[2:0] Z-lock angle threshold(1)
- Step size is 4°
- Range is from 14° to 43° 100 ≥ 29° (default) 111 ≥ 43° (maximum)
Table 43. Z-lock threshold angles Table 44. Back/Front orientation definitions
00 Z < 80° or Z > 280° Z > 100° and Z < 260°
01 Z < 75° or Z > 285° Z > 105° and Z < 255°
10 Z < 70° or Z > 290° Z > 110° and Z < 250°
11 Z < 65° or Z > 295° Z > 115° and Z < 245°
Table 45. 0x14: P_L_THS_REG register (Read/Write) Back to Register Address Map Table 46. P_L_THS_REG register
36 Freescale Semiconductor, Inc. All angles are accurate to ±2°. from portrait to landscape and landscape to portrait. This angle ranges from 0° to ±24°. Table 47. Threshold angle thresholds look-up table Table 48. Trip angles with hysteresis for 45° angle Table 46. P_L_THS_REG register (Continued)
Freescale Semiconductor, Inc. 37
6.8 Freefall/Motion configuration and status registers
The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15: FF_MTG_CFG, bit 6). The freefall/motion detection block can be disabled by setting all three bits (ZEFE, YEFE, XEFE) to zero. Depending on the register bits ELE (0x15: FF_MTG_CFG, bit 7) and OAE (0x15: FF_MTG_CFG, bit 6), each of the freefall and motion detection block can operate in four different modes.
6.8.1 Motion and freefall modes
6.8.1.1 Mode 1: Freefall det ection with ELE = 0, OAE = 0
In this mode, the EA bit (0x16: FF_MTG_CFG, bit 7) indicates a freefall event after the debounce counter is complete. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. Once the EA bit is set, and DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. This is because the counter is in decrement mode. If DBCNTM = 1, then the EA bit is cleared as soon as the freefall condition disappears, and will not be set again before the delay specified by FF_MT_COUNT has passed. Reading the FF_MT_SRC register does not clear the EA bit. The event flags (0x16) ZHE, ZHP , YHE, YHP , XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set.
6.8.1.2 Mode 2: Freefall det ection with ELE = 1, OAE = 0
In this mode, the EA event bit indicates a freefall event after the debounce counter. Once the debounce counter reaches the time value for the set threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, the EA bit and the debounce counter are cleared, and a new event can only be generated after the delay specified by FF_MT_CNT. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. While EA = 0, the event flags ZHE, ZHP , YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP are latched when the EA event bit is set. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP will start changing only after the FF_MT_SRC register has been read.
6.8.1.3 Mode 3: Motion det ection with ELE = 0, OAE = 1
In this mode, the EA bit indicates a motion event after the debounce counter time is reached . The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the EA bit is set and if DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. If DBCNTM = 1, then the EA bit is cleared as soon as the motion high g condition disappears. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Reading the FF_MT_SRC does not clear any flags, nor is the debounce counter reset.
6.8.1.4 Mode 4: Motion det ection with ELE = 1, OAE = 1
In this mode, the EA bit indicates a motion event after debouncing. The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the debounce counter reaches the threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, all register bits are cleared and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT. While the bit EA is zero, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. When the EA bit is set, these bits (ZHE, ZHP , YHE, YHP, XHE, XHP) keep their current value until the FF_MT_SRC register is read.
38 Freescale Semiconductor, Inc. This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. Figure 14. FF_MT_CFG high-g and low-g threshold Table 49. 0x15 FF_MT_CFG register (Read/Write) Back to Register Address Map Table 50. FF_MT_CFG register Event Latch Enable: Event flags are latched into FF_MT_SRC register. status in the FF_MT_SRC will indicate the real-time status of the event.
- If ELE bit is set to 1, then the event flags are frozen when the EA bit gets set, and the event flags are cleared by reading the FF_MT_SRC source register.
- Reading the FF_MT_SRC register clears the event flag EA and all FF_MT_SRC bits.
0 Event flag latch disabled (default)
1 Event flag latch enabled
Selects between Motion (logical OR combination) and Freefall (logical AND combination) detection.
0 Freefall flag (Logical AND combination) (default)
1 Motion flag (Logical OR combination)
the threshold set in FF_MT_THS register.
- If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC register.
0 Event detection disabled (default)
1 Raise event flag on measured accelera tion value beyond preset threshold
4 YEFE
the threshold set in FF_MT_THS register.
- If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC register.
3 XEFE
the threshold set in FF_MT_THS register.
- If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC register.
INT_CFG_FF_MT register bits to generate the freefall/motion interrupts.
- An X,Y, or Z motion is true when the acceleration value of t he X or Y or Z channel is higher than the preset threshold value defined in the FF_MT_THS register.
- An X, Y, and Z low event is true when the acceleration value of the X and Y and Z channel is lower than or equal to the preset threshold value defined in the FF_MT_THS register.
Table 51. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only) Back to Register Address Map Table 52. Freefall/Motion Source register
0 No event flag has been asserted (default)
1 One or more event flags has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. ZHE bit always reads zero if the ZEFE control bit is set to zero.
0 No Z motion event detected (default)
1 Z motion has been detected
ZHP bit always reads zero if the ZEFE control bit is set to zero.
0 Z event was positive g (default)
1 Z event was negative g
YHE bit always reads zero if the YEFE control bit is set to zero.
0 No Y motion event detected (default)
1 Y motion has been detected
YHP bit always reads zero if the YEFE control bit is set to zero.
0 Y event detected was positive g (default)
1 Y event was negative g
XHE bit always reads zero if the XEFE control bit is set to zero.
0 No X motion event detected (default)
1 X motion has been detected
XHP bit always reads zero if the XEFE control bit is set to zero.
0 X event was positive g (default)
1 X event was negative g
40 Freescale Semiconductor, Inc. FF_MT_THS is the threshold register used to detect freefall motion events.
- The unsigned 7-bit FF_MT_THS threshold register holds the threshold for the freefall detection where the magnitude of the X and Y and Z acceleration values is lower or equal than the threshold value.
- Conversely, the FF_MT_THS also holds the threshold for the motion detection where the magnitude of the X or Y or Z acceleration value is higher than the threshold value. The threshold resolution is 0.063 g/LSB and the threshold register has a range of 0 to 127 counts. The maximum range is to ±8 g. Note that even when the full scale value is set to ±2 g or ±4 g, the motion still detects up to ±8 g. The DBCNTM bit configures the way in which the debounce counter is reset when the inertial event of interest is momentarily not true.
- When the DBCNTM bit is 1, the debounce counter is cleared to 0 whenever the inertial event of interest is no longer true as shown in Figure 15, (b).
- While the DBCNTM bit is set to 0, the debounce counter is decremented by 1 whenever the inertial event of interest is no longer true (Figure 15, (c)) until the debounce counter reaches 0 or until the inertial event of interest becomes active. Decrementing the debounce counter acts as a median enabling the system to filter out irregular spurious events (which might impede the detection of inertial events). 6.8.5 0x18 FF_MT_COUNT Debounce register The Debounce register sets the number of debounce sample counts for the event trigger. The Debounce register sets the minimum number of debounce sample counts that continuously match the detection condition selected by you for the freefall/motion event. When the internal debounce counter reaches the FF_MT_COUNT value, a freefall/motion event flag is set. The debounce counter will never increase beyond the FF_MT_COUNT value. The time step used for the debounce sample count depends on the ODR chosen and the Oversampling mode, as shown in Table 57.
Table 53. 0x17 FF_MT_THS register (Read/Write) Back to Register Address Map Table 54. FF_MT_THS register
0 Increments or decrements debounce (default)
1 Increments or clears counter. Table 55. 0x18 FF_MT_COUNT register (Read/Write) Back to Register Address Map Table 56. FF_MT_COUNT register
Figure 15. DBCNTM bit function Table 57. FF_MT_COUNT relationship with the ODR
42 Freescale Semiconductor, Inc.
6.9 Transient configurati on and status registers
detection function, except that high-pass filtered data is compared. detection. This allows for the device to have two motion detection functions. filter is bypassed, the function behaves similar to the motion detection. Table 58. 0x1D TRANSIENT_CFG register (Read/Write) Back to Register Address Map Table 59. TRANSIENT_CFG register Reading of the TRANSIENT_SRC register clears the event flag.
3 ZTEFE Event flag enable for Z-transient acceleration greater than a
1 Raise event flag on measured acceleration delta
value that is greater than a transient threshold. a transient threshold event.
0 HPF_BYP
0 Data to transient acceleration detection block is through HPF
1 Data to transient acceleration detection block is NOT through
TRANSIENT_SRC register is read, it clears the interrupt for the transient detection. updated. However no *TRANSE bit may get cleared before the TRANSIENT_SRC register is read.
- When the EA bit gets set while ELE = 1, all other status bits get frozen at their current state.
- By reading the TRANSIENT_SRC register, all bits get cleared.
Table 60. 0x1E TRANSIENT_SRC register (Read-Only) Back to Register Address Map Table 61. TRANSIENT_SRC register 1 One or more event flags has been asserted.
5 ZTRANSE
0 No interrupt (default)
1 Z-transient acceleration greater than the value of TRANSIENT_THS event has occurred
4 Z_Trans_Pol
0 Z-event was positive g (default)
1 Z-event was negative g
3 YTRANSE
1 Y-transient acceleration greater than the value of TRANSIENT_THS event has occurred
2 Y_Trans_Pol
0 Y-event was Positive g (default)
1 Y-event was Negative g
1 XTRANSE
1 X-transient acceleration greater than the value of TRANSIENT_THS event has occurred
0 X_Trans_Pol
0 X-event was Positive g (default)
1 X-event was Negative g
44 Freescale Semiconductor, Inc. pass filtered acceleration value exceeds the threshold limit, an event flag is raised and the interrupt is generated (if enabled). unsigned value of high-pass filtered data is greater than the user-specified value of TRANSIENT_THS. The time step for the transient detection debounce counter is set by the value of the system ODR and the Oversampling mode. Table 62. 0x1F TRANSIENT_THS register (Read/Write) Back to Register Address Map Table 63. TRANSIENT_THS register
7 DBCNTM
1 Increments or clears counter
A 7-bit unsigned number, with 0.063 g/LSB. The maximum threshold is ±8 g. function will still operate up to ±8 g. Table 64. 0x20 TRANSIENT_COUNT register (Read/Write) Back to Register Address Map Table 65. TRANSIENT_COUNT register Table 66. TRANSIENT_COUNT relationship with the ODR
6.10 Pulse configuration and status registers
Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. The tap detection registers are referred to as “Pulse”. Table 67. 0x21 PULSE_CFG register (Read/Write) Back to Register Address Map Table 68. PULSE_CFG register
0 Double Pulse detection is not aborted if the start of a pulse is detected during
1 Setting the DPA bit momentarily suspends the double tap detection if the
specified by the PULSE_LTCY register. 6E L E Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag.
0 Event detection is disabled (default)
1 Event detection is enabled
5 ZDPEFE Event flag enable for a double pulse event on Z-axis
4 ZSPEFE Event flag enable for a single pulse event on Z-axis
3 YDPEFE Event flag enable for a double pulse event on Y-axis
2 YSPEFE Event flag enable for a single pulse event on Y-axis
1 XDPEFE Event flag enable for a double pulse event on X-axis
0 XSPEFE Event flag enable for a single pulse event on X-axis
46 Freescale Semiconductor, Inc. axis and event must be enabled in register 0x21 for the event flag to be asserted in the source register.
- When the EA bit gets set while ELE = 1, all status bits (AxZ, AxY, AxZ, DPE, and PolX, PolY, PolZ) are frozen.
- Reading the PULSE_SRC register clears all bits.
- Reading the source register will clear the interrupt.
Table 69. 0x22 PULSE_SRC register (Read-Only) Back to Register Address Map Table 70. PULSE_SRC register
0 No interrupt has been generated (default)
1 One or more interrupt events have been generated
1 Z-axis event has occurred
1 Y-axis event has occurred)
1 X-axis event has occurred
0 Single pulse event triggered interrupt (default)
1 Double pulse event triggered interrupt
0 Pulse event that triggered interrupt was positive (default)
1 Pulse event that triggered interrupt was negative)
1 Pulse event that triggered interrupt was negative
registers define the threshold that is used by the system to start the pulse detection procedure.
- The threshold values range from 1 to 1 27, with steps of 0.63 g/LSB at a fixed ±8 g acceleration range, thus the minimum resolution is always fixed at 0.063 g/LSB.
- The PULSE_THSX, PULSE_ THSY and PULSE_THSZ registers define the threshold which is used by the system to start the pulse detection procedure.
- The threshold value is expressed over seven bits as an unsigned number.
Table 71. 0x23 PULSE_THSX register (Read/Write) Back to Register Address Map
0 THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0
Table 72. PULSE_THSX register Table 73. 0x24 PULSE_THSY register (Read/Write) Back to Register Address Map
0 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0
Table 74. PULSE_THSY register Table 75. 0x25 PULSE_THSZ register (Read/Write) Back to Register Address Map
0 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0
Table 76. PULSE_THSZ register
48 Freescale Semiconductor, Inc. to be considered a valid pulse. The minimum time step for the pulse time limit is defined in Table 79 and Table 80.
- Maximum time for a given ODR and Oversampling mode is the time step pulse multiplied by 255.
- The time steps available are dependent on the Oversampling mode and whether the pulse low-pass filter option is enabled or not.
- The pulse low-pass filter is set in Register 0x0F.
Table 77. 0x26 PULSE_TMLT register (Read/Write) Back to Register Address Map Table 78. PULSE_TMLT register Table 79. Time Step for PULSE time limit (Reg 0x0F) Pulse_LPF_EN = 1 Table 80. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0
Bits LTCY7 – LTCY0 define the time interval that starts after the first pulse detection. During this time interval, all pulses are ignored. This timer must be set for single pulse and for double pulse. The minimum time step for the pulse latency is defined in Table 83 and Table 84.
- The maximum time is the time step at the ODR and Oversampling mode multiplied by 255.
- The timing also changes when the Pulse LPF is enabled or disabled.
Table 81. 0x27 PULSE_LTCY register (Read/Write) Back to Register Address Map Table 82. PULSE_LTCY register Table 83. Time Step for PULSE Latency at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 84. Time Step for PULSE Latency at ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0
50 Freescale Semiconductor, Inc. double pulse need not finish within the time specified by the PULSE_WIND register. oversampling mode and LPF filter option multiplied by 255. Table 85. 0x28: PULSE_WIND Second Pulse Time Window register Back to Register Address Map Table 86. PULSE_WIND register Table 87. Time Step for PULSE Detection window at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 88. Time Step for PULSE Detection window at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 0
6.11 Auto-WAKE/SLEEP detection
- Wake ODR is set by CTRL_REG1[DR] bits.
- Sleep ODR is set by CTRL_REG1[ASLP_RATE] bits.
- Auto WAKE/SLEEP function is enabled by asserting the CTRL_REG2[SLPE] bit. D7–D0 defines the minimum duration time needed to change the current ODR value from DR to ASLP_RATE. The time step and maximum value depend on the ODR chosen (as shown in Table 91). For functional blocks that may be monitored for inactivity (to trigger the “return to SLEEP” event), see Table 92.
Table 89. 0x29 ASLP_COUNT register (Read/Write) Back to Register Address Map Table 90. ASLP_COUNT register Table 91. ASLP_COUNT relationship with ODR
200 Hz 0 to 81 5 320
100 Hz 0 to 81 10 320
50 Hz 0 to 81 20 320
12.5 Hz 0 to 81 80 320
6.25 Hz 0 to 81 160 320
1.56 Hz 0 to 162 640 640
Table 92. SLEEP/WAKE mode gates and triggers
52 Freescale Semiconductor, Inc.
- Four interrupt sources can WAKE the device: Transient, Orientat ion, T ap, and the Motion/Freefall. One or more of these functions can be enabled. — To WAKE the device, the desired function(s) must be ena bled in CTRL_REG4 register and set to WAKE-to-SLEEP in CTRL_REG3 register. — All enabled functions still run in SLEEP mode at the SLEEP ODR. Only the functions that have been selected for WAKE from SLEEP will actually WAKE the device (as configured in register 0x2C). — The Auto-WAKE/SLEEP interrupt d oes not affect the WAKE/SLEEP, nor does the data ready interrupt. — Note that the FIFO does not WAKE the device. — When set to 1, the FIFO gate (bit 7 in Register 0x2C) will hold the last data in the FIFO, before transitioning to a different ODR. After the buffer is flushed, it will accept new sample data at the current ODR. See Register 0x2C for the WAKE-from-SLEEP interrupt enable bit definitions.
- MMA8652FC has four functions that can be used to keep the sensor from falling asleep: Transient, Orientation, T ap and Motion/Freefall.
- Auto-SLEEP bit: — If the Auto-SLEEP bit is disabled, then the device can only toggle between STANDBY and WAKE mode. — If Auto-SLEEP interrupt is enabled, th en transitioning from ACTIVE mode to Auto-SLEEP mode (or vice versa) generates an interrupt.
6.12 System and control registers
of the fields within CTRL_REG1 (0x2A). and STANDBY/ACTIVE mode selection. Table 93. 0x2A CTRL_REG1 register (Read/Write) Back to Register Address Map Table 94. CTRL_REG1 register Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode.
1 F_READ
0 Normal mode (default)
1 Fast Read Mode
0 STANDBY mode (default)
1 ACTIVE mode
The ACTIVE bit selects between STANDBY mode and ACTIVE mode.
- The F_Read bit selects between normal and Fast Read mode. When selected, the auto-increment counter will skip over the LSB data bytes. Data read from the FIFO will skip over the LSB data, reducing the acquisition time.
- Note that F_READ can only be changed when FMODE = 00.
- The F_READ bit applies for both the output registers and the FIFO.
Table 95. SLEEP mode rates rate set by the ASLP_RATE field. Table 96. System output data-rate selection Table 97. Full-Scale selection using ACTIVE bit
0 STANDBY (default)
54 Freescale Semiconductor, Inc. SLEEP and WAKE mode power scheme selection (oversampling modes). resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode. The I2C communication system is reset to avoid accidental corrupted data access. At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero. available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0]. Table 98. 0x2B CTRL_REG2 register (Read/Write) Back to Register Address Map Table 99. CTRL_REG2 register Activates the self-test function.
- When ST is set, the X, Y, and Z outputs will shift.
0 Self-Test disabled (default)
1 Self-Test enabled
RST bit is used to activate the software reset.
- The reset mechanism is enabled in both STANDBY and ACTIVE modes.
0 Device reset disabled (default)
0 Auto-SLEEP is not enabled (default)
Table 100. (S)MODS Oversampling modes
00 N ormal
interrupt to wake. CTRL_REG3 register also configures the interrupt pins INT1 and INT2. Table 101. MODS Oversampling modes averaging values at each ODR Table 102. 0x2C CTRL_REG3 register (Read/Write) Back to Register Address Map Table 103. CTRL_REG3 register
1 The FIFO input buffer is blocked when transiti oning from WAKE to SLEEP mode or from SLEEP to WAKE
emptied by the host application.
6 WAKE_TRANS
1 Transient function interrupt can wake up system
5 WAKE_LNDPRT
1 Orientation function interrupt can wake up system
4 WAKE_PULSE
1 Pulse function interrupt can wake up system
3 WAKE_FF_MT
1 Freefall/Motion function interrupt can wake up
Selects the polarity of the interrupt signals. When IPOL is 0 (default value), any interrupt event is signaled with a logical 0.
0 ACTIVE low (default)
1 ACTIVE high
56 Freescale Semiconductor, Inc. CTRL_REG5 register maps the desired interrupts to INT2 or INT1 pins. routing table for the INT1 and INT2 interrupt pins.
- If the bit value is 0, then the functional block’s interrupt is routed to INT2.
- If the bit value is 1, then the function al block’s interrupt is routed to INT1. One or more functions can assert an interrupt pin; therefore a host application responding to an interrupt should read the INT_SOURCE (0x0C) register, to determine the appropriate sources of the interrupt.
0 PP_OD
Configures the interrupt pins to Push-Pull or to Open-Drain mode. The Open-Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line.
0 Push-Pull (default)
1 Open Drain
Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write) Back to Register Address Map Table 105. CTRL_REG4 register
7 INT_EN_ASLP Auto-SLEEP/WAKE Interrupt E nable 0 interrupt is disabled (default)
6 INT_EN_FIFO FIFO Interrupt Enable
5 INT_EN_TRANS Transient Interrupt Enable
4 INT_EN_LNDPRT Orientation (Landscape/Portrait) Interrupt Enable
3 INT_EN_PULSE Pulse Detection Interrupt Enable
2 INT_EN_FF_MT Freefall/Motion Interrupt Enable
0 INT_EN_DRDY Data Ready Interrupt Enable
Table 106. 0x2E: CTRL_REG5 Interrupt Configuration register Back to Register Address Map Table 107. 0x2E CTRL_REG5 register
7 INT_CFG_ASLP Auto-SLEEP/WAKE INT1/INT2 Configuration
0 Interrupt is routed to INT2 pin (default)
1 Interrupt is routed to INT1 pin
6 INT_CFG_FIFO FIFO INT1/INT2 Configuration
5 INT_CFG_TRANS Transient INT1/INT2 Configuration
4 INT_CFG_LNDPRT Orientation INT1/INT2 Configuration
3 INT_CFG_PULSE Pulse INT1/INT2 Configuration
2 INT_CFG_FF_MT Freefall/motion INT1/INT2 Configuration
0 INT_CFG_DRDY Data Ready INT1/INT2 Configuration
Table 103. CTRL_REG3 register (Continued)
6.13 Data calibration registers
in an offset compensation range ±250 mg for each axis. Table 108. 0x2F OFF_X register (Read/Write) Back to Register Address Map Table 109. OFF_X register Table 110. 0x30 OFF_Y register (Read/Write) Back to Register Address Map Table 111. OFF_Y register Table 112. 0x31 OFF_Z register (Read/Write) Back to Register Address Map Table 113. OFF_Z register
58 Freescale Semiconductor, Inc.
7 Mounting Guidelines
Surface mount printed circuit board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The MMA865xFC digital output accelerometers use the DFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications.
7.1 Overview of sold ering considerations
Information provided here is based on experiments executed on DFN devices. They do not represent exact conditions present at a customer site. Therefore, this information should be used as guidance only and process and design optimizations are recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process.
7.2 Halogen content
This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight.
7.3 PCB mounting/sold ering recommendations
- The PCB land should be designed as Non Solder Mask Defined (NSMD) as shown in Figure 16. 2. No additional via pattern underneath package. 3. PCB land pad is 0.6 mm x 0.225 mm as shown in Figure 16. 4. Solder mask opening = PCB land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm 6. Stencil thickness is 100 or 125 µm. 7. Do not place any components or vias at a distance le ss than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area. 8. Signal traces connected to pads are as symmetric as possi ble. Put dummy traces on NC pads, to have same length of exposed trace for all pads. 9. Use a standard pick and place process and equipment. Do not use a hand soldering process. 10. Use caution when putting an assembled PCB into an en closure, noting where the screw-down holes are and if any press-fitting is involved. It is important that the assembled PCB remain flat after assembly, to ensure optimal electronic operation of the device. 11. The PCB should be rated for the multiple lead- free reflow condition with max 260°C temperature. 12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale DFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices.
Figure 16. Package mounting measurements Table 114. Board mounting guidelines
60 Freescale Semiconductor, Inc.
8 Tape and Reel
8.1 Tape dimensions
Figure 17. Carrier tape
8.2 Device orientation
Figure 18. Device orientation on carrier tape
9 Package Dimensions
This drawing is located at http://cache.freescale.com/files/shared/doc/package_info/98ASA00301D.pdf. Figure 19. Case 98ASA00301D, 10-Lead DFN—page 1
62 Freescale Semiconductor, Inc. Figure 20. Case 98ASA00301D, 10-Lead DFN—page 2
Figure 21. Case 98ASA00301D, 10-Lead DFN—page 3
64 Freescale Semiconductor, Inc. Table 115. Revision history for MMA8652FC 0 10/2012 • Initial release. 1.0 12/2012 • Classification changed to Technical Data. 2.0 02/2013 • Feature comparison table: Orientation Detection features (2) rewritten for clarification.
- Section 1: Topics reordered for clarification and consistency. 3.0 06/2014
- Section 1.2: Updated Descriptions for Pins 3 and 4.
- Section 6.6.2: Updated Description for Field SEL[1:0] in Table 32.
- Section 6.12.2: Replace contents in Table 101. 3.2 03/2014 • Section 5.11: Updated paragraph before Table 11. 3.3 10/2015 • No technical changes - corrected format on page 49.
Document Number: MMA8652FC Rev. 3.3 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., respective owners. © 2015 Freescale Semiconductor, Inc.