MMA8652FC FREESCALE | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block Diagram and Pin Descriptions
- 1.1 Block diagram
- 1.2 Pin descriptions
- 1.3 Orientation definitions
- 1.4 Recommended application diagram
- 2 Mechanical and Electrical Specifications
- 2.1 Absolute maximum ratings
- 2.2 Mechanical characteristics
- 2.3 Electrical characteristics
- 2.4 I2C interface characteristics
- 3 Terminology
- 3.1 Sensitivity
- 3.2 Zero-g offset
- 3.3 Self-Test
- 4 Modes of Operation
- 5 Functionality
- 5.1 Device calibration
- 5.3 Internal FIFO data buffer
- 5.5 Auto-WAKE/SLEEP mode
- 5.6 Freefall and motion detection
- 5.7 Transient detection
- 5.8 Tap detection
- 5.9 Orientation detection
- 5.10 Interrupt register configurations
- 5.11 Serial I2C interface
- 6 Register Descriptions
- 6.1 Register quick jump table
- 6.2 Register address map
- 6.3 Register summary
- 6.4 Data registers
- 6.5 FIFO registers
- 6.6 System status and ID registers
- 6.7 Data configuration registers
- 6.8 Portrait/Landscape configuration and status registers
- 6.9 Freefall/Motion configuration and status registers
- 6.10 Transient configuration and status registers
- 6.11 Pulse configuration and status registers
- 6.12 Auto-WAKE/SLEEP register
- 6.13 System and control registers
- 6.14 Data calibration registers
- 7 Mounting Guidelines
- 7.1 Overview of soldering considerations
- 7.2 Halogen content
- 7.3 PCB mounting/soldering recommendations
- 8 Tape and Reel
- 8.1 Tape dimensions
- 8.2 Device orientation
- 9 Package Dimensions
- 10 Revision History
Features
- 1.95V to 3.6V supply voltage 1.62V to 3.6V digital interface voltage ±2g, ±4g, and ±8g dynamically selectable full-scale ranges Output Data Rates (ODR) from 1.56 Hz to 800 Hz 12-bit digital output 2C digital output interface with programmable interrupts Four embedded channels of configurable motion detection (Freefall, Motion, Pulse, Transient) Orientation (Portrait/Landscape) detection with programmable hysteresis Automatic ODR change triggered by the Auto-Wake / Sleep state change 32-sample FIFO High-Pass Filter Data available per sample and through the FIFO S e l f - T e s t Typical Applications eCompass applications tilt compensation Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/Front position identification) Notebook, eReader, and Laptop Tumble and Freefall Detection Real-time orientation detection (virtual reality and gaming 3D user position feedback) Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup) Motion detection for portable product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming) Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) User interface (menu scrolling by orientation change, tap detection for button replacement)
ORDERING INFORMATION
Part Number Temperature Range Package Description Shipping MMA8652FCR1 -40°C to +85°C DFN-10 Tape and Reel MMA8652FC Top View Pin Connections VDD SCL INT1 BYP INT2 SDA GND GND VDDIO GND MMA8652FC 10-PIN DFN 2 mm x 2 mm x 1 mm CASE 2162 Top and Bottom View
2 Freescale Semiconductor, Inc. Feature comparison of the MMA865xFC devices Feature List MMA8652FC MMA8653FC Digital Resolution (Bits) 12 10 Digital Sensitivity in 2g mode (Counts/g) 1024 256 Low-Power Mode Yes Yes Auto-WAKE Yes Yes Auto-SLEEP Yes Yes 32-Level FIFO Yes No Low-Pass Filter Yes Yes High-Pass Filter Yes No Transient Detection with High-Pass Filter Yes No Orientation Detection Portrait to Landscape = 30°, Landscape to Portrait = 60°, and Fixed 45° Threshold Yes Yes Programmable Orientation Detection Yes No Data-Ready Interrupt Yes Yes Single-Tap Interrupt Yes No Double-Tap Interrupt Yes No Directional Tap Interrupt Yes No Freefall Interrupt Yes Yes Motion Interrupt with Direction Yes No
4 Freescale Semiconductor, Inc.
1 Block Diagram and Pin Descriptions
1.1 Block diagram
Figure 1. Block diagram
32 Data Point
1.2 Pin descriptions
Figure 2. Direction of the detectable accelerations
1.3 Orientation definitions
orientation detection and are described in detail in the register setting section. Figure 3. Landscape/Portrait orientation
10 VDD
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1.4 Recommended application diagram
Figure 4. Application diagram Table 1. Pin descriptions
1 VDD Power supply
7-bit I2C device address is 0x1D. 2C connections are open drain, and therefore usually require a pullup resistor.
3 INT1 Interrupt 1 The interrupt source and pin settings are user-programmable through the I 2C
5 INT2 Interrupt 2 See INT1.
6 GND Ground
7 GND Ground
8 VDDIO Digital Interface Power supply
9 GND Ground
10 SDA I
are only needed for open-drain.
2 Mechanical and Electrical Specifications
2.1 Absolute maximum ratings
rating conditions for extended periods may affect device reliability. Table 2. Maximum ratings Table 3. ESD and latch-up protection characteristics cause the part to otherwise fail. This part is ESD-sensitive. I mproper handling can cause permanent damage to the part.
8 Freescale Semiconductor, Inc.
2.2 Mechanical characteristics
Table 4. Mechanical characteristics at VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted
- Post-board mount offset specifications ar e based on an 8-layer PCB, relative to 25°C.
- Self-Test is one direction only.
2 MHz Clock -20 +20 %
2.3 Electrical characteristics
Table 5. Electrical characteristics at VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted
- There is no requirement for power s upply sequencing. The VDDIO input voltage can be higher than the VDD input voltage.
10 Freescale Semiconductor, Inc.
2.4 I 2C interface characteristics
Figure 5. I2C slave timing
- Note that the first sample is typically not very precise; on ly the second or third or fourth sample (depending on ODR/MODS settings) has full
Table 6. I2C slave timing values(1)
- All values referred to VIH (min) and VIL (max) levels.
- This device does not stretch the LOW period (t LOW) of the SCL signal.
- t VD;DAT = time for Data signal from SCL LOW to SDA output.
- t VD;ACK = time for Acknowledgement signal from SCL LOW to SD A output (HIGH or LOW, depending on which one is worse).
- C b = total capacitance of one bus line in pF.
Freescale Semiconductor, Inc. 11
3 Terminology
3.1 Sensitivity
The sensitivity is represented in counts/g. In 2g mode, sensitivity = 1024 counts/g. In 4g mode, sensitivity = 512 counts/g. In 8g mode, sensitivity = 256 counts/g.
3.2 Zero-g offset
Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0g in X-axis and 0g in Y -axis, whereas the Z-axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT Registers 0x00, data expressed as a 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress on the MEMS sensor, and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
3.3 Self-Test
Self-T est can be used to verify the transducer and signal chain functionality without the need to apply external mechanical stimulus. When Self-T est is activated: An electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case, the sensor outputs w ill exhibit a change in their DC levels which, are related to the selected full scale through the device sensitivity . The device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force.
12 Freescale Semiconductor, Inc.
4 Modes of Operation
Figure 6. Operating modes for MMA8652FC how to transition between these modes, see Section 5, “Functionality”. Table 7. Operating modes The device is powered off. All analog and digital blocks are shutdown. Only digital blocks are enabled. Analog subsystem is disabled. All blocks are enabled (digital, analog).
5 Functionality
used to detect events and notify an external microprocessor over interrupt lines. the different functions. Separate application notes are available to help configure the device for each embedded functionality .
5.1 Device calibration
changing the default offset values. The user offset adjustments are stored in 3 volatile 8-bit registers (OFF_X, OFF_Y, OFF_Z). be set. When the F_READ bit is cleared, the fast read mode is disabled. (0.98mg) at 12-bits resolution. (1.96mg) at 12-bits resolution. If only the 8-bit results are used, then the resolution is reduced by a factor of 16. with the Sensor T oolbox demo board (LFSTBEB865xFC) with this application note. Table 8. Accelerometer 12-bit output data
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5.3 Internal FIFO data buffer
the data (up to 32 samples per axis). The FIFO can run at all output data rates. There are options for accessing the full 12-bit data or for accessing only the 8-bit data. When access speed is more important than high resolution, the 8-bit data read is a better option. Fill Buffer mode collects the first 32 samples and asserts the overflow flag when the buffer is full and another sample arrives. that the data must be flushed to analyze the event. samples after the event occurs. of samples has filled in the buffer (1 to 32). schemes of the data can activated when MODS = 10 in Register 0x2B, which will improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz. reduced. When MODS = 11, the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz.
5.5 Auto-WAKE/SLEEP mode
mode (lower current) when the device does not require higher sampling rates. may also interrupt the processor to transition from a SLEEP mode to a higher power mode. Table 9. Accelerometer 8-bit output data Table 8. Accelerometer 12-bit output data (Continued)
Freescale Semiconductor, Inc. 15 SLEEP mode occurs after the accelerometer has not detected an interrupt for longer than the user-definable timeout period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode, to save on current during this period of inactivity . The Interrupts that can WAKE the device from SLEEP are the following: T ap Detection, Orientation Detection, Motion/Freefall, and Transient Detection. The FIFO can be configured to hold the data in the buffer until it is flushed, if the FIFO Gate bit is set (in Register 0x2C) and if the FIFO cannot WAKE the device from SLEEP. The interrupts that can keep the device from falling asleep are the same interrupts that can wake the device—with the addition of the FIFO. If the FIFO interrupt is enabled and data is being accessed continually servicing the interrupt, then the device will remain in WAKE mode.
5.6 Freefall and motion detection
MMA8652FC has flexible interrupt architecture for detecting either a Freefall or a Motion. Freefall can be enabled where the set threshold must be less than the configured threshold. Motion can be enabled where the set threshold must be greater than the configured threshold. The motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset); the freefall configuration does not use the high-pass filter.
5.6.1 Freefall detection
The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user-specified threshold for a user-definable amount of time. The usable threshold ranges are normally between ±100 mg and ±500 mg.
5.6.2 Motion detection
Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold, the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2g. This condition would need to occur for a minimum of 100 ms to ensure that the event was not just noise. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for configurable set of time (like 100 ms or longer). To detect the direction of the motion, there is also directional data available in the source register. This is useful for applications such as directional shake or flick, which assists with the algorithm for various gesture detections.
5.7 Transient detection
The MMA8652FC has a built-in high pass filter. Acceleration data goes through the high pass filter, eliminating the offset (DC) and low frequencies. The high pass filter cutoff frequency can be set to 4 different frequencies, which depends on the Output Data Rate (ODR). A higher cutoff frequency ensures that the DC data (or slower moving data) will be filtered out, allowing only the higher frequencies to pass. The embedded Transient detection function uses the high-pass filtered data, allowing you to set the threshold and debounce counter. The transient detection feature can be used in the same manner as the motion detection feature, by bypassing the high-pass filter. There is an option in the configuration register to do this, which adds more flexibility to accommodate various use cases. Many applications use the accelerometer’s static acceleration readings (like tilt), which measure the change in acceleration due to gravity only . These functions benefit from acceleration data being filtered with a low-pass filter where high frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the acceleration. It is simpler to interpret these functions (which are dependent on dynamic acceleration data) when the static component has been removed. The Transient Detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 are the dedicated Transient Detection configuration registers. The source register contains directional data to determine the direction of the acceleration (either positive or negative).
5.8 Tap detection
The MMA8652FC has embedded single/double and directional tap detection.
16 Freescale Semiconductor, Inc. pulses. There are programmable thresholds for all three axes. more customizing and tunable tap detection schemes. The status register provides updates on the axes where the event was detected and the direction of the tap.
5.9 Orientation detection
configurable trip points. The embedded algorithm allows the selection of the mid-point with the desired hysteresis value. The MMA8652FC orientation detection algorithm confirms the reliability of the function with a configurable Z-lockout angle. the “Z-lockout angle”. The device operates down to 14° from the flat position. Figure 8 and Figure 9 show the definitions of the trip angles, going from landscape to portrait and then from portrait to landscape. Figure 7. Landscape/Portrait orientation Figure 8. Landscape to Portrait transition
Figure 9. Z-Tilt angle lockout transition
5.10 Interrupt regist er configurations
events, and Auto-SLEEP events. Figure 10. System interrupt generation simplifying data synchronization in the digital system that uses the device. functions of the device for Motion, Freefall, Transient, Orientation, and T ap.
5.11 Serial I 2C interface
2C serial interface (Table 10). VDDIO is present, then the MMA8652FC is in OFF mode—and communications on the I 2C interface are ignored. flat. This is user-configurable. routed to one of two interrupt pins.
18 Freescale Semiconductor, Inc. The I2C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards (Table 6).
- The transaction on the bus is started through a start condition (ST ART) signal. A ST ART condition is defined as a high-to-
- The next byte of data transmitted after ST ART contains the slave address in the first 7 bits, and the 8th bit tells whether
the Master is receiving data from the slave or is transmitting data to the slave.
- After a start condition and when an address is sent, each device in the system compares the first 7 bits with its address.
If the device’s address matches the sent address, then the device considers itself addressed by the Master.
- The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The
remains stable low during the high period of the acknowledge clock period.
- A Master may also issue a repeated ST ART during a data transfer. The MMA8652FC expects repeated ST ART s to be
used to randomly read from specific registers.
- A low-to-high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer
is always terminated by a STOP. addresses are available upon request.
5.11.1 Single byte read
- The transmission of an 8-bit command begins on the falling edge of SCL. After the 8 clock cycles are used to send the
diagram for the accelerometer 8-bit I2C read operation.
- The Master (or MCU) transmits a start condition (ST) to the MMA8652FC [slave address (0x1D), with the R/W bit set to
“0” for a write], and the MMA8652FC sends an acknowledgement.
- Next the Master (or MCU) transmits the address of the register to read, and the MMA8652FC sends an
- The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8652FC (0x1D), with the R/
W bit set to “1” for a read from the previously selected register.
- The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge
(NAK) the transmitted data, but transmits a stop condition to end the data transfer. Figure 11. Single Byte Read timing (I2C) Table 10. Serial Interface pins SDA is a bidirectional line used for sending and receiving the data to/from the interface. is free, both SCL and SDA lines are high. Table 11. I2C Device address sequence
For the following subsections, use the following legend.
5.11.2 Multiple byte read
- When performing a multi-byte read or “burst read”, the MMA8652FC automatically increments the received register
address commands after a read command is received.
- After following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each
- Until a no acknowledge (NAK) occurs from the Master,
- Followed by a stop condition (SP), which signals the end of transmission.
Figure 12. Multiple Byte Read timing (I2C)
5.11.3 Single byte write
- T o start a write command, the Master transmits a start condition (ST) to the MMA8652FC, slave address ($1D) with the
- The MMA8652FC sends an acknowledgement.
- Next the Master (MCU) transmits the address of the register to write to, and the MMA8652FC sends an
- Then the Master (or MCU) transmits the 8-bit data to write to the designated register, and the MMA8652FC sends an
condition (SP) to the data transfer. The data sent to the MMA8652FC is now stored in the appropriate register. Figure 13. Single Byte Write timing (I2C)
5.11.4 Multiple byte write
- After a write command is received, the MMA8652FC automatically increments the received register address
- Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers
after each MMA8652FC acknowledgment (ACK) is received.
20 Freescale Semiconductor, Inc. Figure 14. Multiple Byte Write timing (I2C)
6 Register Descriptions
6.1 Register quick jump table
6.2 Register address map
Click the blue register name to go to the register description. Table 12. Register address map
22 Freescale Semiconductor, Inc. 0x08 — — — — — — Reserved. Read return 0x00. (1)(4) R/W 0x11 0x12 10000000 0x80 Landscape/Portrait configuration. — — — — — — Reserved. Read return 0x00. Table 12. Register address map (Continued)
Auto-increment addresses that are not a simple increment are highlighted in bold.
- Register contents are preserved when a transi tion from ACTIVE to STANDBY mode occurs.
- Register contents are reset when a transit ion from STANDBY to ACTIVE mode occurs.
- Register contents can be modified at any ti me in either STANDBY or ACTIVE mode.
A write to this register will cause a reset of the corresponding internal system debounce counter.
- Register contents can only be modified while the device is in ST ANDBY mode; the only exceptions to this are the CTRL_REG1[ACTIVE] and
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6.3 Register summary
Table 13. MMA8652FC register summary
00 STATUS/F_STATUS Data Status R R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR
01 OUT_X_MSB 12-bit X Data R R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4
02 OUT_X_LSB 12-bit X Data R R XD3 XD2 XD1 XD0 0 0 0 0
03 OUT_Y_MSB 12-bit Y Data R R YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4
04 OUT_Y_LSB 12-bit Y Data R R YD3 YD2 YD1 YD0 0 0 0
05 OUT_Z_MSB 12-bit Z Data R R ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4
06 OUT_Z_LSB 12-bit Z Data R R ZD3 ZD2 ZD1 ZD0 0 0 0 0
09 F_SETUP FIFO Setup R/W R/W F_MODE1 F_MODE0 F_WMRK5 F_WMRK4 F_WMRK3 F_WMRK2 F_WMRK1 F_WMRK0
10 PL_STATUS PL Status R R NEWLP LO — — — LAPO[1] LAPO[0] BAFRO
11 PL_CFG PL Configuration R/W R/W DBCNTM PL_EN — — — — — —
12 PL_COUNT PL DEBOUNCE R/W R/W DBNCE[7] DBNCE[6] DB NCE[5] DBNCE[4] DBNCE[3] DBNCE[2] DBNCE[1] DBNCE[0]
13 PL_BF_ZCOMP PL Back/Front Z Comp
15 FF_MT_CFG Freefall/Motion Config
16 FF_MT_SRC Freefall/Motion Source
17 FF_MT_THS Freefall/Motion Threshold
18 FF_MT_COUNT Freefall/Motion Debounce
20 TRANSIENT_COUNT Transient Debounce
21 PULSE_CFG Pulse Config R/W R/W DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE
22 PULSE_SRC Pulse Source R R EA AxZ AxY AxX DPE Pol_Z Pol_Y Pol_X
23 PULSE_THSX Pulse X Threshold R/W R/W — THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0
24 PULSE_THSY Pulse Y Threshold R/W R/W — THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0
25 PULSE_THSZ Pulse Z Threshold R/W R/W — THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0
26 PULSE_TMLT Pulse First Timer R/W R/W TMLT7 TMLT6 TMLT5 TMLT4 TMLT3 TMLT2 TMLT1 TMLT0
27 PULSE_LTCY Pulse Latency R/W R/W LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0
28 PULSE_WIND Pulse 2nd Window
29 ASLP_COUNT Auto-SLEEP Counter
30 OFF_Y Y-axis 0g offset R/W R/W D7 D6 D5 D4 D3 D2 D1 D0
31 OFF_Z Z-axis 0g offset R/W R/W D7 D6 D5 D4 D3 D2 D1 D0
Table 13. MMA8652FC register summary (Continued)
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6.4 Data registers
MMA8652FC, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. real-time status information of the X, Y and Z sample data. register 0x01 (X_MSB) for either the 12-bit or 8-bit data. Z data overwrite and data ready flag. Figure 15. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only) Table 14. STATUS register bits Set whenever a new acceleration data is produced before completing the retrieval of the previous set .
0 No data overwrite has occurred (default)
Cleared whenever the OUT_ #_MSB register is read.
1 Previous Z-axis data was overwritten by new #-axis
Set when a new sample for any of the enabled channels is available.
0 No new set of data ready (default)
1 A new set of data is ready
Cleared whenever the OUT_# _MSB register is read.
0 No new # -axis data ready (default)
28 Freescale Semiconductor, Inc. — Reading the MSB register and then the LSB register in sequence ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the MSB and the LSB byte. If the FIFO is enabled (F_MODE > 00), then Register 0x01 points to the FIFO read pointer, while Registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read.
6.5 FIFO registers
Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. of samples stored in the buffer when the FIFO is enabled). or greater than then F_WMRK value. (even if the FIFO is full and overflows). If the FIFO overflow flag is set and F_MODE is = 11, then the FIFO has stopped accepting samples. Figure 22. 0x00 F_STATUS: FIFO STATUS register (Read-Only) Table 15. FIFO Flag Event 0 — No FIFO overflow events were detected. 1 — FIFO event was detected; the FIFO has overflowed. — 0 No FIFO watermark events were detected. If F_MODE = 11, then a Trigger Event was detected. Table 16. FIFO Sample Count register Indicates the number of acceleration samples currently stored in the FIFO buffer. 00_0001 to 10_0000 indicates that 1 to 32 samples are stored in the FIFO.
30 Freescale Semiconductor, Inc. mode can be switched between Fill mode, Circular mode, and Trigger mode. dictated by the selected system ODR. In ACTIVE mode, the ODR is set by the DR bits (CTRL_REG1 register). When Auto-SLEEP is active, the ODR is set by the ASLP_RA TE field (CTRL_REG1 register). byte read transaction to empty the FIFO. Figure 23. 0x09 F_SETUP: FIFO Setup register (Read/Write) Table 17. F_SETUP register
- Bit field can be written in ACTIVE mode.
- Bit field can be written in STANDBY mode.
01 FIFO contains the most recent samples when overflowed (circular buffer). The oldest sample is discarded and replaced by a new sample. 10 FIFO stops accepting new samples when overflowed. both before and after the trigger event, and it is definable by the watermark setting. SLEEP), or transitioning from STANDBY mode to ACTIVE mode. Disabling the FIFO (F_MODE = 00) resets the F_OVF, F_WMRK_FLAG, F_CNT to zero. sample count watermark (i.e., F_WMRK) asserts the F_WMRK_FLAG event flag. These bits set the number of FIFO samples required to trigger a watermark interrupt. A FIFO watermark event flag is raised when FIFO sample count F_CNT[5:0] ≥ F_WMRK[5:0] watermark. Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation. Also used to set the number of pre- trigger samples in Trigger mode.
The Trigger Configuration register configures which interrupt(s) may trigger the FIFO. Figure 24. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write) Table 18. Trigger Configuration register Trigger bits are reset by reading the appropriate source register.
1 This function can trigger the FIFO at its (the function’s) interrupt
0 This function has not asserted its interrupt.
4 Trig_LNDPRT
3 Trig_PULSE Pulse Interrupt Trigger 0
2 Trig_FF_MT Freefall/Motion Trigger 0
32 Freescale Semiconductor, Inc.
6.6 System status and ID registers
also indicates the status of the FIFO gate error and the number of samples since the gate error occurred. Figure 25. 0x0B SYSMOD: System Mode register (Read-Only) Table 19. SYSMOD register 1 FIFO Gate Error was detected. Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register. Interrupt Control register”. Number of ODR time units since FGERR was asserted . Reset when FGERR bit is cleared.
00 STANDBY mode (default)
01 WAKE mode
10 SLEEP mode
In the interrupt source register, the status of the various embedded features can be determined. The bits that are set (logic ‘1’) indicate which function has asserted an interrupt. The bits that are cleared (logic ‘0’) indicate which function has not asserted (or has deasserted) an interrupt. INT_SOURCE register bits are set by a low-to-high transition, and are cleared by reading the appropriate interrupt source register. cleared by simply reading the STATUS register (0x00), but is cleared by reading all the X, Y, and Z MSB data. Figure 26. 0x0C INT_SOURCE: System Interrupt Status register (Read Only) Table 20. INT_SOURCE register
7 SRC_ASLP
specified limit (ASLP_COUNT). This causes the system to transition to a user-specified low ODR setting. causing the system to transition to a user-specified high ODR setting. Reading the SYSMOD register clears the SRC_ASLP bit.
1 An interrupt event that can cause a WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition has
SRC_FIFO bit is cleared by reading the F_STATUS register. 1 A FIFO interrupt event (such as an overflow event or watermark) has occurred.
5 SRC_TRANS
SRC_TRANS bit is cleared by reading the TRANS_SRC register. 1A n acceleration transient value greater than user-specified threshold has occurred.
4 SRC_LNDPRT
SRC_LNDPRT bit is cleared by reading the PL_STATUS register. 1 An interrupt was generated due to a change in the device orientation status.
3 SRC_PULSE
SRC_PULSE bit is cleared by reading the PULSE_SRC register. 1 An interrupt was generated due to single and/or double pulse event.
2 SRC_FF_MT
SRC_FF_MT bit is cleared by reading the FF_MT_SRC register. 1 The Freefall/Motion function interrupt is active.
34 Freescale Semiconductor, Inc.
0 SRC_DRDY
SRC_DRDY bit is asserted when the ZYXOW and/or ZYXDR bit is set and the interrupt has been enabled. SRC_DRDY bit is cleared by reading the X, Y, and Z data. 1 The X, Y, Z data ready interrupt is active (indica ting the presence of new data and/or data overrun). Table 20. INT_SOURCE register (Continued)
part leaves the factory. For custom alternate values, contact Freescale. Figure 27. 0x0D: WHO_AM_I Device ID register (Read-Only)
36 Freescale Semiconductor, Inc.
6.7 Data configuration registers
is set, the FIFO and DATA registers both will contain high-pass filtered data.
000 H PF_OUT 0 0 F S1F S0
Figure 28. 0x0E: XYZ_DATA_CFG register (Read/Write) Table 21. XYZ Data Configuration register 1 Output data is high-pass filtered. and the high-pass filter is disabled. Table 22. Full Scale Range
application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers .
00 Pulse_HPF_BY Pulse_LPF_EN 0 0 SEL1 SEL0
Figure 29. 0x0F HP_FILTER_CUTOFF: High-Pass filter register (Read/Write) Table 23. High-Pass filter cutoff register
5 Pulse_HPF_BYP
0 HPF is enabled for pulse processing (default)
1 HPF is bypassed for pulse processing
4 Pulse_LPF_EN
0 LPF is disabled for pulse processing (default)
1 LPF is enabled for pulse processing
Table 24. High-Pass filter cutoff options
38 Freescale Semiconductor, Inc.
6.8 Portrait/Landscape configur ation and status registers
Manipulation and Basic Settings for Xt rinsic MMA865xFC Accelerometers . orientations, see Figure 3. The interrupt is cleared when reading the PL_STATUS register. The orientation mechanism state change is limited to a maximum 1.25g. LAPO, BAFRO, and LO continue to change when NEWLP is set. Figure 30. 0x10 PL_STATUS Register (Read-Only) Table 25. PL_STATUS register change in LO, BAFRO, or LAPO occurs. NEWLP bit is cleared anytime PL_STATUS register is read.
0 No change (default)
1 BAFRO and/or LAPO and/or Z-Tilt lockout value has changed
0 Lockout condition has not been detected (default)
1 Z-Tilt lockout trip angle has been exceeded.
- The default power-up state is BAFRO = 0, LAPO = 00, and LO = 0 .
00 Portrait Up: Equipment standing vertically in the normal orientation (default)
01 Portrait Down: Equipment standing vertically in the inverted orientation
10 Landscape Right: Equipment is in landscape mode to the right
11 Landscape Left: Equipment is in landscape mode to the left.
0 Front: Equipment is in the fr ont-facing orientation (default)
1 Back: Equipment is in the back-facing orientation
Figure 31. 0x11 PL_CFG register (Read/Write) Table 26. PL_CFG register 0 Decrements debounce whenever the condition of interest is no longer valid.
6 PL_EN
1 Portrait/Landscape Detection is enabled.
40 Freescale Semiconductor, Inc. transition from WAKE to SLEEP (or SLEEP to Wake) resets the internal Landscape/Portrait debounce counter. Figure 32. 0x12 PL_COUNT register (Read/Write) Table 27. PL_COUNT register Table 28. PL_COUNT relationship with the ODR
a range of 65° to 80° (with 5° step increments). Figure 33. 0x13: PL_BF_ZCOMP register (Read/Write) Table 29. PL_BF_ZCOMP register All angles are accurate to ±2°. Table 30. Z-lock threshold angles Table 31. Back/Front orientation definitions
00 Z < 80° or Z > 280° Z > 100° and Z < 260°
01 Z < 75° or Z > 285° Z > 105° and Z < 255°
10 Z < 70° or Z > 290° Z > 110° and Z < 250°
11 Z < 65° or Z > 295° Z > 115° and Z < 245°
42 Freescale Semiconductor, Inc. to Landscape mode and from Landscape to Portrait mode. This register includes a value for the hysteresis. and from landscape to portrait. The default trip angle is 45° (0x10). The default hysteresis is ±14°. Figure 34. 0x14: P_L_THS_REG register (Read/Write) Table 32. P_L_THS_REG register from portrait to landscape and landscape to portrait. This angle ranges from 0° to ±24°. Table 33. Threshold angle thresholds look-up table Table 34. Trip angles with hysteresis for 45° angle
Freescale Semiconductor, Inc. 43
6.9 Freefall/Motion configur ation and status registers
The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15: FF_MTG_CFG, bit 6). The freefall/motion detection block can be disabled by setting all three bits ZEFE, YEFE, and XEFE to zero. Depending on the register bits ELE (0x15: FF_MTG_CFG, bit 7) and OAE (0x15: FF_MTG_CFG, bit 6), each of the freefall and motion detection block can operate in four different modes.
6.9.1 Motion and freefall modes
6.9.1.1 Mode 1: Freefall detection with ELE = 0, OAE = 0
In this mode, the EA bit (0x16: FF_MTG_CFG, bit 7) indicates a freefall event after the debounce counter is complete. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. Once the EA bit is set, and DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. This is because the counter is in decrement mode. If DBCNTM = 1, then the EA bit is cleared as soon as the freefall condition disappears, and will not be set again before the delay specified by FF_MT_COUNT has passed. Reading the FF_MT_SRC register does not clear the EA bit. The event flags (0x16) ZHE, ZHP, YHE, YHP , XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set.
6.9.1.2 Mode 2: Freefall detection with ELE = 1, OAE = 0
In this mode, the EA event bit indicates a freefall event after the debounce counter . Once the debounce counter reaches the time value for the set threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, the EA bit and the debounce counter are cleared, and a new event can only be generated after the delay specified by FF_MT_CNT. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. While EA = 0, the event flags ZHE, ZHP, YHE, YHP , XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. The event flags ZHE, ZHP , YHE, YHP, XHE, and XHP are latched when the EA event bit is set. The event flags ZHE, ZHP, YHE, YHP , XHE, and XHP will start changing only after the FF_MT_SRC register has been read.
6.9.1.3 Mode 3: Motion detection with ELE = 0, OAE = 1
In this mode, the EA bit indicates a motion event after the debounce counter time is reached . The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the EA bit is set and if DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. If DBCNTM = 1, then the EA bit is cleared as soon as the motion high g condition disappears. The event flags ZHE, ZHP , YHE, YHP , XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Reading the FF_MT_SRC does not clear any flags, nor is the debounce counter reset.
6.9.1.4 Mode 4: Motion detection with ELE = 1, OAE = 1
In this mode, the EA bit indicates a motion event after debouncing . The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the debounce counter reaches the threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, all register bits are cleared and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT. While the bit EA is zero, the event flags ZHE, ZHP , YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. When the EA bit is set, these bits (ZHE, ZHP, YHE, YHP , XHE, XHP) keep their current value until the FF_MT_SRC register is read.
44 Freescale Semiconductor, Inc. This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. Figure 36. FF_MT_CFG high and low g level Figure 35. 0x15 FF_MT_CFG register (Read/Write) Table 35. FF_MT_CFG register Event Latch Enable: Event flags are latched into FF_MT_SRC register. status in the FF_MT_SRC will indicate the real-time status of the event. reading the FF_MT_SRC source register. Reading the FF_MT_SRC register clears the event flag EA and all FF_MT_SRC bits.
0 Event flag latch disabled (default)
1 Event flag latch enabled
Selects between Motion (logical OR combination) and Freefall (logical AND combination) detection.
0 Freefall flag (Logical AND combination) (default)
1 Motion flag (Logical OR combination)
the threshold set in FF_MT_THS register.
0 Event detection disabled (default)
1 Raise event flag on measured acceleration value beyond preset threshold
the threshold set in FF_MT_THS register. the threshold set in FF_MT_THS register.
INT_CFG_FF_MT register bits to generate the freefall/motion interrupts. defined in the FF_MT_THS register. threshold value defined in the FF_MT_THS register. Figure 37. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only) Table 36. Freefall/Motion Source register
0 No event flag has been asserted (default)
1 One or more event flags has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. ZHE bit always reads zero if the ZEFE control bit is set to zero.
0 No Z motion event detected (default)
1 Z motion has been detected
ZHP bit always reads zero if the ZEFE control bit is set to zero.
0 Z event was positive g (default)
1 Z event was negative g
YHE bit always reads zero if the YEFE control bit is set to zero.
0 No Y motion event detected (default)
1 Y motion has been detected
YHP bit always reads zero if the YEFE control bit is set to zero.
0 Y event detected was positive g (default)
1 Y event was negative g
XHE bit always reads zero if the XEFE control bit is set to zero.
0 No X motion event detected (default)
1 X motion has been detected
XHP bit always reads zero if the XEFE control bit is set to zero.
0 X event was positive g (default)
1 X event was negative g
46 Freescale Semiconductor, Inc. FF_MT_THS is the threshold register used to detect freefall motion events. the X and Y and Z acceleration values is lower or equal than the threshold value. acceleration value is higher than the threshold value. The threshold resolution is 0.063g/LSB and the threshold register has a range of 0 to 127 counts. The maximum range is to 8g. Note that even when the full scale value is set to 2g or 4g, the motion still detects up to 8g. longer true (Figure 40, (c)) until the debounce counter reaches 0 or until the inertial event of interest becomes active. impede the detection of inertial events). Figure 38. 0x17 FF_MT_THS register (Read/Write) Table 37. FF_MT_THS register
0 Increments or decrements debounce (default)
1 Increments or clears counter.
The Debounce register sets the number of debounce sample counts for the event trigger. selected by you for the freefall/motion event. the ODR chosen and the Oversampling mode, as shown in Table 39. Figure 39. 0x18 FF_MT_COUNT register (Read/Write) Table 38. FF_MT_COUNT register Table 39. FF_MT_COUNT relationship with the ODR
48 Freescale Semiconductor, Inc. Figure 40. DBCNTM bit function
6.10 Transient configuratio n and status registers
detection function, except that high-pass filtered data is compared. detection. This allows for the device to have two motion detection functions. filter is bypassed, the function behaves similar to the motion detection. Figure 41. 0x1D TRANSIENT_CFG register (Read/Write) Table 40. TRANSIENT_CFG register Reading of the TRANSIENT_SRC register clears the event flag.
3 ZTEFE Event flag enable for Z-transient acceleration greater than a
1 Raise event flag on measured acceleration delta
value that is greater than a transient threshold.
2 YTEFE Event flag enable for Y-transient acceleration greater than a
1 XTEFE Event flag enable for X-transient acceleration greater than
a transient threshold event.
0 Data to transient acceleration detection block is through HPF
1 Data to transient acceleration detection block is NOT through
50 Freescale Semiconductor, Inc. TRANSIENT_SRC register is read, it clears the interrupt for the transient detection. updated. However no *TRANSE bit may get cleared before the TRANSIENT_SRC register is read. When the EA bit gets set while ELE = 1, all other status bits get frozen at their current state. By reading the TRANSIENT_SRC register, all bits get cleared. Figure 42. 0x1E TRANSIENT_SRC register (Read-Only) Table 41. TRANSIENT_SRC register 1 One or more event flags has been asserted.
5 ZTRANSE
0 No interrupt (default)
1 Z transient acceleration greater than the value of TRANSIENT_THS event has occurred
4 Z_Trans_Pol
1 Y transient acceleration greater than the value of TRANSIENT_THS event has occurred
2 Y_Trans_Pol
0 Y event was Positive g (default)
1 X transient acceleration greater than the value of TRANSIENT_THS event has occurred
0 X_Trans_Pol
pass filtered acceleration value exceeds the threshold limit, an event flag is raised and the interrupt is generated (if enabled). Figure 43. 0x1F TRANSIENT_THS register (Read/Write) Table 42. TRANSIENT_THS register
1 Increments or clears counter
A 7-bit unsigned number, with 0.063g/LSB. The maximum threshold is 8g. will still operate up to 8g.
52 Freescale Semiconductor, Inc. unsigned value of high-pass filtered data is greater than the user-specified value of TRANSIENT_THS. The time step for the transient detection debounce counter is set by the value of the system ODR and the Oversampling mode. Figure 44. 0x20 TRANSIENT_COUNT register (Read/Write) Table 43. TRANSIENT_COUNT register Table 44. TRANSIENT_COUNT relationship with the ODR
6.11 Pulse configuration and status registers
Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. The tap detection registers are referred to as “Pulse”. Figure 45. 0x21 PULSE_CFG register (Read/Write) Table 45. PULSE_CFG register
0 Double Pulse detection is not aborted if the start of a pulse is detected during
1 Setting the DPA bit momentarily suspends the double tap detection if the
specified by the PULSE_LTCY register. 6E L E Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag.
0 Event detection is disabled (default)
1 Event detection is enabled
4 ZSPEFE Event flag enable for a single pulse event on Z-axis
2 YSPEFE Event flag enable for a single pulse event on Y-axis
0 XSPEFE Event flag enable for a single pulse event on X-axis
54 Freescale Semiconductor, Inc. axis and event must be enabled in register 0x21 for the event flag to be asserted in the source register. When the EA bit gets set while ELE = 1, all status bits (AxZ, AxY, AxZ, DPE, and PolX, PolY , PolZ) are frozen. Reading the PULSE_SRC register clears all bits. Reading the source register will clear the interrupt. Figure 46. 0x22 PULSE_SRC register (Read-Only) Table 46. PULSE_SRC register
0 No interrupt has been generated (default)
1 One or more interrupt events have been generated
1 Z-axis event has occurred
1 Y-axis event has occurred)
1 X-axis event has occurred
0 Single pulse event triggered interrupt (default)
1 Double pulse event triggered interrupt
0 Pulse event that triggered interrupt was positive (default)
1 Pulse event that triggered interrupt was negative)
1 Pulse event that triggered interrupt was negative
registers define the threshold that is used by the system to start the pulse detection procedure. resolution is always fixed at 0.063g/LSB. the pulse detection procedure. The threshold value is expressed over 7-bits as an unsigned number.
0 THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0
Figure 47. 0x23 PULSE_THSX register (Read/Write) Table 47. PULSE_THSX register
0 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0
Figure 48. 0x24 PULSE_THSY register (Read/Write) Table 48. PULSE_THSY register
7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0
Figure 49. 0x25 PULSE_THSZ register (Read/Write) Table 49. PULSE_THSZ register
56 Freescale Semiconductor, Inc. to be considered a valid pulse. The minimum time step for the pulse time limit is defined in Table 51 and Table 52. Maximum time for a given ODR and Oversampling mode is the time step pulse multiplied by 255. The pulse low-pass filter is set in Register 0x0F. Figure 50. 0x26 PULSE_TMLT register (Read/Write) Table 50. PULSE_TMLT register Table 51. Time Step for PULSE time limit (Reg 0x0F) Pulse_LPF_EN = 1 Table 52. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0
Bits LTCY7 – LTCY0 define the time interval that starts after the first pulse detection. During this time interval, all pulses are ignored. This timer must be set for single pulse and for double pulse. The minimum time step for the pulse latency is defined in Table 54 and Table 55. The maximum time is the time step at the ODR and Oversampling mode multiplied by 255. The timing also changes when the Pulse LPF is enabled or disabled. Figure 51. 0x27 PULSE_LTCY register (Read/Write) Table 53. PULSE_LTCY register Table 54. Time Step for PULSE Latency at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 55. Time Step for PULSE Latency at ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0
58 Freescale Semiconductor, Inc. double pulse need not finish within the time specified by the PULSE_WIND register. oversampling mode and LPF filter option multiplied by 255. Figure 52. 0x28: PULSE_WIND Second Pulse Time Window register Table 56. PULSE_WIND register Table 57. Time Step for PULSE Detection window at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 58. Time Step for PULSE Detection window at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 0
6.12 Auto-WAKE/SLEEP register
Wake ODR is set by CTRL_REG1[DR] bits. Sleep ODR is set by CTRL_REG1[ASLP_RATE] bits. Auto WAKE/SLEEP function is enabled by asserting the CTRL_REG2[SLPE] bit. maximum value depend on the ODR chosen (as shown in Table 60). For functional blocks that may be monitored for inactivity (to trigger the “return to SLEEP” event), see Table 61. Figure 53. 0x29 ASLP_COUNT register (Read/Write) Table 59. ASLP_COUNT register Table 60. ASLP_COUNT relationship with ODR
200 Hz 0 to 81 5 320
100 Hz 0 to 81 10 320
50 Hz 0 to 81 20 320
12.5 Hz 0 to 81 80 320
6.25 Hz 0 to 81 160 320
1.56 Hz 0 to 162 640 640
Table 61. SLEEP/WAKE mode gates and triggers
60 Freescale Semiconductor, Inc. — All enabled functions still run in SLEEP mode at the SLEEP ODR. Only the functions that have been selected for WAKE from SLEEP will actually WAKE the device (as configured in register 0x2C). — Note that the FIFO does not WAKE the device. — The Auto-WAKE/SLEEP interrupt does not affect the WAKE/SLEEP , nor does the data ready interrupt. — When set to 1, the FIFO gate (bit 7 in Register 0x2C) will hold the last data in the FIFO, before transitioning to a different ODR. After the buffer is flushed, it will accept new sample data at the current ODR. See Register 0x2C for the WAKE-from-SLEEP interrupt enable bit definitions. MMA8652FC has 4 functions that can be used to keep the sensor from falling asleep: Transient, Orientation, T ap and Motion/ Freefall. Auto-SLEEP bit: — If the Auto-SLEEP bit is disabled, then the device can only toggle between STANDBY and WAKE mode. — If Auto-SLEEP interrupt is enabled, then transitioning from ACTIVE mode to Auto-SLEEP mode (or vice versa) generates an interrupt.
6.13 System and control registers
of the fields within CTRL_REG1 (0x2A). and STANDBY/ACTIVE mode selection. Figure 54. 0x2A CTRL_REG1 register (Read/Write) Table 62. CTRL_REG1 register Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode .
0 Normal mode (default)
1 Fast Read Mode
0 STANDBY mode (default)
1 ACTIVE mode
Table 63. SLEEP mode rates rate set by the ASLP_RATE field. Table 64. System output data rate selection
62 Freescale Semiconductor, Inc. The ACTIVE bit selects between STANDBY mode and ACTIVE mode. The F_Read bit selects between normal and Fast Read mode. When selected, the auto-increment counter will skip over the LSB data bytes. Data read from the FIFO will skip over the LSB data, reducing the acquisition time. Note that F_READ can only be changed when FMODE = 00. The F_READ bit applies for both the output registers and the FIFO. Table 65. Full-Scale selection using ACTIVE bit
0 STANDBY (default)
SLEEP and WAKE mode power scheme selection (oversampling modes). resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP , or STANDBY mode. The I2C communication system is reset to avoid accidental corrupted data access. At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero. available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0]. Figure 55. 0x2B CTRL_REG2 register (Read/Write) Table 66. CTRL_REG2 register Activates the self-test function. When ST is set, the X, Y, and Z outputs will shift.
0 Self-Test disabled (default)
1 Self-Test enabled
RST bit is used to activate the software reset. The reset mechanism is enabled in both STANDBY and ACTIVE modes.
0 Device reset disabled (default)
0 Auto-SLEEP is not enabled (default)
Table 67. (S)MODS Oversampling modes Table 68. MODS Oversampling modes averaging values at each ODR
1.56 Hz TBD 128 TBD 32 TBD 1024 TBD 16
50 Hz TBD 4 TBD 4 TBD 32 TBD 2
64 Freescale Semiconductor, Inc. Current values will be added at a later date.
100 Hz TBD 4 TBD 4 TBD 16 TBD 2
200 Hz TBD 4 TBD 4 TBD 8 TBD 2
400 Hz TBD 4 TBD 4 TBD 4 TBD 2
800 Hz TBD 2 TBD 2 TBD 2 TBD 2
Table 68. MODS Oversampling modes averaging values at each ODR (Continued)
interrupt to wake. CTRL_REG3 register also configures the interrupt pins INT1 and INT2. Figure 56. 0x2C CTRL_REG3 register (Read/Write) Table 69. CTRL_REG3 register
7 FIFO_GATE
1 The FIFO input buffer is blocked when transitioning from WAKE to SLEEP mode or from SL EEP to WAKE
emptied by the host application.
6 WAKE_TRANS
1 Transient function interrupt can wake up system
5 WAKE_LNDPRT
1 Orientation function interrupt can wake up system
4 WAKE_PULSE
1 Pulse function interrupt can wake up system
3 WAKE_FF_MT
1 Freefall/Motion function interrupt can wake up
Selects the polarity of the interrupt signal. When IPOL is 0 (default value), any interrupt event is signaled with a logical 0.
0 ACTIVE low (default)
1 ACTIVE high
0 PP_OD
Configures the interrupt pin to Push-Pull or to Open-Drain mode. The Open-Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line.
0 Push-Pull (default)
1 Open Drain
66 Freescale Semiconductor, Inc. Figure 57. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write) Table 70. CTRL_REG4 register
7 INT_EN_ASLP Auto-SLEEP/WAKE Interrupt Enable 0 interrupt is disabled (default)
4 INT_EN_LNDPRT Orientation (Landscape/Portrait) Interrupt Enable
3 INT_EN_PULSE Pulse Detection Interrupt Enable
2 INT_EN_FF_MT Freefall/Motion Interrupt Enable
0 INT_EN_DRDY Data Ready Interrupt Enable
CTRL_REG5 register maps the desired interrupts to INT2 or INT1 pins. the routing table for the INT1 and INT2 interrupt pins. If the bit value is 0, then the functional block’s interrupt is routed to INT2. If the bit value is 1, then the functional block’s interrupt is routed to INT1. INT_SOURCE (0x0C) register, to determine the appropriate sources of the interrupt. Figure 58. 0x2E: CTRL_REG5 Interrupt Configuration register Table 71. 0x2E CTRL_REG5 register
7 INT_CFG_ASLP Auto-SLEEP/WAKE INT1/INT2 Configuration
0 Interrupt is routed to INT2 pin (default)
1 Interrupt is routed to INT1 pin
4 INT_CFG_LNDPRT Orientation INT1/INT2 Configuration
0 INT_CFG_DRDY Data Ready INT1/INT2 Configuration
68 Freescale Semiconductor, Inc.
6.14 Data calibration registers
in an offset compensation range ±250 mg for each axis. Figure 59. 0x2F OFF_X register (Read/Write) Table 72. OFF_X register Figure 60. 0x30 OFF_Y register (Read/Write) Table 73. OFF_Y register Figure 61. 0x31 OFF_Z register (Read/Write) Table 74. OFF_Z register
Freescale Semiconductor, Inc. 69
7 Mounting Guidelines
Surface mount printed circuit board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The MMA865xFC digital output accelerometers use the DFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications.
7.1 Overview of soldering considerations
Information provided here is based on experiments executed on DFN devices. They do not represent exact conditions present at a customer site. Therefore, this information should be used as guidance only and process and design optimizations are recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process.
7.2 Halogen content
This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight.
7.3 PCB mounting/soldering recommendations
- The PCB land should be designed as Non Solder Mask Defined (NSMD) as shown in Figure 62. 2. No additional via pattern underneath package. 3. PCB land pad is 0.6 mm x 0.225 mm as shown in Figure 62. 4. Solder mask opening = PCB land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm 6. Stencil thickness is 100 or 125 um. 7. Do not place any components or vias at a distance less than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area. 8. Signal traces connected to pads are as symmetric as possible. Put dummy traces on NC pads, to have same length of exposed trace for all pads. 9. Use a standard pick and place process and equipment. Do not use a hand soldering process. 10. Use caution when putting an assembled PCB into an enclosure, noting where the screw-down holes are and if any press-fitting is involved. It is important that the assembled PCB remain flat after assembly, to ensure optimal electronic operation of the device. 11. The PCB should be rated for the multiple lead-free reflow condition with max 260°C temperature. 12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale DFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices.
70 Freescale Semiconductor, Inc. Figure 62. Package mounting measurements Table 75. Board mounting guidelines
8 Tape and Reel
8.1 Tape dimensions
Figure 63. Carrier tape
8.2 Device orientation
Figure 64. Device orientation on carrier tape
72 Freescale Semiconductor, Inc.
9 Package Dimensions
Figure 65. CASE 2162-02, ISSUE O, 10-Lead DFN—page 1
Figure 66. CASE 2162-02, ISSUE O, 10-Lead DFN—page 2
74 Freescale Semiconductor, Inc. Figure 67. CASE 2162-02, ISSUE O, 10-Lead DFN—page 3
Figure 68. CASE 2162-02, ISSUE O, 10-Lead DFN—page 4
76 Freescale Semiconductor, Inc. Table 76. Revision history
Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C- Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Document Number: MMA8652FC Rev. 0