MMA8452QT

MMA8452Q FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• 1.95V to 3.6V supply voltage
• 1.6V to 3.6V interface voltage
• ±2g/±4g/±8g dynamicall y selectable full-scale
• Output Data Rates (ODR) from 1.56 Hz to 800 Hz
• 99 μg/√Hz noise
• 12-bit and 8-bit digital output 2C digital output interface
• Two programmable interrupt pins for six interrupt sources
• Three embedded channels of motion detection — Freefall or Motion Detection: 1 channel — Pulse Detection: 1 channel — Transient Detection: 1 channel – Orientation (Portrait/Landscape) detection with set hysteresis – Automatic ODR change for Auto-WAKE and return to SLEEP – High-Pass Filter Data available real-time –S e l f - T e s t – RoHS compliant – Current Consumption: 6 μA – 165 μA Typical Applications
• eCompass applications
• Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/ Front position identification)
• Notebook, eReader and Laptop Tumble and Freefall Detection
• Real-time orientation detection (virtual reality and gaming 3D user position feedback)
• Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)
• Motion detection for portab le product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)
• Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)
• User interface (menu scrolling by orientation change, pulse detection for button replacement)

ORDERING INFORMATION

Part Number Temperature Range Package Description Shipping MMA8452QT -40°C to +85°C QFN-16 Tray MMA8452QR1 -40°C to +85°C QFN-16 Tape and Reel MMA8452Q

16 PIN QFN

2 Freescale Semiconductor, Inc. Related Documentation The MMA8452Q device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at: http://www.freescale.com/ 2. In the Keyword search box at the top of the page, enter the device number MMA8452Q. 3. In the Refine Your Result pane on the left, click on the Documentation link.

Contents

1 Block Diagram and Pin Description

Figure 1. Block Diagram Figure 2. Direction of the Detectable Accelerations

single 4.7 µF ceramic) should be placed as near as possible to the pins 1 and 14 of the device. signals SCL, SDA, and SA0 will clamp any logic signals with their internal ESD protection diodes.

1.1 Soldering Information

The QFN package is compliant with the RoHS standard. Please refer to AN4077. Table 1. Pin Descriptions

7 SA0 I2C Least Significant Bit of the Device I2C Address Input

10 GND Connect to Ground Input

11 INT1 Inertial Interrupt 1 Output

12 GND Connect to Ground Input

13 NC Internally not connected (can be GND or VDD) Input

15 NC Internally not connected (can be GND or VDD) Input

16 NC Internally not connected (can be GND or VDD) Input

6 Freescale Semiconductor, Inc.

2 Mechanical and Electr ical Specifications

2.1 Mechanical Characteristics

Table 2. Mechanical Characteristics @ VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted.

1. Dynamic Range is limited to 4g when the Low-Noise bit in Register 0x2A, bit 2 is set.
2. Sensitivity remains in spec as stated, but changing Oversampling mode to Low Power causes 3% sensitivity shift. This behavior is also seen

when changing from 800 Hz to any other data rate in the Normal, Low Noise + Low Power or High Resolution mode.

1. Post Board Mount Offset Specifications are based on an 8 Layer PCB, relative to 25°C.
2. Self-Test is one direction only.

2 MHz Clock ±2 %

2.2 Electrical Characteristics

Table 3. Electrical Characteristics @ VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted.

1. There is no requirement for power supply sequencing. The VDDIO input voltage can be higher than the VDD input voltage.
2. Note that the first sample is typically not very precise. Depending on ODR/MODS settings, a minimum of three samples is recommended for

8 Freescale Semiconductor, Inc.

2.3 I 2C Interface Characteristics

Table 4. I2C Slave Timing Values(1)

1. All values referred to VIH (min) and VIL (max) levels.
2. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
3. The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard mode and Fast mode, but must be less than the maximum of tVD;DAT or tVD;ACK
4. tVD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
5. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
6. A Fast mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will
7. Cb = total capacitance of one bus line in pF.
8. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.

Figure 5. I2C Slave Timing Diagram

2.4 Absolute Maximum Ratings

maximum rating conditions for extended periods may affect device reliability. Table 5. Maximum Ratings Table 6. ESD and Latchup Protection Characteristics cause the part to otherwise fail. This device is sensitive to ESD, improper handling can cause permanent damage to the part.

10 Freescale Semiconductor, Inc.

3 Terminology

3.1 Sensitivity

512 counts/g and in 8g mode the sensitivity is 256 counts/g.

3.2 Zero-g Offset

extensive mechanical stress.

3.3 Self-Test

4 Modes of Operation

Figure 6. MMA8452Q Mode Transition Diagram these modes please refer to the functionality section of this document. Table 7. Mode of Operation Description are shutdown. I2C bus inhibited. Only digital blocks are enabled. Analog subsystem is disabled. Internal clocks disabled. All blocks are enabled (digital, analog).

5 Functionality

• 8-bit or 12-bit data which includes High-Pass Filtered data
• 4 different oversampling options for compromising between resolution and current consumption based on application requirements
• Additional Low-Noise mode that functions independently of the Oversampling modes for higher resolution
• Low-Power and Auto-WAKE/SLEEP for conservation of current consumption
• Single-/Double-pulse with directional information 1 channel
• Motion detection with directional information or Freefall 1 channel
• Transient detection based on a high-pass filter and settable threshold for detecting the change in acceleration above a threshold with directional information 1 channel
• Portrait/Landscape detection with trip points fixed at 30° and 60° for smooth transitions between orientations. All functionality is available in 2g, 4g or 8g dynamic ranges. There are many configuration settings for enabling all the different functions. Separate application notes have been provided to help configure the device for each embedded functionality .

Table 8. Features of the MMA845xQ devices

32 Level FIFO Yes No No

12 Freescale Semiconductor, Inc.

5.1 Device Calibration

The device interface is factory calibrated for sensitivity and Zero-g offset for each axis. The trim values are stored in Non Volatile Memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry . In normal use, further calibration in the end application is not necessary . However, the MMA8452Q allows the user to adjust the Zero-g offset for each axis after power-up, changing the default offset values. The user offset adjustments are stored in 6 volatile registers. For more information on device calibration, refer to Freescale application note, AN4069. 5.2 8-bit or 12-bit Data The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 12-bit numbers. The most significant 8-bits of each axis are stored in OUT_X (Y, Z)_MSB, so applications needing only 8-bit results can use these 3 registers and ignore OUT_X,Y, Z_LSB. To do this, the F_READ bit in CTRL_REG1 must be set. When the F_READ bit is cleared, the fast read mode is disabled. When the full-scale is set to 2g, the measurement range is -2g to +1.999g, and each count corresponds to 1g/1024 (1 mg) at 12-bits resolution. When the full-scale is set to 8g, the measurement range is -8g to +7.996g, and each count corresponds to 1g/256 (3.9 mg) at 12-bits resolution. The resolution is reduced by a factor of 16 if only the 8-bit results are used. For more information on the data manipulation between data formats and modes, refer to Freescale application note, AN4076. There is a device driver available that can be used with the Sensor T oolbox demo board (LFSTBEB8451, 2, 3Q) with this application note. 5.3 Low-Power Modes vs. High-Resolution Modes The MMA8452Q can be optimized for lower power modes or for higher resolution of the output data. High resolution is achieved by setting the LNOISE bit in Register 0x2A. This improves the resolution but be aware that the dynamic range is limited to 4g when this bit is set. This will affect all internal functions and reduce noise. Another method for improving the resolution of the data is by oversampling. One of the oversampling schemes of the data can activated when MODS = 10 in Register 0x2B which will improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz. There is a trade-off between low power and high resolution. Low Power can be achieved when the oversampling rate is reduced. When MODS = 11 the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz. For more information on how to configure the MMA8452Q in Low-Power mode or High-Resolution mode and to realize the benefits, refer to Freescale application note, AN4075.

5.4 Auto-WAKE/SLEEP Mode

The MMA8452Q can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. The advantage of using the Auto-WAKE/SLEEP is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the SLEEP mode (lower current) when the device does not require higher sampling rates. Auto-WAKE refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This may also interrupt the processor to transition from a SLEEP mode to a higher power mode. SLEEP mode occurs after the accelerometer has not detected an interrupt for longer than the user definable time-out period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save on current during this period of inactivity . The Interrupts that can WAKE the device from SLEEP are the following: Pulse Detection, Orientation Detection, Motion/Freefall, and Transient Detection. Refer to AN4074, for more detailed information for configuring the Auto-WAKE/SLEEP.

5.5 Freefall and Motion Detection

MMA8452Q has flexible interrupt architecture for detecting either a Freefall or a Motion. Freefall can be enabled where the set threshold must be less than the configured threshold, or motion can be enabled where the set threshold must be greater than the threshold. The motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset). The freefall does not use the high-pass filter. For details on the Freefall and Motion detection with specific application examples and recommended configuration settings, refer to Freescale application note AN4070.

5.5.1 Freefall Detection

The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user specified threshold for a user definable amount of time. Normally the usable threshold ranges are between ±100 mg and ±500 mg.

Freescale Semiconductor, Inc. 13

5.5.2 Motion Detection

Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2g. This condition would need to occur for a minimum of 100 ms to ensure that the event wasn't just noise. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for configurable set of time (i.e., 100 ms or longer). There is also directional data available in the source register to detect the direction of the motion. This is useful for applications such as directional shake or flick, which assists with the algorithm for various gesture detections.

5.6 Transient Detection

The MMA8452Q has a built-in high-pass filter. Acceleration data goes through the high-pass filter, eliminating the offset (DC) and low frequencies. The high-pass filter cutoff frequency can be set by the user to four different frequencies which are dependent on the Output Data Rate (ODR). A higher cutoff frequency ensures the DC data or slower moving data will be filtered out, allowing only the higher frequencies to pass. The embedded Transient Detection function uses the high-pass filtered data allowing the user to set the threshold and debounce counter. The Transient detection feature can be used in the same manner as the motion detection by bypassing the high-pass filter. There is an option in the configuration register to do this. This adds more flexibility to cover various customer use cases. Many applications use the accelerometer’s static acceleration readings (i.e., tilt) which measure the change in acceleration due to gravity only . These functions benefit from acceleration data being filtered with a low-pass filter where high-frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the acceleration. It is simpler to interpret these functions dependent on dynamic acceleration data when the static component has been removed. The Transient Detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 are the dedicated Transient Detection configuration registers. The source register contains directional data to determine the direction of the acceleration, either positive or negative. For details on the benefits of the embedded Transient Detection function along with specific application examples and recommended configuration settings, please refer to Freescale application note, AN4071.

5.7 Pulse Detection

The MMA8452Q has embedded single/double and directional pulse detection. This function has various customizing timers for setting the pulse time width and the latency time between pulses. There are programmable thresholds for all three axes. The pulse detection can be configured to run through the high-pass filter and also through a low-pass filter, which provides more customizing and tunable pulse-detection schemes. The status register provides updates on the axes where the event was detected and the direction of the tap. For more information on how to configure the device for pulse detection, please refer to Freescale application note AN4072.

5.8 Orientation Detection

The MMA8452Q has an orientation detection algorithm with the ability to detect all 6 orientations. The transition from portrait to landscape is fixed with a 45° threshold angle and a ±14° hysteresis angle. This allows the for a smooth transition from portrait to landscape at approximately 30° and then from landscape to portrait at approximately 60°. The angle at which the device no longer detects the orientation change is referred to as the “Z-Lockout angle”. The device operates down to 29° from the flat position. All angles are accurate to ±2°. For further information on the orientation detection function refer to Freescale application note, AN4068. Figure 8 shows the definitions of the trip angles going from Landscape to Portrait (A) and then also from Portrait to Landscape (B).

5.9 Interrupt Register Configurations

Figure 10. System Interrupt Generation Block Diagram

5.10 Serial I 2C Interface

Freefall, Transient, Orientation, and Pulse. communications between other I2C devices and the MMA8452Q does not affect the I2C bus. and Normal mode (100 kHz) I2C standards (Table 5). Table 9. Serial Interface Pin Description

16 Freescale Semiconductor, Inc.

5.10.1 I 2C Operation

The transaction on the bus is started through a start condition (ST ART) signal. ST ART condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After ST ART has been transmitted by the Master, the bus is considered busy . The next byte of data transmitted after ST ART contains the slave address in the first 7 bits, and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The 9th clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock period. A LOW to HIGH transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer is always terminated by a STOP. A Master may also issue a repeated ST ART during a data transfer. The MMA8452Q expects repeated ST ART s to be used to randomly read from specific registers. The MMA8452Q's standard slave address is a choice between the two sequential addresses 001 1 100 and 001 1 101. The selection is made by the high- and low-logic level of the SA0 (pin 7) input respectively . The slave addresses are factory programmed and alternate addresses are available at customer request. The format is shown in Table 10. Single Byte Read The MMA8452Q has an internal ADC that can sample, convert and return sensor data on request. The transmission of an 8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send the command, note that the data returned is sent with the MSB first once the data is received. Figure 11 shows the timing diagram for the accelerometer 8-bit I read operation. The Master (or MCU) transmits a start condition (ST) to the MMA8452Q, slave address ($1D), with the R/W bit set to “0” for a write, and the MMA8452Q sends an acknowledgement. Then the Master (or MCU) transmits the address of the register to read and the MMA8452Q sends an acknowledgement. The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8452Q ($1D) with the R/W bit set to “1” for a read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NAK) the transmitted data, but transmits a stop condition to end the data transfer. Multiple Byte Read When performing a multi-byte read or “burst read”, the MMA8452Q automatically increments the received register address commands after a read command is received. Therefore, after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA8452Q acknowledgment (AK) is received until a no acknowledge (NAK) occurs from the Master followed by a stop condition (SP) signaling an end of transmission. Single Byte Write T o start a write command, the Master transmits a start condition (ST) to the MMA8452Q, slave address ($1D) with the R/W bit set to “0” for a write, the MMA8452Q sends an acknowledgement. Then the Master (MCU) transmits the address of the register to write to, and the MMA8452Q sends an acknowledgement. Then the Master (or MCU) transmits the 8-bit data to write to the designated register and the MMA8452Q sends an acknowledgement that it has received the data. Since this transmission is complete, the Master transmits a stop condition (SP) to the data transfer. The data sent to the MMA8452Q is now stored in the appropriate register.

The MMA8452Q automatically increments the received register address commands after a write command is received. MMA8452Q acknowledgment (ACK) is received. Figure 11. I2C Timing Diagram Table 10. I2C Device Address Sequence

18 Freescale Semiconductor, Inc.

6 Register Descriptions

Table 11. Register Address Map OUT_X_MSB(1)(2) R 0x01 0x02 0x03 Output — [7:0] are 8 MSBs of 12-bit sample. OUT_X_LSB(1)(2) R 0x02 0x03 0x00 Output — [7:4] are 4 LSBs of 12-bit sample. OUT_Y_MSB(1)(2) R 0x03 0x04 0x05 Output — [7:0] are 8 MSBs of 12-bit sample. OUT_Y_LSB(1)(2) R 0x04 0x05 0x00 Output — [7:4] are 4 LSBs of 12-bit sample. OUT_Z_MSB(1)(2) R 0x05 0x06 0x00 Output — [7:0] are 8 MSBs of 12-bit sample. OUT_Z_LSB(1)(2) R 0x06 0x00 Output — [7:4] are 4 LSBs of 12-bit sample. Reserved R 0x07 — — — Reserved. Read return 0x00. Reserved R 0x08 — — — Reserved. Read return 0x00. PL_CFG(3)(4) R/W 0x11 0x12 10000000 0x80 Landscape/Portrait configuration. 0x1C — — — Reserved. Read return 0x00.

6.1 Data Registers

to application note, AN4076. Reserved (do not modify) 0x40 – 7F — — — Reserved. Read return 0x00.

1. Register contents are reset when transition from STANDBY to ACTIVE mode occurs.
2. This register data is only valid in ACTIVE mode.
3. Register contents are preserved when transition from ACTIVE to STANDBY mode occurs.
4. Modification of this register’s contents can only occur when device is STANDBY mode except CTRL_REG1 ACTIVE bit and CTRL_REG2

Table 12. STATUS Description

20 Freescale Semiconductor, Inc. ZYXOW is set whenever a new acceleration data is produced before completing the retrieval of the previous set. This event occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been overwritten. ZYXOW is cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the active channels are read. ZOW is set whenever a new acceleration sample related to the Z-axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. ZOW is cleared anytime OUT_Z_MSB register is read. YOW is set whenever a new acceleration sample related to the Y -axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. YOW is cleared anytime OUT_Y_MSB register is read. XOW is set whenever a new acceleration sample related to the X-axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. XOW is cleared anytime OUT_X_MSB register is read. ZYXDR signals that a new sample for any of the enabled channels is available. ZYXDR is cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the enabled channels are read. ZDR is set whenever a new acceleration sample related to the Z-axis is generated. ZDR is cleared anytime OUT_Z_MSB register is read. YDR is set whenever a new acceleration sample related to the Y-axis is generated. YDR is cleared anytime OUT_Y_MSB register is read. XDR is set whenever a new acceleration sample related to the X-axis is generated. XDR is cleared anytime OUT_X_MSB register is read. Data Registers: 0x01: OUT_X_MSB, 0x02: OUT_X_LSB, 0x03: OUT_Y_MSB, 0x04: OUT_Y_LSB, 0x05: OUT_Z_MSB, 0x06: OUT_Z_LSB These registers contain the X-axis, Y-axis, and Z-axis 12-bit output sample data expressed as 2's complement numbers. The sample data output registers store the current sample data. OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the auto- incrementing address range of 0x01 to 0x06 to reduce reading the status followed by 12-bit axis data to 7 bytes. If the F_READ bit is set (0x2A bit 1), auto-increment will skip over LSB registers. This will shorten the data acquisition from 7 bytes to 4 bytes. The LSB registers can only be read immediately following the read access of the corresponding MSB register. A random read access to the LSB registers is not possible. Reading the MSB register and then the LSB register in sequence ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the MSB and the LSB byte. 0x0B: SYSMOD System Mode Register The system mode register indicates the current device operating mode. Applications using the Auto-SLEEP/WAKE mechanism should use this register to synchronize the application with the device operating mode transitions. 0x01: OUT_X_MSB: X_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 0x02: OUT_X_LSB: X_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XD3 X D2 X D1 X D0 0000 0x03: OUT_Y_MSB: Y_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 0x04: OUT_Y_LSB: Y_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 YD3 Y D2 X D1 X D0 0000 0x05: OUT_Z_MSB: Z_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4 0x06: OUT_Z_LSB: Z_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ZD3Z D2Z D1Z D0 0 0 0 0 0x0B: SYSMOD: System Mode Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 SYSMOD1 SYSMOD0

reading the Status Register (0x00). Table 13. SYSMOD Description System Mode. Default value: 00. Table 14. INT_SOURCE Description Auto-SLEEP/WAKE interrupt status bit. Default value: 0. Logic ‘0’ indicates that no WAKE to SLEEP or SLEEP to WAKE system mode transition interrupt event has occurred. (ASLP_COUNT). This causes the system to transition to a user specified low ODR setting. system to transition to a user specified high ODR setting. Reading the SYSMOD register clears the SRC_ASLP bit. Transient interrupt status bit. Default value: 0. indicates that no transient event has occurred. cleared by reading the TRANS_SRC register. Landscape/Portrait Orientation interrupt status bit. Default value: 0. that no change in orientation status was detected. This bit is cleared by reading the PL_STATUS register. Pulse interrupt status bit. Default value: 0. This bit is asserted whenever “EA” bit in the PULSE_SRC is asserted and the interrupt has been enabled. This bit is cleared by reading the PULSE_SRC register. Freefall/Motion interrupt status bit. Default value: 0. This bit is cleared by reading the FF_MT_SRC register. Data Ready Interrupt bit status. Default value: 0. Logic ‘1’ indicates that the X, Y, Z data ready interrupt is active indicating the presence of new data and/or data overrun. Otherwise if it is a logic ‘0’ the X, Y, Z interrupt is not active. This bit is asserted when the ZYXOW and/or ZYXDR is set and the interrupt has been enabled. This bit is cleared by reading the X, Y, and Z data.

22 Freescale Semiconductor, Inc. factory for custom alternate values. bit is set. The data registers 0x01 - 0x06 will contain high-pass filtered data when this bit is set. The default full scale value range is 2g and the high-pass filter is disabled. to Freescale application note AN4071.

000 H PF_OUT 0 0 F S1F S0

Table 15. XYZ Data Configuration Descriptions FS[1:0] Output buffer data format full scale. Default value: 00 (2g). Table 16. Full Scale Range

11 R eserved

7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Table 17. High-Pass Filter Cutoff Register Descriptions Bypass High-Pass Filter for Pulse Processing Function. Enable Low-Pass Filter for Pulse Processing Function. HPF Cutoff frequency selection. Default value: 00 (see Table 18).

6.2 Portrait/ Landscape Embedded Function Registers

Right, Back and Front orientations please refer to Figure 3. The interrupt is cleared when reading the PL_STATUS register. the absolute value of the acceleration experienced on any of the three axes is greater than 1.25g. Table 18. High-Pass Filter Cutoff Options Table 19. PL_STATUS Register Description NEWLP Landscape/Portrait status change flag. Default value: 0. Z-Tilt Angle Lockout. Default value: 0. 0: Lockout condition has not been detected. 1: Z-Tilt lockout trip angle has been exceeded. Lockout has been detected.

1. The default power up state is BAFRO = 0, LAPO = 0, and LO = 0.

11: Landscape Left: Equipment is in landscape mode to the left. 0: Front: Equipment is in the front facing orientation. 1: Back: Equipment is in the back facing orientation.

24 Freescale Semiconductor, Inc. This register enables the Portrait/Landscape function and sets the behavior of the debounce counter. The Z-Lock angle compensation is set to 29°. The Back to Front trip angle is set to ±75°. Note: All angles are accurate to ±2°. Table 20. PL_CFG Description 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid. 0: Portrait/Landscape Detection is Disabled. 1: Portrait/Landscape Detection is Enabled. Table 21. PL_COUNT Description DBCNE[7:0] Debounce Count value. Default value: 0000_0000. Table 22. PL_COUNT Relationship with the ODR Table 23. PL_BF_ZCOMP Description BKFR[1:0] Back Front Trip Angle Fixed Threshold = 01 which is ≥ ±75°. ZLOCK[2:0] Z-Lock Angle Fixed Threshold = 100 which is 29°.

This register represents the Portrait to Landscape trip threshold.

6.3 Motion and Freefall Embedded Function Registers

bit 6). The freefall/motion detection block can be disabled by setting all three bits ZEFE, YEFE, and XEFE to zero. that the corresponding bits ZEFE, YEFE, and/or XEFE are set. after the FF_MT_SRC register has been read. FF_MT_SRC does not clear any flags, nor is the debounce counter reset. their current value until the FF_MT_SRC register is read. Table 24. P_L_THS_REG Description P_L_THS[7:3] Portrait/Landscape Fixed Threshold angle = 1_0000 (45°). Portrait. This angle is fixed at ±14°, which is 100. Table 25. Trip Angles with Hysteresis for 45° Angle

26 Freescale Semiconductor, Inc. This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. OAE bit allows the selection between Motion (logical OR combination) and Freefall (logical AND combination) detection. EA bit gets set, and are cleared by reading the FF_MT_SRC source register. are blocked from updating the FF_MT_SRC register. X or Y or Z acceleration value is higher than the threshold value. Figure 12. FF_MT_CFG High- and Low-g Level Table 26. FF_MT_CFG Description flag EA and all FF_MT_SRC bits. Default value: 0. ZEFE Event flag enable on Z Default value: 0. YEFE Event flag enable on Y event. Default value: 0. XEFE Event flag enable on X event. Default value: 0.

INT_CFG_FF_MT register bits to generate the freefall/motion interrupts. defined in the FF_MT_THS register. to the preset threshold value defined in the FF_MT_THS register. 0x2A then the maximum threshold will be limited to 4g regardless of the full scale range. impede the detection of inertial events. Table 27. Freefall/Motion Source Description Event Active Flag. Default value: 0. 0: No event flag has been asserted; 1: one or more event flag has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. Z Motion Flag. Default value: 0. Z Motion Polarity Flag. Default value: 0. Y Motion Flag. Default value: 0. Table 28. FF_MT_THS Description DBCNTM Debounce counter mode selection. Default value: 0. 0: increments or decrements debounce, 1: increments or clears counter. THS[6:0] Freefall /Motion Threshold: Default value: 000_0000.

28 Freescale Semiconductor, Inc. This register sets the number of debounce sample counts for the event trigger. selected for the freefall, motion event. ODR chosen and the Oversampling mode as shown in Table 30. Table 29. FF_MT_COUNT Description Table 30. FF_MT_COUNT Relationship with the ODR

Figure 13. DBCNTM Bit Function

30 Freescale Semiconductor, Inc.

6.4 Transient (HPF) Acceleration Detection

filter is bypassed, the function behaves similar to the motion detection. TRANSIENT_SRC register is read. register, all bits get cleared. Table 31. TRANSIENT_CFG Description ZTEFE Event flag enable on Z transient acceleration greater than transient threshold event. Default value: 0. 0: Event detection disabled; 1: Raise event flag on measured acceleration delta value greater than transient threshold. YTEFE Event flag enable on Y transient acceleration greater than transient threshold event. Default value: 0. 0: Event detection disabled; 1: Raise event flag on measured acceleration delta value greater than transient threshold. XTEFE Event flag enable on X transient acceleration greater than transient threshold event. Default value: 0. 0: Event detection disabled; 1: Raise event flag on measured acceleration delta value greater than transient threshold. Bypass High-Pass filter Default value: 0.

0 EA ZTRANSE Z_Trans_Pol YTRANSE Y _Trans_Pol XTRANSE X_Trans_Pol

Table 32. TRANSIENT_SRC Description EA Event Active Flag. Default value: 0. 0: no event flag has been asserted; 1: one or more event flag has been asserted. ZTRANSE Z transient event. Default value: 0. Z_Trans_Pol Polarity of Z Transient Event that triggered interrupt. Default value: 0. YTRANSE Y transient event. Default value: 0. Y_Trans_Pol Polarity of Y Transient Event that triggered interrupt. Default value: 0. XTRANSE X transient event. Default value: 0. X_Trans_Pol Polarity of X Transient Event that triggered interrupt. Default value: 0.

Pass Filtered acceleration value exceeds the threshold limit an event flag is raised and the interrupt is generated if enabled. Freescale application note, AN4071. unsigned value of high-pass filtered data is greater than the user specified value of TRANSIENT_THS. The time step for the transient detection debounce counter is set by the value of the system ODR and the Oversampling mode. Table 33. TRANSIENT_THS Description DBCNTM Debounce counter mode selection. Default value: 0. 0: increments or decrements debounce; 1: increments or clears counter. THS[6:0] Transient Threshold: Default value: 000_0000. Table 34. TRANSIENT_COUNT Description D[7:0] Count value. Default value: 0000_0000. Table 35. TRANSIENT_COUNT Relationship with the ODR

32 Freescale Semiconductor, Inc.

6.5 Single, Double and Directional Pulse-Detection Registers

For more details of how to configure the pulse detection and sample code please refer to Freescale application note, AN4072. The pulse-detection registers are referred to as “Pulse”. must be enabled in Register 0x21 for the event to be seen in the source register. PULSE_SRC register clears all bits. Reading the source register will clear the interrupt. Table 36. PULSE_CFG Description Double Pulse Abort. Default value: 0. 0: Double Pulse detection is not aborted if the start of a pulse is detected during the time period specified by the PULSE_LTCY register. specified by the PULSE_LTCY register and the pulse ends before the end of the time period specified by the PULSE_LTCY register. Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag. ZDPEFE Event flag enable on double pulse event on Z-axis. Default value: 0. ZSPEFE Event flag enable on single pulse event on Z-axis. Default value: 0. YDPEFE Event flag enable on double pulse event on Y-axis. Default value: 0. YSPEFE Event flag enable on single pulse event on Y-axis. Default value: 0. XDPEFE Event flag enable on double pulse event on X-axis. Default value: 0. XSPEFE Event flag enable on single pulse event on X-axis. Default value: 0. Table 37. PULSE_SRC Description EA Event Active Flag. Default value: 0. AxZ Z-axis event. Default value: 0. AxY Y-axis event. Default value: 0. AxX X-axis event. Default value: 0. DPE Double pulse on first event. Default value: 0. PolZ Pulse polarity of Z-axis Event. Default value: 0. PolY Pulse polarity of Y-axis Event. Default value: 0. PolX Pulse polarity of X-axis Event. Default value: 0.

registers define the threshold which is used by the system to start the pulse detection procedure. detection procedure. The threshold value is expressed over 7-bits as an unsigned number. specified threshold to be considered a valid pulse. and whether the Pulse Low-Pass Filter option is enabled or not. The Pulse Low-Pass Filter is set in Register 0x0F.

0 THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0

Table 38. PULSE_THSX Description THSX[6:0] Pulse Threshold on X-axis. Default value: 000_0000.

0 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0

Table 39. PULSE_THSY Description THSY[6:0] Pulse Threshold on Y-axis. Default value: 000_0000.

0 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0

Table 40. PULSE_THSZ Description THSZ[6:0] Pulse Threshold on Z-axis. Default value: 000_0000. Table 41. PULSE_TMLT Description TMLT[7:0] Pulse Time Limit. Default value: 0000_0000. Table 42. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 1

34 Freescale Semiconductor, Inc. pulses are ignored. Note: This timer must be set for single pulse and for double pulse. and Oversampling mode multiplied by 255. The timing also changes when the Pulse LPF is enabled or disabled. Table 43. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0 Table 44. PULSE_LTCY Description Table 45. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 46. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0

of the double pulse need not finish within the time specified by the PULSE_WIND register. Oversampling mode and LPF Filter Option multiplied by 255. Table 47. PULSE_WIND Description WIND[7:0] Second Pulse Time Window. Default value: 0000_0000. Table 48. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 49. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0

36 Freescale Semiconductor, Inc.

6.6 Auto-WAKE/SLEEP Detection

register. See Table 52 for functional blocks that may be monitored for inactivity in order to trigger the “return to SLEEP” event. value depend on the ODR chosen as shown in Table 51. selected for WAKE from SLEEP will WAKE the device. does the data ready interrupt. See Register 0x2C for the WAKE from SLEEP bits. interrupt is enabled, transitioning from ACTIVE mode to Auto-SLEEP mode and vice versa generates an interrupt. Table 50. ASLP_COUNT Description D[7:0] Duration value. Default value: 0000_0000. Table 51. ASLP_COUNT Relationship with ODR

200 Hz 0 to 81s 5 ms 320 ms

100 Hz 0 to 81s 10 ms 320 ms

50 Hz 0 to 81s 20 ms 320 ms

12.5 Hz 0 to 81s 80 ms 320 ms

6.25 Hz 0 to 81s 160 ms 320 ms

1.56 Hz 0 to 162s 640 ms 640 ms

Table 52. SLEEP/WAKE Mode Gates and Triggers

6.7 Control Registers

functional blocks are overridden by the data rate set by the ASLP_RATE field. DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples. The default value is 000 for a data rate of 800 Hz. ACTIVE bit selects between STANDBY mode and ACTIVE mode. The default value is 0 for STANDBY mode. maximum signal that can be measured is ±4g. Note: Any thresholds set above 4g will not be reached. Table 53. CTRL_REG1 Description ASLP_RATE[1:0] Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode. Default value: 00. See Table 54 for more information. DR[2:0] Data rate selection. Default value: 000. See Table 55 for more information. LNOISE Reduced noise reduced Maximum range mode. Default value: 0. F_READ Fast Read mode: Data format limited to single Byte Default value: 0. ACTIVE Full Scale selection. Default value: 00. Table 54. SLEEP Mode Rate Description Table 55. System Output Data Rate Selection Table 56. Full Scale Selection

38 Freescale Semiconductor, Inc. ST bit activates the self-test function. When ST is set, X, Y, and Z outputs will shift. RST bit is used to activate the software reset. The reset mechanism can be enabled in STANDBY and ACTIVE mode. resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode. The I2C communication system is reset to avoid accidental corrupted data access. At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero. available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0]. Table 57. CTRL_REG2 Description ST Self-Test Enable. Default value: 0. RST Software Reset. Default value: 0. 0: Device reset disabled; 1: Device reset enabled. SMODS[1:0] SLEEP mode power scheme selection. Default value: 00. Auto-SLEEP enable. Default value: 0. MODS[1:0] ACTIVE mode power scheme selection. Default value: 00. Table 58. MODS Oversampling Modes

00 N ormal

Table 59. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR

1.56 Hz 24 128 8 32 165 1024 6 16

6.25 Hz 24 32 8 8 165 256 6 4

12.5 Hz 24 16 8 4 165 128 6 2

50 Hz 24 4 24 4 165 32 14 2

100 Hz 44 4 44 4 165 16 24 2

200 Hz 85 4 85 4 165 8 44 2

400 Hz 165 4 165 4 165 4 85 2

800 Hz 165 2 165 2 165 2 165 2

Pull mode. The Open Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line. system’s interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin.

0 WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT 0 IPOL PP_OD

Table 60. CTRL_REG3 Description WAKE_TRANS 0: Transient function is bypassed in SLEEP mode. Default value: 0. WAKE_LNDPRT 0: Orientation function is bypassed in SLEEP mode. Default value: 0. WAKE_PULSE 0: Pulse function is bypassed in SLEEP mode. Default value: 0. WAKE_FF_MT 0: Freefall/Motion function is bypassed in SLEEP mode. Default value: 0. IPOL Interrupt polarity ACTIVE high, or ACTIVE low. Default value: 0. PP_OD Push-Pull/Open Drain selection on interrupt pad. Default value: 0. Table 61. Interrupt Enable Register Description INT_EN_ASLP Interrupt Enable. Default value: 0. 0: Auto-SLEEP/WAKE interrupt disabled; 1: Auto-SLEEP/WAKE interrupt enabled. INT_EN_TRANS Interrupt Enable. Default value: 0. 0: Transient interrupt disabled; 1: Transient interrupt enabled. Interrupt Enable. Default value: 0. 0: Orientation (Landscape/Portrait) interrupt disabled. 1: Orientation (Landscape/Portrait) interrupt enabled. INT_EN_PULSE Interrupt Enable. Default value: 0. INT_EN_FF_MT Interrupt Enable. Default value: 0. INT_EN_DRDY Interrupt Enable. Default value: 0.

40 Freescale Semiconductor, Inc.

6.8 User Offset Correction Registers

Table 62. Interrupt Configuration Register Description INT_CFG_ASLP INT1/INT2 Configuration. Default value: 0. INT_CFG_TRANS INT1/INT2 Configuration. Default value: 0. INT_CFG_LNDPRT INT1/INT2 Configuration. Default value: 0. INT_CFG_PULSE INT1/INT2 Configuration. Default value: 0. INT_CFG_FF_MT INT1/INT2 Configuration. Default value: 0. INT_CFG_DRDY INT1/INT2 Configuration. Default value: 0. Table 63. OFF_X Description D[7:0] X-axis offset value. Default value: 0000_0000. Table 64. OFF_Y Description D[7:0] Y-axis offset value. Default value: 0000_0000. Table 65. OFF_Z Description D[7:0] Z-axis offset value. Default value: 0000_0000.

Table 66. MMA8452Q Register Map

00 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR

01 OUT_X_MSB 12-bit X Data R XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2

02 OUT_X_LSB 12-bit X Data R XD1 XD0 0 0 0 0 0 0

03 OUT_Y_MSB 12-bit Y Data R YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2

04 OUT_Y_LSB 12-bit Y Data R YD1 YD0 0 0 0 0 0 0

05 OUT_Z_MSB 12-bit Z Data R ZD9 ZD8 ZD7 ZD6 ZD5 ZD4 ZD3 ZD2

06 OUT_Z_LSB 12-bit Z Data R ZD1 ZD0 0 0 0 0 0 0

10 PL_STATUS PL Status R NEWLP LO 0 0 0 LAPO[1] LAPO[0] BAFRO

11 PL_CFG PL Configuration R/W DBCNTM PL_EN 0 0 0 0 0 0

12 PL_COUNT PL DEBOUNCE R/W DBNCE[7] DBNCE[6] DBNCE[5] DBNCE[4] DBNCE[3] DBNCE[2] DBNCE[1] DBNCE[0]

13 PL_BF_ZCOMP PL Back/Front Z Comp

15 FF_MT_CFG Freefall/Motion Config

16 FF_MT_SRC Freefall/Motion Source

17 FF_MT_THS

18 FF_MT_COUNT

20 TRANSIENT_COUNT Transient Debounce

21 PULSE_CFG Pulse Config R/W DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE

22 PULSE_SRC Pulse Source R EA AxZ AxY AxX DPE Pol_Z Pol_Y Pol_X

23 PULSE_THSX Pulse X Threshold R/W 0 THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0

24 PULSE_THSY Pulse Y Threshold R/W 0 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0

25 PULSE_THSZ Pulse Z Threshold R/W 0 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0

26 PULSE_TMLT Pulse First Timer R/W TMLT7 TMLT6 TMLT5 TMLT4 TMLT3 TMLT2 TMLT1 TMLT0

27 PULSE_LTCY Pulse Latency R/W LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0

28 PULSE_WIND Pulse 2nd Window

29 ASLP_COUNT Auto-SLEEP Counter

42 Freescale Semiconductor, Inc.

30 OFF_Y Y 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0

31 OFF_Z Z 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0

Table 67. Accelerometer Output Data

Freescale Semiconductor, Inc. 43 PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN

44 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN

Freescale Semiconductor, Inc. 45 PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN

46 Freescale Semiconductor, Inc. Table 1. Revision History

• Table 2. Updated Typ values for Sensitivity Accuracy from 2.5% to 2.68%; Zero-g Level Offset Accuracy from ±20 mg to ±17 mg and Zero-g Level Offset Accuracy Post Board Mount from ±30 mg to ±20 mg.
• Updated section 2.3 I2C Interface Characteristics
• Added Table 8. Features of the MMA845xQ devices.
• Removed FIFO paragraph at the end of Section 6.1.
• Updated Case outline.

Document Number: MMA8452Q Rev. 5 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/Policy.asSelectorpx?Selector=RT&s=STR0326182960&pc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.