MMA8451Q FREESCALE | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 2 Freescale Semiconductor
- 1 Block Diagram and Pin Description
- 1.1 Block Diagram
- 1.2 Pin Description
- 1.3 Soldering Information
- 2 Mechanical and Electrical Specifications
- 2.1 Mechanical Characteristics
- 2.2 Electrical Characteristics
- 2.3 I 2C Interface Characteristic
- 2.4 Absolute Maximum Ratings
- 3 Terminology
- 3.1 Sensitivity
- 3.2 Zero-g Offset
- 3.3 Self-Test
- 4 Modes of Operation
- 5 Functionality
- 5.1 Device Calibration
- 5.3 Internal FIFO Data Buffer
- 5.5 Auto-WAKE/SLEEP Mode
- 5.6 Freefall and Motion Detection
- 5.6.1 Freefall Detection
- 5.6.2 Motion Detection
- 5.7 Transient Detection
- 5.8 Tap Detection
- 5.9 Orientation Detection
- 5.10 Interrupt Register Configuratio ns
- 5.11 Serial I 2C Interface
- 5.11.1 I 2C Operation
Features
- 1.95 V to 3.6 V supply voltage
- 1.6 V to 3.6 V interface voltage
- ±2g/±4g/±8g dynamically selectable full-scale
- Output Data Rates (ODR) from 1.56 Hz to 800 Hz
- 9 9 μg/√Hz noise
- 14-bit and 8-bit digital output 2C digital output interface (operates to 2.25 MHz with 4.7 kΩ pull-up)
- 2 programmable interrupt pins for 7 interrupt sources
- 3 embedded channels of motion detection – Freefall or Motion Detection: 1 channel – Pulse Detection: 1 channel – Jolt Detection: 1 channel
- Orientation (Portrait/Landscape) detection with programmable hysteresis
- Automatic ODR change for Auto-WAKE and return to SLEEP
- 32 sample FIFO
- High Pass Filter Data available per sample and through the FIFO
- S e l f - T e s t
- RoHS compliant
- Current Consumption: 6 μA – 165 μA Typical Applications
- E-Compass applications
- Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/ Front position identification)
- Notebook, E-Reader and Laptop Tumble and Freefall Detection
- Real-time orientation detection (virt ual reality and gaming 3D user position feedback)
- Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)
- Motion detection for portable product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)
- Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)
- User interface (menu scrolling by orientation change, tap detection for button replacement)
ORDERING INFORMATION
Part Number Temperature Range Package Description Shipping MMA8451QT -40°C to +85°C QFN-16 Tray MMA8451QR1 -40°C to +85°C QFN-16 Tape and Reel GND VDDIO SCL NC INT2 INT1 GND GND SDA SA0 VDDNC NC NC BYP NC MMA8451Q 1415 6 7 8
16 PIN QFN
MMA8451Q: 3-AXIS DIGITAL ACCELEROMETER ±2g/±4g/±8g Top and Bottom View Top View Pin Connections
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- AN4068, Embedded Orientation Detection Using the MMA8451, 2, 3Q
- AN4069, Offset Calibration of the MMA8451, 2, 3Q
- AN4070, Motion and Freefall Detection Using the MMA8451, 2, 3Q
- AN4071, High Pass Data and Functions Using the MMA8451, 2,3Q
- AN4072, MMA8451, 2, 3Q Single/Double and Directional Tap Detection
- AN4073, Using the 32 Sample First In First Out (FIFO) in the MMA8451Q
- AN4074, Auto-Wake/Sleep Using the MMA8451, 2, 3Q
- AN4075, How Many Bits are Enough? The Trade-off Between High Resolution and Low Power Using Oversampling Modes
- AN4076, Data Manipulation and Basic Settings of the MMA8451, 2, 3Q
- AN4077, MMA8451, 2, 3Q Design Checklist and Board Mounting Guidelines
1 Block Diagram and Pin Description
1.1 Block Diagram
Figure 1. Block Diagram
1.2 Pin Description
Figure 2. Direction of the Detectable Accelerations
32 Data Point
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single 4.7 µF ceramic) should be placed as near as possible to the pins 1 and 14 of the device. signals SCL, SDA, and SA0 will clamp any logic signals with their internal ESD protection diodes.
1.3 Soldering Information
The QFN package is compliant with the RoHS standard. Please refer to AN4077. Table 1. Pin Description
5 GND Connect to Ground Input
7 SA0 I2C Least Significant Bit of the Device I2C Address Input
8 NC Internally not connected (can be GND or VDD) Input
9 INT2 Inertial Interrupt 2 Output
10 GND Connect to Ground Input
11 INT1 Inertial Interrupt 1 Output
12 GND Connect to Ground Input
13 NC Internally not connected (can be GND or VDD) Input
15 NC Internally not connected (can be GND or VDD) Input
16 NC Internally not connected (can be GND or VDD) Input
2 Mechanical and Elect rical Specifications
2.1 Mechanical Characteristics
Table 2. Mechanical Characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted.
- Dynamic Range is limited to 4g when the Low Noise bit in Register 0x2A, bit 2 is set.
- Sensitivity remains in spec as stated, but changing Oversampling mode to Low Power causes 3% sensitivity shift. This behavior is also seen
when changing from 800 Hz to any other data rate in the Normal, Low Noise + Low Power or High Resolution mode.
- Post Board Mount Offset Specifications are based on an 8 Layer PCB, relative to 25°C.
- Self-Test is one direction only.
2 MHz Clock ±2 %
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2.2 Electrical Characteristics
Table 3. Electrical Characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted.
- There is no requirement for power supply sequencing. The VDDIO input voltage can be higher than the VDD input voltage.
2.3 I 2C Interface Characteristic
Table 4. I2C Slave Timing Values(1)
- All values referred to VIH (min) and VIL (max) levels.
- tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
- The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard mode and Fast mode, but must be less than the maximum of tVD;DAT or tVD;ACK
- tVD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
- tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
- A Fast mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will
- Cb = total capacitance of one bus line in pF.
- The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.
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Figure 5. I2C Slave Timing Diagram
2.4 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. Table 5. Maximum Ratings Table 6. ESD and Latch-Up Protection Characteristics cause the part to otherwise fail. This is an ESD sensitive, improper handling can cause permanent damage to the part.
3 Terminology
3.1 Sensitivity
g and in 8g mode the sensitivity is 1024 counts/g.
3.2 Zero-g Offset
extensive mechanical stress.
3.3 Self-Test
4 Modes of Operation
Figure 6. MMA8451Q Mode Transition Diagram these modes please refer to the functionality section of this document. Table 7. Mode of Operation Description are shutdown. I2C bus inhibited. Only digital blocks are enabled. Analog subsystem is disabled. Internal clocks disabled. All blocks are enabled (digital, analog).
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5F u n c t i o n a l i t y The MMA8451Q is a low-power, digital output 3-axis linear accelerometer with a I2C interface and embedded logic used to detect events and notify an external microprocessor over interrupt lines. The functionality includes the following:
- 8-bit or 14-bit data, High Pass Filtered data, 8-bit or 14-bit configurable 32 sample FIFO
- 4 different oversampling options for compromising betw een resolution and current cons umption based on application requirements
- Additional Low Noise mode that functions independently of the Oversampling modes for higher resolution
- Low Power and Auto-WAKE/SL EEP for conservation of current consumption
- Single/Double tap with directional information 1 channel
- Motion detection with directional in formation or Freefall 1 channel
- Transient/Jolt detection based on a high pass filter and settable threshold for detecting the change in acceleration above a threshold with directional information 1 channel
- Flexible user configurable portrait landscape detection algorithm addressing many use cases for screen orientation All functionality is available in 2g, 4g or 8g dynamic ranges. There are many configuration settings for enabling all the different functions. Separate application notes have been provided to help configure the device for each embedded functionality .
5.1 Device Calibration
The device interface is factory calibrated for sensitivity and Zero-g offset for each axis. The trim values are stored in Non Volatile Memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry . In normal use, further calibration in the end application is not necessary . However, the MMA8451Q allows the user to adjust the Zero-g offset for each axis after power-up, changing the default offset values. The user offset adjustments are stored in 6 volatile registers. For more information on device calibration, refer to Freescale application note, AN4069. 5.2 8-bit or 14-bit Data The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 14-bit numbers. The most significant 8-bits of each axis are stored in OUT_X (Y, Z)_MSB, so applications needing only 8-bit results can use these 3 registers and ignore OUT_X,Y, Z_LSB. To do this, the F_READ bit in CTRL_REG1 must be set. When the F_READ bit is cleared, the fast read mode is disabled. When the full-scale is set to 2g, the measurement range is -2g to +1.99975g, and each count corresponds to 1g/4096 (0.25 mg) at 14-bits resolution. When the full-scale is set to 8g, the measurement range is -8g to +7.999g, and each count corresponds to 1g/1024 (0.98 mg) at 14-bits resolution. The resolution is reduced by a factor of 64 if only the 8-bit results are used. For more information on the data manipulation between data formats and modes, refer to Freescale application note, AN4076. There is a device driver available that can be used with the Sensor T oolbox demo board (LFSTBEB8451, 2, 3Q) with this application note.
5.3 Internal FIFO Data Buffer
MMA8451Q contains a 32 sample internal FIFO data buffer minimizing traffic across the I2C bus. The FIFO can also provide power savings of the system by allowing the host processor/MCU to go into a SLEEP mode while the accelerometer independently stores the data, up to 32 samples per axis. The FIFO can run at all output data rates. There is the option of accessing the full 14-bit data or for accessing only the 8-bit data. When access speed is more important than high resolution the 8-bit data read is a better option. The FIFO contains four modes (Fill Buffer Mode, Circular Buffer Mode, Trigger Mode, and Disabled Mode) described in the F_SETUP Register 0x09. Fill Buffer Mode collects the first 32 samples and asserts the overflow flag when the buffer is full and another sample arrives. It does not collect any more data until the buffer is read. This benefits data logging applications where all samples must be collected. The Circular Buffer Mode allows the buffer to be filled and then new data replaces the oldest sample in the buffer. The most recent 32 samples will be stored in the buffer. This benefits situations where the processor is waiting for an specific interrupt to signal that the data must be flushed to analyze the event. The trigger mode will hold the last data up to the point when the trigger occurs and can be set to keep a selectable number of samples after the event occurs. The MMA8451Q FIFO Buffer has a configurable watermark, allowing the processor to be triggered after a configurable number of samples has filled in the buffer (1 to 32). For details on the configurations for the FIFO buffer as well as more specific examples and application benefits, refer to Freescale application note, AN4073.
Freescale Semiconductor 15 MMA8451Q 5.4 Low Power Modes vs. High Resolution Modes The MMA8451Q can be optimized for lower power modes or for higher resolution of the output data. High resolution is achieved by setting the LNOISE bit in Register 0x2A. This improves the resolution but be aware that the dynamic range is limited to 4g when this bit is set. This will affect all internal functions and reduce noise. Another method for improving the resolution of the data is by oversampling. One of the oversampling schemes of the data can activated when MODS = 10 in Register 0x2B which will improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz. There is a trade-off between low power and high resolution. Low Power can be achieved when the oversampling rate is reduced. When MODS = 11 the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz. For more information on how to configure the MMA8451Q in Low Power mode or High Resolution mode and to realize the benefits, refer to Freescale application note, AN4075.
5.5 Auto-WAKE/SLEEP Mode
The MMA8451Q can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. The advantage of using the Auto-WAKE/SLEEP is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the SLEEP mode (lower current) when the device does not require higher sampling rates. Auto-WAKE refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This may also interrupt the processor to transition from a SLEEP mode to a higher power mode. SLEEP mode occurs after the accelerometer has not detected an interrupt for longer than the user definable time-out period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save on current during this period of inactivity . The Interrupts that can WAKE the device from SLEEP are the following: T ap Detection, Orientation Detection, Motion/Freefall, and Transient Detection. The FIFO can be configured to hold the data in the buffer until it is flushed if the FIFO Gate bit is set in Register 0x2C but the FIFO cannot WAKE the device from SLEEP. The interrupts that can keep the device from falling asleep are the same interrupts that can wake the device with the addition of the FIFO. If the FIFO interrupt is enabled and data is being accessed continually servicing the interrupt then the device will remain in the WAKE mode. Refer to AN4074, for more detailed information for configuring the Auto-WAKE/SLEEP.
5.6 Freefall and Motion Detection
MMA8451Q has flexible interrupt architecture for detecting either a Freefall or a Motion. Freefall can be enabled where the set threshold must be less than the configured threshold, or motion can be enabled where the set threshold must be greater than the threshold. The motion configuration has the option of enabling or disabling a high pass filter to eliminate tilt data (static offset). The freefall does not use the high pass filter. For details on the Freefall and Motion detection with specific application examples and recommended configuration settings, refer to Freescale application note AN4070.
5.6.1 Freefall Detection
The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user specified threshold for a user definable amount of time. Normally the usable threshold ranges are between ±100 mg and ±500 mg.
5.6.2 Motion Detection
Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2g. This condition would need to occur for a minimum of 100 ms to ensure that the event wasn't just noise. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for configurable set of time (i.e., 100 ms or longer). There is also directional data available in the source register to detect the direction of the motion. This is useful for applications such as directional shake or flick, which assists with the algorithm for various gesture detections.
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5.7 Transient Detection
flexibility to cover various customer use cases. specific application examples and recommended configuration settings, please refer to Freescale application note, AN4071.
5.8 Tap Detection
5.9 Orientation Detection
configurable trip points. The embedded algorithm allows the selection of the mid point with the desired hysteresis value. The MMA8451Q Orientation Detection algorithm confirms the reliability of the function with a configurable Z-lockout angle. “Z-Lockout angle”. The device operates down to 14° from the flat position. configuring the device to support various application use cases, refer to Freescale application note, AN4068. Figure 7. Landscape/Portrait Orientation
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5.10 Interrupt Register Configurations
pin, INT1 or INT2, will assert. Figure 11. System Interrupt Generation Block Diagram
5.11 Serial I 2C Interface
Freefall, Transient, Orientation, and T ap. communications between other I2C devices and the MMA8451Q does not affect the I2C bus. and Normal mode (100 kHz) I2C standards (Table 4). Table 8. Serial Interface Pin Description
5.11.1 I 2C Operation
stable low during the high period of the acknowledge clock period. repeated ST ART s to be used to randomly read from specific registers. programmed and alternate addresses are available at customer request. The format is shown in Table 9. data, but transmits a stop condition to end the data transfer. occurs from the Master followed by a stop condition (SP) signaling an end of transmission. Table 9. I2C Address Selection Table
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The MMA8451Q automatically increments the received register address commands after a write command is received. MMA8451Q acknowledgment (ACK) is received. Figure 12. I2C Timing Diagram Table 10. I2C Device Address Sequence
6 Register Descriptions
Table 11. Register Address Map PL_CFG(1)(4) R/W 0x11 0x12 10000000 0x80 Landscape/Portrait configuration.
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6.1 Data Registers
to application note, AN4076. bit is cleared the 14-bit data is read accessing all 6 bytes sequentially (X_MSB, X_LSB, Y_MSB, Y_LSB, Z_MSB, Z_LSB). Reserved (do not modify) 0x40 – 7F — — — Reserved. Read return 0x00.
- Register contents are preserved when transition from ACTIVE to STANDBY mode occurs.
- Register contents are reset when transition from STANDBY to ACTIVE mode occurs.
- Register contents can be modified anytime in STANDBY or ACTIVE mode. A write to this register will cause a reset of the corresponding
internal system debounce counter.
- Modification of this register’s contents can only occur when device is STANDBY mode except CTRL_REG1 ACTIVE bit and CTRL_REG2 RST
ZOW is set whenever a new acceleration sample related to the Z-axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. ZOW is cleared anytime OUT_Z_MSB register is read. YOW is set whenever a new acceleration sample related to the Y -axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. YOW is cleared anytime OUT_Y_MSB register is read. XOW is set whenever a new acceleration sample related to the X-axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. XOW is cleared anytime OUT_X_MSB register is read. acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the enabled channels are read. Table 12. STATUS Description
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Data Registers: 0x01 OUT_X_MSB, 0x02 OUT_X_LSB, 0x03 OUT_Y_MSB, 0x04 OUT_Y_LSB, 0x05 OUT_Z_MSB, 0x06 OUT_Z_LSB These registers contain the X-axis, Y-axis, and Z-axis14-bit output sample data expressed as 2's complement numbers. Note: The sample data output registers store the current sample data if the FIFO data output register driver is disabled, but if the FIFO data output register driver is enabled (F_MODE > 00) the sample data output registers point to the head of the FIFO buffer (Register 0x01 X_MSB) which contains the previous 32 X, Y, and Z data samples. Data Registers F_MODE = 00 OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the auto- incrementing address range of 0x01 to 0x06 to reduce reading the status followed by 14-bit axis data to 7 bytes. If the F_READ bit is set (0x2A bit 1), auto increment will skip over LSB registers. This will shorten the data acquisition from 7 bytes to 4 bytes. The LSB registers can only be read immediately following the read access of the corresponding MSB register. A random read access to the LSB registers is not possible. Reading the MSB register and then the LSB register in sequence ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the MSB and the LSB byte. If the FIFO is enabled (F_MODE > 00), Register 0x01 points to the FIFO read pointer, while registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read. If the F_READ bit is set (0x2A bit 1), auto increment will skip over LSB registers to access the MSB data only. 6.2 32 Sample FIFO The following registers are used to configure the FIFO. For more information on the FIFO please refer to AN4073. F_MODE > 0 0x00: F_STATUS FIFO Status Register When F_MODE > 0, Register 0x00 becomes the FIFO Status Register which is used to retrieve information about the FIFO. This register has a flag for the overflow and watermark. It also has a counter that can be read to obtain the number of samples stored in the buffer when the FIFO is enabled. 0x01 OUT_X_MSB: X_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XD13 XD12 XD11 XD10 XD9 XD8 XD7 XD6 0x02 OUT_X_LSB: X_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X D 5X D 4X D 3X D 2X D 1X D 0 0 0 0x03 OUT_Y_MSB: Y_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 YD13 YD12 YD11 YD10 YD9 YD8 YD7 YD6 0x04 OUT_Y_LSB: Y_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 YD5 YD4 YD3 YD2 YD1 YD0 0 0 0x05 OUT_Z_MSB: Z_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 0x06 OUT_Z_LSB: Z_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z D 5Z D 4Z D 3Z D 2Z D 1Z D 0 0 0 0x00 F_STATUS: FIFO STATUS Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F_OVF F_WMRK_FLAG F_CNT5 F_CNT4 F_CNT3 F_CNT2 F_CNT1 F_CNT0
is = 11, the FIFO has stopped accepting samples. be switched between Fill mode, Circular mode and Trigger mode. SLEEP is active the ODR is set by the ASLP_RA TE field in the CTRL_REG1 register. multi-byte read transaction to empty the FIFO. Table 13. FIFO Flag Event Description 0 — No FIFO overflow events detected. 1 — FIFO event detected; FIFO has overflowed. — 0 No FIFO watermark events detected. — 1 FIFO Watermark event detected. FIFO sample count is greater than watermark value. If F_MODE = 11, Trigger Event detected. Table 14. FIFO Sample Count Description F_CNT[5:0] FIFO sample counter. Default value: 00_0000. Table 15. F_SETUP Description
- Bit field can be written in ACTIVE mode.
- Bit field can be written in STANDBY mode.
FIFO buffer overflow mode. Default value: 0. 10: FIFO stops accepting new samples when overflowed. and after the trigger event and it is definable by the watermark setting. or transitioning from STANDBY mode to ACTIVE mode. Disabling the FIFO (F_MODE = 00) resets the F_OVF, F_WMRK_FLAG, F_CNT to zero. sample count watermark (i.e., F_WMRK) asserts the F_WMRK_FLAG event flag. FIFO Event Sample Count Watermark. Default value: 00_0000. flag is raised when FIFO sample count F_CNT[5:0] ≥ F_WMRK[5:0] watermark. Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation. Also used to set the number of pre-trigger samples in Trigger mode.
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and conversely bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt. register also indicates the status of the FIFO gate error and number of samples since the gate error occurred. Table 16. Trigger Configuration Description Table 17. SYSMOD Description FIFO Gate Error. Default value: 0. 0: No FIFO Gate Error detected. 1: FIFO Gate Error was detected. Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register. See section 0x2C: CTRL_REG3 Interrupt Control Register for more information on configuring the FIFO Gate function. System Mode. Default value: 00.
reading the Status Register (0x00). Table 18. INT_SOURCE Description Auto-SLEEP/WAKE interrupt status bit. Default value: 0. Logic ‘0’ indicates that no WAKE to SLEEP or SLEEP to WAKE system mode transition interrupt event has occurred. (ASLP_COUNT). This causes the system to transition to a user specified low ODR setting. system to transition to a user specified high ODR setting. Reading the SYSMOD register clears the SRC_ASLP bit. FIFO interrupt status bit. Default value: 0. that no FIFO interrupt event has occurred. This bit is cleared by reading the F_STATUS register. Transient interrupt status bit. Default value: 0. indicates that no transient event has occurred. cleared by reading the TRANS_SRC register. Landscape/Portrait Orientation interrupt status bit. Default value: 0. that no change in orientation status was detected. This bit is cleared by reading the PL_STATUS register. Pulse interrupt status bit. Default value: 0. This bit is asserted whenever “EA” bit in the PULSE_SRC is asserted and the interrupt has been enabled. This bit is cleared by reading the PULSE_SRC register. Freefall/Motion interrupt status bit. Default value: 0. This bit is cleared by reading the FF_MT_SRC register. Data Ready Interrupt bit status. Default value: 0. Logic ‘1’ indicates that the X, Y, Z data ready interrupt is active indicating the presence of new data and/or data overrun. Otherwise if it is a logic ‘0’ the X, Y, Z interrupt is not active. This bit is asserted when the ZYXOW and/or ZYXDR is set and the interrupt has been enabled. This bit is cleared by reading the X, Y, and Z data.
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factory for custom alternate values. bit is set, both the FIFO and DATA registers will contain high pass filtered data. The default full scale value range is 2g and the high pass filter is disabled. to Freescale application note AN4071. Table 19. XYZ Data Configuration Descriptions HPF_OUT Enable High pass output data 1 = output data High pass filtered. Default value: 0. FS[1:0] Output buffer data format full scale. Default value: 00 (2g). Table 20. Full Scale Range
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7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Table 21. High Pass Filter Cut-off Register Descriptions Bypass High Pass Filter (HPF) for Pulse Processing Function. Enable Low Pass Filter (LPF) for Pulse Processing Function. SEL[1:0] HPF Cut-off frequency selection. Default value: 00 (see Table 22).
6.3 Portrait/Landscape Embedded Function Registers
Right, Back and Front orientations please refer to Figure 3. The interrupt is cleared when reading the PL_STATUS register. the absolute value of the acceleration experienced on any of the three axes is greater than 1.25g. Table 22. High Pass Filter Cut-off Options Table 23. PL_STATUS Register Description NEWLP Landscape/Portrait status change flag. Default value: 0. Z-Tilt Angle Lockout. Default value: 0. 0: Lockout condition has not been detected. 1: Z-Tilt lockout trip angle has been exceeded. Lockout has been detected.
- The default power up state is BAFRO = 0, LAPO = 0, and LO = 0.
11: Landscape Left: Equipment is in landscape mode to the left. 0: Front: Equipment is in the front facing orientation. 1: Back: Equipment is in the back facing orientation.
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This register enables the Portrait/Landscape function and sets the behavior of the debounce counter. adjusted from a range of 65° to 80° with 5° step increments. Note: All angles are accurate to ±2°. Table 24. PL_CFG Description 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid. 0: Portrait/Landscape Detection is Disabled. 1: Portrait/Landscape Detection is Enabled. Table 25. PL_COUNT Description DBCNE[7:0] Debounce Count value. Default value: 0000_0000. Table 26. PL_COUNT Relationship with the ODR Table 27. PL_BF_ZCOMP Description BKFR[7:6] Back/Front Trip Angle Threshold. Default: 01 ≥ ±75°. Step size is 5°. ZLOCK[2:0] Z-Lock Angle Threshold. Range is from 14° to 43°. Step size is 4°. Default value: 100 ≥ 29°. Maximum value: 111 ≥ 43°.
to Landscape and Landscape to Portrait. This register includes a value for the hysteresis. Landscape and Landscape to Portrait. The default Trip Angle is 45° (0x10). The default hysteresis is ±14°. Note: THS + HYS > 0 and THS + HYS < 32 for the Landscape/Portrait detection to work correctly. All angles are accurate to ±2°. Table 28. Z-Lock Threshold Angles Table 29. Back/Front Orientation Definition
00 Z < 80° or Z > 280° Z > 100° and Z < 260°
01 Z < 75° or Z > 285° Z > 105° and Z < 255°
10 Z < 70° or Z > 290° Z > 110° and Z < 250°
11 Z < 65° or Z > 295° Z > 115° and Z < 245°
Table 30. P_L_THS_REG Description threshold angle. Default value: 1_0000 (45°). HYS[2:0] This angle is added to the threshold angle for a smoother transition from Portrait to Landscape and Landscape to Portrait. This angle ranges from 0° to ±24°. The default is 100 (±14°). Table 31. Threshold Angle Thresholds Look-up Table Table 32. Trip Angles with Hysteresis for 45° Angle
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6.4 Motion and Freefall Embedded Function Registers
The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15 bit 6). The freefall/motion detection block can be disabled by setting all three bits ZEFE, YEFE, and XEFE to zero. Depending on the register bits ELE (0x15 bit 7) and OAE (0x15 bit 6), each of the freefall and motion detection block can operate in four different modes: Mode 1: Freefall Detection with ELE = 0, OAE = 0 In this mode, the EA bit (0x16 bit 7) indicates a freefall event after the debounce counter is complete. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. Once the EA bit is set, and DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. This is because the counter is in decrement mode. If DBCNTM = 1, the EA bit is cleared as soon as the freefall condition disappears, and will not be set again before the delay specified by FF_MT_COUNT has passed. Reading the FF_MT_SRC register does not clear the EA bit. The event flags (0x16) ZHE, ZHP, YHE, YHP , XHE, and XHP reflect the motion detection status (i.e. high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Mode 2: Freefall Detection with ELE = 1, OAE = 0 In this mode, the EA event bit indicates a freefall event after the debounce counter. Once the debounce counter reaches the time value for the set threshold, the EA bit is set, and remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, the EA bit and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. While EA = 0, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP are latched when the EA event bit is set. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP will start changing only after the FF_MT_SRC register has been read. Mode 3: Motion Detection with ELE = 0, OAE = 1 In this mode, the EA bit indicates a motion event after the debounce counter time is reached. The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the EA bit is set, and DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. If DBCNTM = 1, the EA bit is cleared as soon as the motion high g condition disappears. The event flags ZHE, ZHP, YHE, YHP , XHE, and XHP reflect the motion detection status (i.e., high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Reading the FF_MT_SRC does not clear any flags, nor is the debounce counter reset. Mode 4: Motion Detection with ELE = 1, OAE = 1 In this mode, the EA bit indicates a motion event after debouncing. The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the debounce counter reaches the threshold, the EA bit is set, and remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, all register bits are cleared and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT. While the bit EA is zero, the event flags ZHE, ZHP , YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. When the EA bit is set, these bits keep their current value until the FF_MT_SRC register is read.
This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. OAE bit allows the selection between Motion (logical OR combination) and Freefall (logical AND combination) detection. EA bit gets set, and are cleared by reading the FF_MT_SRC source register. are blocked from updating the FF_MT_SRC register. X or Y or Z acceleration value is higher than the threshold value. Figure 13. FF_MT_CFG High and Low g Level Table 33. FF_MT_CFG Description flag EA and all FF_MT_SRC bits. Default value: 0. ZEFE Event flag enable on Z Default value: 0. YEFE Event flag enable on Y event. Default value: 0. XEFE Event flag enable on X event. Default value: 0.
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INT_CFG_FF_MT register bits to generate the freefall/motion interrupts. defined in the FF_MT_THS register. to the preset threshold value defined in the FF_MT_THS register. 0x2A then the maximum threshold will be limited to 4g regardless of the full scale range. impede the detection of inertial events. Table 34. Freefall/Motion Source Description Event Active Flag. Default value: 0. 0: No event flag has been asserted; 1: one or more event flag has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. Z Motion Flag. Default value: 0. Z Motion Polarity Flag. Default value: 0. Y Motion Flag. Default value: 0. Table 35. FF_MT_THS Description DBCNTM Debounce counter mode selection. Default value: 0. 0: increments or decrements debounce, 1: increments or clears counter. THS[6:0] Freefall /Motion Threshold: Default value: 000_0000.
This register sets the number of debounce sample counts for the event trigger. selected for the freefall, motion event. ODR chosen and the Oversampling mode as shown in Table 37. Table 36. FF_MT_COUNT Description Table 37. FF_MT_COUNT Relationship with the ODR
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Figure 14. DBCNTM Bit Function
6.5 Transient (HPF) Acceleration Detection
filter is bypassed, the function behaves similar to the motion detection. TRANSIENT_SRC register is read. register, all bits get cleared. Table 38. TRANSIENT_CFG Description ZTEFE Event flag enable on Z transient acceleration greater than transient threshold event. Default value: 0. 0: Event detection disabled; 1: Raise event flag on measured acceleration delta value greater than transient threshold. YTEFE Event flag enable on Y transient acceleration greater than transient threshold event. Default value: 0. 0: Event detection disabled; 1: Raise event flag on measured acceleration delta value greater than transient threshold. XTEFE Event flag enable on X transient acceleration greater than transient threshold event. Default value: 0. 0: Event detection disabled; 1: Raise event flag on measured acceleration delta value greater than transient threshold. Bypass High Pass filter Default value: 0. Table 39. TRANSIENT_SRC Description EA Event Active Flag. Default value: 0. 0: no event flag has been asserted; 1: one or more event flag has been asserted. ZTRANSE Z transient event. Default value: 0. Z_Trans_Pol Polarity of Z Transient Event that triggered interrupt. Default value: 0. YTRANSE Y transient event. Default value: 0. Y_Trans_Pol Polarity of Y Transient Event that triggered interrupt. Default value: 0. XTRANSE X transient event. Default value: 0. X_Trans_Pol Polarity of X Transient Event that triggered interrupt. Default value: 0.
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Pass Filtered acceleration value exceeds the threshold limit an event flag is raised and the interrupt is generated if enabled. 0.063g/LSB. The maximum threshold is 8g. Even if the part is set to full scale at 2g or 4g this function will still operate up to 8g. If the Low Noise bit is set in Register 0x2A the maximum threshold to be reached is 4g. unsigned value of high pass filtered data is greater than the user specified value of TRANSIENT_THS. The time step for the transient detection debounce counter is set by the value of the system ODR and the Oversampling mode. Table 40. TRANSIENT_THS Description DBCNTM Debounce counter mode selection. Default value: 0. 0: incr ements or decrements debounce; 1: increments or clears counter. THS[6:0] Transient Threshold: Default value: 000_0000. Table 41. TRANSIENT_COUNT Description D[7:0] Count value. Default value: 0000_0000. Table 42. TRANSIENT_COUNT Relationship with the ODR
6.6 Single, Double and Directional Tap Detection Registers
For more details of how to configure the tap detection and sample code please refer to Freescale application note, AN4072. The tap detection registers are referred to as “Pulse”. must be enabled in Register 0x21 for the event to be seen in the source register. PULSE_SRC register clears all bits. Reading the source register will clear the interrupt. Table 43. PULSE_CFG Description Double Pulse Abort. Default value: 0. 0: Double Pulse detection is not aborted if the start of a pulse is detected during the time period specified by the PULSE_LTCY register. by the PULSE_LTCY register and the pulse ends before the end of the time period specified by the PULSE_LTCY register. Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag. ZDPEFE Event flag enable on double pulse event on Z-axis. Default value: 0. ZSPEFE Event flag enable on single pulse event on Z-axis. Default value: 0. YDPEFE Event flag enable on double pulse event on Y-axis. Default value: 0. YSPEFE Event flag enable on single pulse event on Y-axis. Default value: 0. XDPEFE Event flag enable on double pulse event on X-axis. Default value: 0. XSPEFE Event flag enable on single pulse event on X-axis. Default value: 0. Table 44. PULSE_SRC Description EA Event Active Flag. Default value: 0. AxZ Z-axis event. Default value: 0. AxY Y-axis event. Default value: 0. AxX X-axis event. Default value: 0. DPE Double pulse on first event. Default value: 0. PolZ Pulse polarity of Z-axis Event. Default value: 0. PolY Pulse polarity of Y-axis Event. Default value: 0. PolX Pulse polarity of X-axis Event. Default value: 0.
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registers define the threshold which is used by the system to start the pulse detection procedure. detection procedure. The threshold value is expressed over 7-bits as an unsigned number. specified threshold to be considered a valid pulse. and whether the Pulse Low Pass Filter option is enabled or not. The Pulse Low Pass Filter is set in Register 0x0F.
0 THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0
Table 45. PULSE_THSX Description THSX[6:0] Pulse Threshold on X- axis. Default value: 000_0000.
0 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0
Table 46. PULSE_THSY Description THSY[6:0] Pulse Threshold on Y-axis. Default value: 000_0000.
0 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0
Table 47. PULSE_THSZ Description THSZ[6:0] Pulse Threshold on Z-axis. Default value: 000_0000. Table 48. PULSE_TMLT Description TMLT[7:0] Pulse Time Limit. Default value: 0000_0000. Table 49. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 1
pulses are ignored. Note: This timer must be set for single pulse and for double pulse. and Oversampling mode multiplied by 255. The timing also changes when the Pulse LPF is enabled or disabled. Table 50. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0 Table 51. PULSE_LTCY Description Table 52. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 53. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0
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of the double pulse need not finish within the time specified by the PULSE_WIND register. Oversampling mode and LPF Filter Option multiplied by 255. Table 54. PULSE_WIND Description WIND[7:0] Second Pulse Time Window. Default value: 0000_0000. Table 55. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 Table 56. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0
6.7 Auto-WAKE/SLEEP Detection
register. See Table 52 for functional blocks that may be monitored for inactivity in order to trigger the “return to SLEEP” event. value depend on the ODR chosen as shown in Table 58. accepting new sample data until the host application flushes the FIFO buffer. selected for WAKE from SLEEP will WAKE the device. at the current ODR. See Register 0x2C for the WAKE from SLEEP bits. interrupt is enabled, transitioning from ACTIVE mode to Auto-SLEEP mode and vice versa generates an interrupt. Table 57. ASLP_COUNT Description D[7:0] Duration value. Default value: 0000_0000. Table 58. ASLP_COUNT Relationship with ODR
200 Hz 0 to 81s 5 ms 320 ms
100 Hz 0 to 81s 10 ms 320 ms
50 Hz 0 to 81s 20 ms 320 ms
12.5 Hz 0 to 81s 80 ms 320 ms
6.25 Hz 0 to 81s 160 ms 320 ms
1.56 Hz 0 to 162s 640 ms 640 ms
Table 59. SLEEP/WAKE Mode Gates and Triggers
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6.8 Control Registers
functional blocks are overridden by the data rate set by the ASLP_RATE field. DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples. The default value is 000 for a data rate of 800 Hz. ACTIVE bit selects between STANDBY mode and ACTIVE mode. The default value is 0 for STANDBY mode. maximum signal that can be measured is ±4g. Note: Any thresholds set above 4g will not be reached. when FMODE = 00. The F_READ bit applies for both the output registers and the FIFO. Table 60. CTRL_REG1 Description ASLP_RATE[1:0] Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode. Default value: 00. See Table 61 for more information. DR[2:0] Data rate selection. Default value: 000. See Table 62 for more information. LNOISE Reduced noise reduced Maximum range mode. Default value: 0. F_READ Fast Read mode: Data format limited to single Byte Default value: 0. ACTIVE Full Scale selection. Default value: 00. Table 61. SLEEP Mode Rate Description Table 62. System Output Data Rate Selection Table 63. Full Scale Selection
0 STANDBY
ST bit activates the self-test function. When ST is set, X, Y , and Z outputs will shift. RST bit is used to activate the software reset. The reset mechanism can be enabled in STANDBY and ACTIVE mode. resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP , or STANDBY mode. The I2C communication system is reset to avoid accidental corrupted data access. At the end of the boot process the RST bit is de-asserted to 0. Reading this bit will return a value of zero. available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0]. Table 64. CTRL_REG2 Description ST Self-Test Enable. Default value: 0. RST Software Reset. Default value: 0. 0: Device reset disabled; 1: Device reset enabled. SMODS[1:0] SLEEP mode power scheme selection. Default value: 00. Auto-SLEEP enable. Default value: 0. MODS[1:0] ACTIVE mode power scheme selection. Default value: 00. Table 65. MODS Oversampling Modes
00 N o r m a l
Table 66. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR
1.56 Hz 24 128 8 32 165 1024 6 16
6.25 Hz 24 32 8 8 165 256 6 4
12.5 Hz 24 16 8 4 165 128 6 2
50 Hz 24 4 24 4 165 32 14 2
100 Hz 44 4 44 4 165 16 24 2
200 Hz 85 4 85 4 165 8 44 2
400 Hz 165 4 165 4 165 4 85 2
800 Hz 165 2 165 2 165 2 165 2
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Pull mode. The Open Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line. system’s interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin. Table 67. CTRL_REG3 Description to WAKE mode. Default value: 0. buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application. Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register. WAKE_TRANS 0: Transient function is bypassed in SLEEP mode. Default value: 0. WAKE_LNDPRT 0: Orientation function is bypassed in SLEEP mode. Default value: 0. WAKE_PULSE 0: Pulse function is bypassed in SLEEP mode. Default value: 0. WAKE_FF_MT 0: Freefall/Motion function is bypassed in SLEEP mode. Default value: 0. IPOL Interrupt polarity ACTIVE high, or ACTIVE low. Default value: 0. PP_OD Push-Pull/Open Drain selection on interrupt pad. Default value: 0. Table 68. Interrupt Enable Register Description INT_EN_ASLP Interrupt Enable. Default value: 0. 0: Auto-SLEEP/WAKE interrupt disabled; 1: Auto-SLEEP/WAKE interrupt enabled. INT_EN_FIFO Interrupt Enable. Default value: 0. 0: FIFO interrupt disabled; 1: FIFO interrupt enabled. INT_EN_TRANS Interrupt Enable. Default value: 0. 0: Transient interrupt disabled; 1: Transient interrupt enabled. Interrupt Enable. Default value: 0. 0: Orientation (Landscape/Portrait) interrupt disabled. 1: Orientation (Landscape/Portrait) interrupt enabled. INT_EN_PULSE Interrupt Enable. Default value: 0. INT_EN_FF_MT Interrupt Enable. Default value: 0. INT_EN_DRDY Interrupt Enable. Default value: 0.
6.9 User Offset Correction Registers
Table 69. Interrupt Configuration Register Description INT_CFG_ASLP INT1/INT2 Configuration. Default value: 0. INT_CFG_TRANS INT1/INT2 Configuration. Default value: 0. INT_CFG_LNDPRT INT1/INT2 Configuration. Default value: 0. INT_CFG_PULSE INT1/INT2 Configuration. Default value: 0. INT_CFG_FF_MT INT1/INT2 Configuration. Default value: 0. INT_CFG_DRDY INT1/INT2 Configuration. Default value: 0. Table 70. OFF_X Description D[7:0] X-axis offset value. Default value: 0000_0000. Table 71. OFF_Y Description D[7:0] Y-axis offset value. Default value: 0000_0000. Table 72. OFF_Z Description D[7:0] Z-axis offset value. Default value: 0000_0000.
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Table 73. MMA8451Q Register Map
00 STATUS/F_STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR
01 OUT_X_MSB 14 bit X Data R XD13 XD12 XD11 XD10 XD9 XD8 XD7 XD6
02 OUT_X_LSB 14 bit X Data R XD5 XD4 XD3 XD2 XD1 XD0 0 0
03 OUT_Y_MSB 14 bit Y Data R YD13 YD12 YD11 YD10 YD9 YD8 YD7 YD6
04 OUT_Y_LSB 14 bit Y Data R YD5 YD4 YD3 YD2 YD1 YD0 0 0
05 OUT_Z_MSB 14 bit Z Data R ZD13 ZD12 ZD11 ZD10 ZD9 ZD8 ZD7 ZD6
06 OUT_Z_LSB 14 bit Z Data R ZD5 ZD4 ZD3 ZD2 ZD1 ZD0 0 0
09 F_SETUP FIFO Set-up R/W F_MODE1 F_MODE0 F_WMRK5 F_WMRK4 F_WMRK3 F_WMRK2 F_WMRK1 F_WMRK0
10 PL_STATUS PL Status R NEWLP LO — — — LAPO[1] LAPO[0] BAFRO
11 PL_CFG PL Configuration R/W DBCNTM PL_EN — — — — — —
12 PL_COUNT PL DEBOUNCE R/W DBNCE[7] DBNCE[6] DBNCE [5] DBNCE[4] DBNCE[3] DBNCE[2] DBNCE[1] DBNCE[0]
13 PL_BF_ZCOMP PL Back/Front Z Comp
15 FF_MT_CFG Freefall/Motion Config
16 FF_MT_SRC Freefall/Motion Source
17 FF_MT_THS Freefall/Motion Threshold
18 FF_MT_COUNT Freefall/Motion Debounce
20 TRANSIENT_COUNT Transient Debounce
21 PULSE_CFG Pulse Config R/W DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE
22 PULSE_SRC Pulse Source R EA AxZ AxY AxX DPE Pol_Z Pol_Y Pol_X
23 PULSE_THSX Pulse X Threshold R/W — THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0
24 PULSE_THSY Pulse Y Threshold R/W — THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0
25 PULSE_THSZ Pulse Z Threshold R/W — THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0
26 PULSE_TMLT Pulse First Timer R/W TMLT7 TMLT6 TMLT5 TMLT4 TMLT3 TMLT2 TMLT1 TMLT0
27 PULSE_LTCY Pulse Latency R/W LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0
28 PULSE_WIND Pulse 2nd Window
29 ASLP_COUNT Auto-SLEEP Counter
30 OFF_Y Y 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0
31 OFF_Z Z 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0
Table 74. Accelerometer Output Data
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Freescale Semiconductor 51 MMA8451Q PACKAGE DIMENSIONS CASE 2077-01 ISSUE O 16-LEAD Q
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