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Technical content

Features

  • 1.71V to 1.89V supply voltage
  • ±2g/±4g/±8g dynamicall y selectable full-scale
  • Output Data Rate (ODR) from 400 Hz to 1.563 Hz
  • 375 μg/√Hz noise at normal mode ODR = 400 Hz
  • 12-bit digital output 2C digital output interface (operates up to 400 kHz Fast Mode)
  • Programmable two interrupt pins for eight interrupt sources
  • Embedded four channels of motion detection – Freefall or motion detection: 2 channels – Pulse Detection: 1 channel – Transient (Jolt) Detection: 1 channel
  • Orientation (Portrait/Landscape) detection with hysteresis compensation
  • Automatic ODR change for auto-wake and return-to-sleep
  • 32 sample FIFO
  • Self-Test
  • 10,000g high shock survivability
  • RoHS compliant Typical Applications
  • Static orientation detection (portrait/landscape, up /down, left/right, back/front position identification)
  • Real-time orientation detection (virtual r eality and gaming 3D user position feedback)
  • Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)
  • Motion detection for portable product power saving (aut o-sleep and auto-wake for cell phone, PDA, GPS, gaming)
  • Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)
  • User interface (menu scrolling by orientation change, tap detection for button replacement

ORDERING INFORMATION

Part Number Temperature Range Package Description Shipping MMA8450QT -40°C to +85°C QFN-16 Tray MMA8450QR1 -40°C to +85°C QFN-16 Tape and Reel

16 PIN QFN

2 Freescale Semiconductor, Inc. Related Documentation The MMA8450Q device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at: http://www.freescale.com/ 2. In the Keyword search box at the top of the page, enter the device number MMA8450Q. 3. In the Refine Your Result pane on the left, click on the Documentation link.

Contents

1 Block Diagram and Pin Description

1.1 Block Diagram

Figure 1. Block Diagram

1.2 Pin Description

Figure 2. Direction of the Detectable Accelerations

32 Data Point

1.3 Soldering Information

The QFN package is compliant with the RoHS standard. Please refer to AN4077. Table 1. Pin Description

2 NC/GND Connect to Ground or Non Connection Input

3 NC/GND Connect to Ground or Non Connection Input

5 GND Connect to Ground Input

7 SA0 I2C Least Significant Bit of the Device Address

9 INT2 Inertial Interrupt 2 Output

10 GND Connect to Ground Input

11 INT1 Inertial Interrupt 1 Output

12 GND Connect to Ground Input

13 GND Connect to Ground Input

15 NC Internally not connected Input

16 NC Internally not connected Input

6 Freescale Semiconductor, Inc.

2 Mechanical and Electr ical Specifications

2.1 Mechanical Characteristics

Table 2. Mechanical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted.

  1. See appendix for distribution graphs.
  2. Post board mount offset specification are based on an 8 layer PCB.
  3. Self-test in one direction only. These are approximate values and can change by ±100 counts.

2.2 Electrical Characteristics

Table 3. Electrical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted.(1)

  1. Time to obtain valid data from Standby mode to Active mode.

8 Freescale Semiconductor, Inc.

2.3 I 2C Interface Characteristic

Table 4. I2C Slave Timing Values(1)

  1. All values referred to VIH (min) and VIL (max) levels.
  2. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
  3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

  1. The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or tVD;ACK

stretches the SCL, the data must be valid by the setup time before it releases the clock.

  1. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
  2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
  3. A Fast-mode I2C device can be used in a Standard-mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will
  4. Cb = total capacitance of one bus line in pF.
  5. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.

Figure 5. I2C Slave Timing Diagram

2.4 Absolute Maximum Ratings

maximum rating conditions for extended periods may affect device reliability. Table 5. Maximum Ratings Table 6. ESD and Latchup Protection Characteristics cause the part to otherwise fail. This is an ESD sensitive, improper handling can cause permanent damage to the part.

10 Freescale Semiconductor, Inc.

3 Terminology

3.1 Sensitivity

acceleration value and dividing by two.

3.2 Zero-g Offset

sensor in a steady state on a horizontal surface will measure 0g in X-axis and 0g in Y-axis whereas the Z-axis will measure 1g. exposing it to extensive mechanical stress.

3.3 Self-Test

4 Modes of Operation

Figure 6. MMA8450Q Mode Transition Diagram the Sleep and Wake modes and how to transition between these modes, please refer to the functionality section of this document. Table 7. Mode of Operation Description OFF Powered Down <1.5 V <VDD + 0.3 V The device is powered off. SHUTDOWN I2C communication ignored ON EN = Low All analog & digital blocks are shutdown. Only POR and digital blocks are enabled. Analog subsystem is disabled. Registers accessible for Read/Write. Device configuration done in this mode. All blocks are enabled (POR, digital, analog).

Freescale Semiconductor, Inc. 11

5 Functionality

The MMA8450Q is a low-power, digital output 3-axis linear accelerometer packaged in a QFN package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C serial interface. There are many embedded features in this accelerometer with a very flexible interrupt routing scheme to two interrupt pins including:

  • 8-bit or 12-bit data, high pass filtered data, 8-bit or 12-bit configurable 32 sample FIFO
  • Low power and Auto-Wake/Sleep for co nservation of current consumption
  • Single and double pulse detection 1 channel
  • Motion detection and Freefall 2 channels
  • Transient detection based on a high pa ss filter and settable threshold for detecting the change in acceleration above a threshold
  • Flexible user configurable portrait landscape detection algorithm addressing many use cases for screen orientation All functionality is available in 2g, 4g or 8g dynamic ranges. There are many configuration settings for enabling all the different functions. Separate application notes have been provided to help configure the device for each embedded functionality.

5.1 Device Calibration

The IC interface is factory calibrated for sensitivity and Zero-g offset for each axis. The trim values are stored in Non Volatile Memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry. In normal use, further calibration in the end application is not necessary. However, the MMA8450Q allows the user to adjust the Zero-g offset for each axis after power-up, changing the default offset values. The user offset adjustments are stored in 6 volatile registers. For more information on device calibration, refer to Freescale application note, AN3916. 5.2 8-bit or 12-bit Data The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 12-bit numbers. The most significant 8-bits of each axis are stored in OUT_X (Y, Z)_MSB, so applications needing only 8-bit results can use these 3 registers and ignore OUT_X(Y, Z)_LSB. When the full-scale is set to 2g, the measurement range is -2g to +1.999g, and each LSB corresponds to 1g/1024 (0.98 mg) at 12-bits resolution. When the full-scale is set to 8g, the measurement range is -8g to +7.996g, and each LSB corresponds to 1g/256 (3.9 mg) at 12-bits resolution. The resolution is reduced by a factor of 16 if only the 8-bit results are used. For more information on the data manipulation between data formats and modes, refer to Freescale application note, AN3922. There is a device driver available that can be used with the Sensor Toolbox demo board (LFSTBEB8450Q) with this application note.

5.3 Internal FIFO Data Buffer

MMA8450Q contains a 32 sample internal FIFO data buffer minimizing traffic across the I2C bus. The FIFO can also provide power savings of the system by allowing the host processor/MCU to go into a sleep mode while the accelerometer independently stores the data, up to 32 samples per axis. The FIFO can run at all output data rates. There is the option of accessing the full 12- bit data for accessing only the 8-bit data. When access speed is more important than high resolution the 8-bit data flush is a better option. The FIFO contains three modes (Fill Buffer Mode, Circular Buffer Mode, and Disabled) described in the F_SETUP Register 0x13. Fill Buffer Mode collects the first 32 samples and asserts the overflow flag when the buffer is full. It does not collect anymore data until the buffer is read. This benefits data logging applications where all samples must be collected. The Circular Buffer Mode allows the buffer to be filled and then new data replaces the oldest sample in the buffer. The most recent 32 samples will be stored in the buffer. This benefits situations where the processor is waiting for an specific interrupt to signal that the data must be flushed to analyze the event. The MMA8450Q FIFO Buffer also has a configurable watermark, allowing the processor to be interrupted after a configurable number of samples has filled in the buffer (1 to 32). For details on the configurations for the FIFO Buffer as well as more specific examples and application benefits, refer to Freescale application note, AN3920.

5.4 Low Power Mode

The MMA8450Q can be set to a low power mode to further reduce the current consumption of the device. When the Low Power Mode is enabled, the device has access to all the configurable sampling rates and features as is available in the Normal power mode. To set the device into Low Power Mode, bit 0 in the System Control Register 2 (0x39) should be set (1) (this bit is cleared (0) for Normal Power Mode). Low Power Mode reduces the current consumption by internally sleeping longer and averaging the data less. The Low Power Mode is an additional feature that is independent of the sleep feature.The sleep feature can also be used to reduce the current consumption by automatically changing to a lower sample rate when no activity is detected. For more information on how to configure the MMA8450Q in Low Power Mode and the power consumption benefits of Low Power Mode and Auto-Wake/Sleep with specific application examples, refer to Freescale application note, AN3921.

12 Freescale Semiconductor, Inc.

5.5 Auto-Wake/Sleep Mode

The MMA8450Q can be configured to transition between sample rates (with their respective current consumption) based on five of the interrupt functions of the device. The advantage of using the Auto-Wake/Sleep is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the Sleep Mode (lower current) when the device does not require higher sampling rates. Auto-Wake refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This may also interrupt the processor to transition from a sleep mode to a higher power mode. Sleep Mode occurs after the accelerometer has not detected an interrupt for longer than the user definable timeout period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save on current during this period of inactivity. The Interrupts that can wake the device from sleep are the following: Tap Detection, Orientation Detection, Motion/Freefall1, Motion/Freefall2, and Transient Detection. The FIFO can be configured to hold the data in the buffer until it is flushed if the FIFO Gate bit is set in Register 0x3A but the FIFO cannot wake the device from sleep. The interrupts that can keep the device from falling asleep are the same interrupts that can wake the device with the addition of the FIFO. If the FIFO interrupt is enabled and data is being accessed continually servicing the interrupt then the device will remain in the wake mode. Refer to AN3921, for more detailed information for configuring the Auto-Wake/Sleep and for application examples of the power consumption savings.

5.6 Freefall and Motion Detection

MMA8450Q has flexible interrupt architecture for detecting Freefall and Motion with the two Motion/Freefall interrupt functions available. With two configurable interrupts for Motion and Freefall, one interrupt can be configured to detect a linear freefall while the other can be configured to detect a spin motion. The combination of these two events can be routed to separate interrupts or to the same interrupt pin to detect tumble which is the combination of spin with freefall. For details on the advantages of having the two embedded functions of Freefall and Motion detection with specific application examples with recommended configuration settings, refer to Freescale application note AN3917.

5.6.1 Freefall Detection

The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user specified threshold for a user definable amount of time. Normally the usable threshold ranges are between ±0 mg and ±500 mg.

5.6.2 Motion Detection

There are two programmable functions for motion (MFF1 and MFF2). Motion is configured using the high-g mechanism. Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2g. This condition would need to occur for a minimum of 100 ms to ensure that the event wasn't just noise. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for configurable set of time (i.e., 100 ms or longer).

5.7 Transient Detection

The MMA8450Q has a built in high pass filter. Acceleration data goes through the high pass filter, eliminating the offset (DC) and low frequencies. The high pass filter cutoff frequency can be set by the user to four different frequencies which are dependent on the Output Data Rate (ODR). A higher cutoff frequency ensures the DC data or slower moving data will be filtered out, allowing only the higher frequencies to pass. The embedded Transient Detection function uses the high pass filtered data allowing the user to set the threshold and debounce counter. Many applications use the accelerometer’s static acceleration readings (i.e., tilt) which measure the change in acceleration due to gravity only. These functions benefit from acceleration data being filtered from a low pass filter where high frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the acceleration. It is simpler to interpret these functions dependent on dynamic acceleration data when the static component has been removed. The Transient Detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 Register (0x3C). Registers 0x2B – 0x2E are the dedicated Transient Detection configuration registers. For details on the benefits of the embedded Transient Detection function along with specific application examples and recommended configuration settings, please refer to Freescale application note, AN3918.

5.8 Orientation Detection

and uncompensated board mount offset, however, it may result in slight angle variations. The MMA8450Q Orientation Detection algorithm confirms the reliability of the function with a configurable Z-lockout angle. different settings for the Z-Angle lockout. system. The MMA8450Q allows for configuring the 1g Lockout Threshold from 1g up to 1.35g (in increments of 0.05g). configuring the device to support various application use cases, refer to Freescale application note, AN3915. Figure 7. Illustration of Landscape-to-Portrait Transition Figure 8. Illustration of Portrait-to-Landscape Transition

14 Freescale Semiconductor, Inc. detection as low as 25° from flat. This is user configurable. The default angle is 32° but it can be set as low as 25°. Figure 9. Illustration of Z-Tilt Angle Lockout Transition

5.9 Interrupt Register Configurations

the corresponding interrupt pin, INT1 or INT2, will assert. Figure 10. System Interrupt Generation Block Diagram

5.10 Serial I 2C Interface

Freefall, Transient, Orientation, and Tap. I/O pin to be either high or low, depending on the desired state. To enable the I2C interface, the EN pin (pin 8) must be tied high. When EN is tied low, MMA8450Q is put into low power shutdown mode and communications on the I2C interface are ignored. EN is tied low and the MMA8450Q does not clamp the I2C bus.

(400 kHz), and normal mode (100 kHz) I2C standards (Table 4). Table 8. Serial Interface Pin Description

16 Freescale Semiconductor, Inc.

5.10.1 I 2C Operation

stable low during the high period of the acknowledge clock period. continues when the receiver is ready for another byte and releases the data line. This delay action is called clock stretching. repeated STARTs to be used to randomly read from specific registers. programmed and alternate addresses are available at customer request. The format is shown in Table 9. transmitted data, but transmits a stop condition to end the data transfer. the Master followed by a stop condition (SP) signaling an end of transmission. Table 9. I2C Address Selection Table

The MMA8450Q automatically increments the received register address commands after a write command is received. MMA8450Q acknowledgment (ACK) is received. Figure 11. I2C Timing Diagram Table 10. I2C device Address Sequence

18 Freescale Semiconductor, Inc.

6 Register Descriptions

differences between the MSBs located in 0x01, 0x02, 0x03 and 0x06, 0x08, 0x0A. Table 11. Register Address Map WHO_AM_I(1) R 0x0F 0xC6 11000110 NVM Programmable Fixed Device ID No. Landscape/Portrait configuration. 1g Lockout offset is set to default value of 1.15g. PL_BF_ZCOMP(1)(4) R/W 0x1C 0x1D 00000010 Back-Front Trip threshold is ±75°.

  1. Register contents are preserved when transition from “ACTIVE” to “STANDBY” mode occurs.
  2. Register contents are reset when transition from “STANDBY” to “ACTIVE” mode occurs.
  3. Modification of this register’s contents can only occur when device is “STANDBY” mode
  4. Register contents can be modified anytime in “STANDBY” or “ACTIVE” mode. A write to this register will cause a reset of the corresponding

internal system debounce counter.

20 Freescale Semiconductor, Inc.

6.1 Data Registers

to application note, AN3922. address auto-incrementing mechanism. ZOW is set whenever a new acceleration sample related to the Z-axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. ZOW is cleared anytime OUT_Z_MSB register is read. YOW is set whenever a new acceleration sample related to the Y-axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. YOW is cleared anytime OUT_Y_MSB register is read. XOW is set whenever a new acceleration sample related to the X-axis is generated before the retrieval of the previous sample. When this occurs the previous sample is overwritten. XOW is cleared anytime OUT_X_MSB register is read. acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the enabled channels are read. enabled (bit ZDEFE = 1 inside XYZ_DATA_CFG register). Table 12. STATUS Description

Freescale Semiconductor, Inc. 21 YDR is set whenever a new acceleration sample related to the Y-axis is available. YDR is cleared anytime OUT_Y_MSB register is read. In order to enable the monitoring and assertion of this bit, the YDR bit requires the Y-axis event detection flag to be enabled (bit YDEFE = 1 inside XYZ_DATA_CFG register). XDR is set to 1 whenever a new acceleration sample related to the X-axis is available. XDR is cleared anytime OUT_X_MSB register is read. In order to enable the monitoring and assertion of this bit, the XDR bit requires the X-axis to event detection flag to be enabled (bit XDEFE = 1 inside XYZ_DATA_CFG register). The ZDR and ZOW flag generation requires the Z-axis event flag generator to be enabled (ZDEFE = 1) in the XYZ_DATA_CFG register. The YDR and YOW flag generation requires the Y-axis event flag generator to be enabled (YDEFE = 1) in the XYZ_DATA_CFG register. The XDR and XOW flag generation requires the X-axis event flag generator to be enabled (XDEFE = 1) in the XYZ_DATA_CFG register. The ZYXDR and ZYXOW flag generation is requires the Z-axis, Y-axis, X-axis event flag generator to be enabled (ZDEFE = 1, YDEFE = 1, XDEFE = 1) in the XYZ_DATA_CFG register. 0x01, 0x02, 0x03: OUT_MSB 8-Bit XYZ Data Registers X, Y and Z-axis data is expressed as 2’s complement numbers. The most significant 8-bits are stored together in OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB so applications needing only 8-bit results can use these registers and can ignore the OUT_X_LSB, OUT_Y_LSB, OUT_Z_LSB. The status Register 0x00, OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB are duplicated in the auto-incrementing address range of 0x00 to 0x03 to reduce reading the status followed by 8-bit axis data to a 4 byte sequence. 0x05 - 0x0A: OUT_MSB and OUT_LSB 12-Bit XYZ Data Registers X, Y and Z-axis data is expressed as 2’s complement numbers. The STATUS (0x04), OUT_X_LSB (0x05), OUT_X_MSB (0x06), OUT_Y_LSB (0x07), OUT_Y_MSB (0x08), OUT_Z_LSB(0x09), OUT_Z_MSB (0x0A) are stored in auto-incrementing address range of 0x04 to 0x0A to reduce reading the status followed by 12-bit axis data to 7 bytes. 0x01 OUT_X_MSB: X_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 0x02 OUT_Y_MSB: Y_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 0x03 OUT_Z_MSB: Z_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4 0x05 OUT_X_LSB: X_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 XD3 XD2 XD1 XD0 0x06 OUT_X_MSB: X_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 0x07 OUT_Y_LSB: Y_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000 Y D3 Y D2 Y D1 Y D0

0x08 OUT_Y_MSB: Y_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 0x09 OUT_Z_LSB: Z_LSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000 Z D3 Z D2 Z D1 Z D0

0x0A OUT_Z_MSB: Z_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4

22 Freescale Semiconductor, Inc. contains the previous 32 X, Y, and Z data samples. This applies for the 8-bit data and the 12-bit data. 0x0A returns a value of 0x00. removed. The value of the high pass filter cutoff frequency is set in Register 0x17. of the FIFO data output register driver bit. Register 0x0B always reflects the status of the delta data. by a byte of NVM. A custom alternate value can be set by customer request. information on the FIFO please refer to AN3920. watermark. It also has a counter that can be read to obtain the number of samples stored in the buffer. interrupt bit flag in the interrupt source register (INT_SOURCE) by reading the F_STATUS register. asserted while the F_CNT value is greater than the F_WMRK value. Table 13. FIFO Flag Event Description 0 — No FIFO overflow events detected. 1 — FIFO event detected; FIFO has overflowed. — 0 No FIFO watermark events detected. — 1 FIFO event detected; FIFO sample count is greater than watermark value.

the sample data, since it is represented by only 3 bytes per sample (OUT_X_MSB, OUT_Y_MSB, and OUT_Z_MSB). maximum of 3 x 32 = 96 data bytes of samples can be read. The FIFO will not accumulate more sample data during an access to F_8DATA until a STOP or repeated START occurs. address location 0x01 or 0x05. sample data, since it is represented by only 3 bytes per sample (OUT_X_MSB, OUT_Y_MSB, and OUT_Z_MSB). reads to the register address 0x02, 0x03, 0x06, 0x07, 0x08, 0x09, and 0x0A return a value of 0x00. The FIFO will not accumulate more sample data during an access to F_12DATA until a STOP or repeated START occurs. maximum number of samples is 32. For more information on the FIFO configuration refer to AN3920. Table 14. FIFO Sample Count Description F_CNT[5:0] FIFO sample counter. Default value: 00_0000.

0000 X D3 X D2 X D1 X D0

24 Freescale Semiconductor, Inc. Auto-Sleep is active the ODR is set by the ASLP_RATE field in the CTRL_REG1 register. multi-read transaction to empty the FIFO. register also indicates the status of the NVM parity error and FIFO gate error flags. buffer clears the FGERR bit. Table 15. F_SETUP Description FIFO buffer overflow mode. Default value: 0. 10: FIFO stops accepting new samples when overflowed. transitioning from “STANDBY” mode to “ACTIVE” mode. Disabling the FIFO (F_MODE = 00) resets the F_OVF, F_WMRK_FLAG, F_CNT to zero. sample count watermark (i.e., F_WMRK) asserts the F_WMRK_FLAG event flag. FIFO Event Sample Count Watermark. Default value: 00_0000. Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation.

  1. Bit field can be written in ACTIVE mode.
  2. Bit field can be written in STANDBY mode.
  3. The FIFO mode (F_MODE) cannot be switched between the two operational modes (01and 10) in Active Mode.

Table 16. SYSMOD Description NVM Parity Error Flag Bit. Default Value: 0. 0: No NVM parity error was detected. 1: NVM parity error detected. FIFO Gate Error. Default value: 0. 0: No FIFO Gate Error detected. 1: FIFO Gate Error was detected. System Mode. Default value: 00.

and are cleared by reading the appropriate interrupt source register. Table 17. INT_SOURCE Description Logic ‘0’ indicates that no “Wake-to-Sleep” or “Sleep-to-Wake” system mode transition interrupt event has occurred. (ASLP_COUNT). This causes the system to transition to a user specified low ODR setting. system to transition to a user specified high ODR setting. Reading the SYSMOD register clears the SRC_ASLP bit. that no FIFO interrupt event has occurred. This bit is cleared by reading the F_STATUS register. indicates that no transient event has occurred. This bit is asserted whenever “EA” bit in the TRANS_SRC is asserted and the interrupt has been enabled. This bit is cleared by reading the TRANS_SRC register. that no change in orientation status was detected. This bit is asserted whenever “NEWLP” bit in the PL_STATUS is asserted and the interrupt has been enabled. This bit is cleared by reading the PL_STATUS register. This bit is asserted whenever “EA” bit in the PULSE_SRC is asserted and the interrupt has been enabled. This bit is cleared by reading the PULSE_SRC register. Logic ‘1’ indicates that the Freefall/Motion1 function interrupt is active. Logic ‘0’ indicates that no Freefall or Motion event was detected. This bit is cleared by reading the FF_MT_SRC_1 register. Logic ‘1’ indicates that the Freefall/Motion2 function interrupt is active. Logic ‘0’ indicates that no Freefall or Motion event was detected. This bit is cleared by reading the FF_MT_SRC_2 register. Logic ‘1’ indicates that the X,Y,Z data ready interrupt is active indicating the presence of new data and/or data overrun. Otherwise if it is a logic ‘0’ the X,Y,Z interrupt is not active. This bit is asserted when the ZYXOW and/or ZYXDR is set and the interrupt has been enabled. This bit is cleared by reading the STATUS and X, Y, or Z register.

26 Freescale Semiconductor, Inc. The XYZ_DATA_CFG register configures the 3-axis acceleration data and event flag generator based on the ODR.

6.3 Portrait/ Landscape Em bedded Function Registers

Table 18. XYZ_DATA_CFG Description FIFO Data Output Register Driver Enable. Default value: 0. 1: The sample data output registers point to the previously stored X, Y, & Z samples data in the FIFO buffer. ZDEFE Data Event Flag Enable on new Z-axis data. Default value: 0. YDEFE Data Event Flag Enable on new Y-axis data. Default value: 0. XDEFE Data Event Flag Enable on new X-axis data. Default value: 0. Table 19. HP_FILTER_CUTOFF Setting Options

has been described in Register 0x18. from ACTIVE to STANDBY or vice versa resets the internal landscape/portrait internal debounce counters. the relationship between the ODR, the step per count and the duration. Table 20. PL_STATUS Register Description NEWLP Landscape-Portrait status change flag. Default value: 0. Z-Tilt Angle Lockout. Default value: 0. 0: Lockout condition has not been detected. 1: Z-Tilt lockout trip angle has been exceeded. Lockout has been detected. Back or Front orientation. Default value: 00. 00: Undefined. This is the default power up state. 01: Front: Device is in the front facing orientation. 10: Back: Device is in the back facing orientation. Landscape/Portrait orientation. Default value: 000. 000: Undefined. This is the default power up state.

  1. The default power up state is BAFRO (Undefined), LAPO (Undefined), and no Lockout for orientation function.

Table 21. PL_CFG Register Description Debounce counter mode selection. Default value: 1. 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid. Portrait-Landscape Detection Enable. Default value: 0. 0: Portrait-Landscape Detection is Disabled. 1: Portrait-Landscape Detection is Enabled. 1g lockout threshold offset expressed in steps of 50 mg. Default value: 011 = 1.15g. The offset specified by the GOFF is added or subtracted from 1g to achieve the optimal 1g lockout threshold.

28 Freescale Semiconductor, Inc. adjusted from a range of 65° to 80° with 5° step increments. and the corresponding values for that angle should be written into the three PL_P_L_THS Registers. Table 22. PL_COUNT Relationship with the ODR Table 23. PL_BF_ZCOMP Description ZLOCK Z-Lock Angle Threshold. Range is from 25° to 50°. Step size is 3.6°. Default value: 010 ≥ 32.1°. Maximum value: 111 ≥ 50°. BKFR Back Front Trip Angle Threshold. Default: 10 ≥ ±75°. Step size is 5°. Table 24. Back/Front Orientation Definitions

00 Z < 80° or Z > 280° Z > 100° and Z < 260°

01 Z < 75° or Z > 285° Z > 105° and Z < 255°

10 Z < 70° or Z > 290° Z > 110° and Z < 250°

11 Z < 65° or Z > 295° Z > 115° and Z < 245°

Table 25. PL_P_L_THS_REG1 Description P_L_THS Portrait-to-Landscape Threshold Register 1. Default value: 30° → 0001_1010. Table 26. PL_P_L_THS_REG2 Description P_L_THS Portrait-to-Landscape Threshold Register 2. Default value: 30° → 0010_0010.

and the corresponding values for that angle should be written into the three PL_L_P_THS Registers. Table 27. PL_P_L_THS_REG3 Description P_L_THS Portrait-to-Landscape Threshold Register 3. Default value: 30°→ 1101_0100. Table 28. Portrait-to-Landscape Trip Angle Thresholds Lookup Table Table 29. PL_L_P_THS_REG1 Description L_P_THS Landscape-to-Portrait Threshol d Register 1. Default value: 60° → 0010_1101. Table 30. PL_L_P_THS_REG2 Description L_P_THS Landscape-to-Portrait Threshol d Register 2. Default value: 60° → 0100_0001. Table 31. PL_L_P_THS_REG3 Description L_P_THS Landscape-to-Portrait Threshol d Register 3. Default value: 60° → 1010_0010.

30 Freescale Semiconductor, Inc.

6.4 Freefall & Motion Detection Registers

combination of X, Y, Z-axis event flags) detection. by reading the FF_MT_SRC_1 source register. higher than the threshold set in FF_MT_THS_1 register. than the threshold set in FF_MT_THS_1 register. event detection where the magnitude of the X, or Y, or Z-axis acceleration values is higher than the threshold value. Table 32. Landscape-to-Portrait Trip Angle Thresholds Lookup Table Table 33. FF_MT_CFG_1 Description event flag. Default value: 0. OAE Logical Or/And combination of events flags. Default value: 0. ZHEFE Event flag enable on Z High event. Default value: 0. ZLEFE Event flag enable on Z Low event. Default value: 0. YHEFE Event flag enable on Y High event. Default value: 0. YLEFE Event flag enable on Y Low event. Default value: 0. XHEFE Event flag enable on X High event. Default value: 0. XLEFE Event flag enable on X Low event. Default value: 0.

INT_CFG_FF_MT_1 register to generate the Freefall/Motion interrupts. preset threshold value defined in the FF_MT_THS_1 register. than the preset threshold value defined in the FF_MT_THS_1 register. the register must be read immediately. The EA bit will remain high until the source register is read.

  • If the selected acceleration g range is 8g mode (FS = 11), the minimum threshold resolution is 0.063g/LSB. The maximum value is 8g.
  • If the selected acceleration g range is 4g mode (FS = 10), the minimum threshold resolution is 0.0315g/LSB. The maximum value is 4g.
  • If the selected acceleration g range is 2g mode (FS = 01), the minimum threshold resolution is 0.01575g/LSB. The maximum value is 2g. When DBCNTM bit is a logic ‘1’, the debounce counter is cleared to 0 whenever the event of interest is no longer true (Figure 12 part b) while if the DBCNTM bit is set a logic ‘0’ the debounce counter is decremented by 1 whenever the event of interest is no longer true (Figure 12 part c) until the debounce counter reaches 0 or the event of interest becomes active. Decrementing of the debounce counter acts as a median filter enabling the system to filter out irregular spurious events which might impede the detection of the event. 0x24: FF_MT_SRC_ Freefall and Motion Source Register (0x24) (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — EA ZHE ZLE YHE YLE XHE XLE

Table 34. FF_MT_SRC_1 Description EA Event Active Flag. Default value: 0. 0: No event flag has been asserted; 1: one or more event flags have been asserted. ZHE Z High Event Flag. Default value: 0. ZLE Z Low Event Flag. Default value: 0. YHE Y High Event Flag. Default value: 0. YLE Y Low Event Flag. Default value: 0. XHE X High Event Flag. Default value: 0. XLE X Low Event Flag. Default value: 0. Table 35. FF_MT_THS_1 Description DBCNTM Debounce counter mode selection. Default value: 0. 0: increments or decrements debounce, 1: increments or clears counter.

32 Freescale Semiconductor, Inc. Figure 12. DBCNTM Bit Function This register sets the number of debounce sample counts for the event trigger. An ODR of 100 Hz and a FF_MT_COUNT_1 value of 15 would result in a debounce response time of 150 ms. Table 36. FF_MT_COUNT_1 Description D[7-0] Count value. Default value: 0000_0000. Table 37. FF_MT_COUNT_1 and FF_MT_COUNT_2 Relationship with the ODR

These registers all have the same descriptions as above for Registers 0x23 - 0x26.

6.5 Transient Detection Registers

For more information on the uses of the transient function and sample code, refer to application note AN3918. mechanism for each of the 3 axes (X, Y, Z) of acceleration. cleared by reading the status register. Table 38. TRANSIENT_ CFG Description ZTEFE Event flag enable on Z-axis. Default value: 0. YTEFE Event flag enable on Y-axis. Default value: 0. XTEFE Event flag enable on X-axis. Default value: 0.

34 Freescale Semiconductor, Inc.

  • If the selected acceleration g range is 8g mode (FS = 11), the minimum threshold resolution is 0.063g/LSB. The maximum is 8g.
  • If the selected acceleration g range is 4g mode (FS = 10), the minimum threshold resolution is 0.0315g/LSB. The maximum is 4g.
  • If the selected acceleration g range is 2g mode (FS = 01), the minimum threshold resolution is 0.01575g/LSB. The maximum is 2g.
  • The DBCNTM bit behaves in the same manner de scribed previously for the Motion/Freefall 1. 0x2E: TRANSIENT_COUNT Transient Debounce Register The TRANSIENT_COUNT sets the minimum number of debounce counts continuously matching the condition where the unsigned value of OUT_X_DELTA or OUT_Y_DELTA or OUT_Z_DELTA register is greater than the user specified value of TRANSIENT_THS. The time step for the Transient detection debounce counter is set by the value of the system ODR. An ODR of 100 Hz and a TRANSIENT_COUNT value of 15 would result in a debounce response time of 150 ms.

Table 39. TRANSIENT_SRC Description EA Event Active Flag. Default value: 0. 0: No event flag asserted; 1: one or more event flag has been asserted. ZTRANSE Z transient event. Default value: 0. YTRANSE Y transient event. Default value: 0. XTRANSE X transient event. Default value: 0. Table 40. TRANSIENT_THS Description Table 41. TRANSIENT_COUNT Description D[7-0] Count value. Default value: 0000_0000. Table 42. TRANSIENT_COUNT Relationship with the ODR

6.6 Tap Detection Registers

For more details of how to configure the tap detection and sample code please refer to Freescale application note, AN3919. The tap detection registers are referred to as “Pulse”. Table 43. PULSE_CFG Description Pulse event flags are latched into the PULSE_SRC register. Reading of the PULSE_SRC register clears the event flag. ZDPEFE Event flag enable on double pulse event on Z-axis. Default value: 0. ZSPEFE Event flag enable on single pulse event on Z-axis. Default value: 0. YDPEFE Event flag enable on double pulse event on Y-axis. Default value: 0. YSPEFE Event flag enable on single pulse event on Y-axis. Default value: 0. XDPEFE Event flag enable on double pulse event on X-axis. Default value: 0. XSPEFE Event flag enable on single pulse event on X-axis. Default value: 0. Table 44. TPULSE_SRC Description ZDPE Double pulse on Z-axis event. Default value: 0. ZSPE Single pulse on Z-axis event. Default value: 0. YDPE Double pulse on Y-axis event. Default value: 0. YSPE Single pulse on Y-axis event. Default value: 0. XDPE Double pulse on X-axis event. Default value: 0. XSPE Single pulse on X-axis event. Default value: 0.

36 Freescale Semiconductor, Inc. pulse detection procedure. The threshold value is expressed over 5-bits as an unsigned number. specified threshold to be considered a valid pulse. Power mode or in Low Power mode. Notice in the table below that the time step is twice as long in Low Power mode. Table 45. PULSE_THSX Description THSX4, THSX0 Pulse Threshold on X-axis. Default value: 0_0000. Table 46. PULSE_THSY Description THSY4, THSY0 Pulse Threshold on Y-axis. Default value: 0_0000. Table 47. PULSE_THSZ Description THSZ4, THSZ0 Pulse Threshold on Z-axis. Default value: 0_0000. Table 48. Time Step for PULSE Time Limit at ODR and Power Mode

are ignored. Note: This timer must be set for single pulse and for double pulse. of the double pulse need not finish within the time specified by the PULSE_WIND register.

6.7 Auto-Sleep Registers

For additional information on how to configure the device for the Auto-Sleep/Wake feature, refer to AN3921. specified in the DR[2:0] to ASLP_RATE (Reg 0x38) value provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register. Table 49. Time Step for PULSE Latency at ODR and Power Mode Table 50. Time Step for PULSE Detection Window at ODR and Power Mode Table 51. ASLP_COUNT Description

38 Freescale Semiconductor, Inc. value depend on the ODR chosen (see Table 52). new sample data at the current ODR. See Register 0x3A for the wake from sleep bits. and vice versa generates an interrupt. functional blocks are overwritten by the data rate set by the ASLP_RATE field in Register 0x38. DR[2:0] bits select the output data rate (ODR) for acceleration samples. The default value is 000 for a data rate of 400 Hz. Table 52. ASLP_COUNT Relationship with ODR Table 53. CTRL_REG1 Description ASLP_RATE [1:0] This register configures the Auto-Wake sample frequency when the device is in Sleep Mode. See Table 54 for more information. Table 54. Sleep Mode Poll Rate Description Table 55. System Output Data Rate Selection

FS[1:0] bits select between standby mode and active mode. The default value is 00 for standby mode. and Table 3) thus allowing host application to check the functionality of the entire signal chain. BOOT bit is used to activate the software reset. The Boot mechanism can be enabled in STANDBY and ACTIVE mode. registers with default NVM values. Note: The I2C communication system is reset to avoid accidental corrupted data access. Table 56. Full Scale Selection Table 57. CTRL_REG2 Description ST Self-Test Enable. Default value: 0. BOOT Reboot device content (Software Reset). Default value: 0. 0: device reboot disabled; 1: device reboot enabled.

  1. When SLPE = 1, the transitioning between sleep mode and wake mode results in a FIFO flush and a reset of internal functional block counters. All functional block

status information are preserve except otherwise stated. See Table 58 for more information about the FIFO_GATE bit in CTRL_REG3 register. Auto-Sleep enable. Default value: 0. MODS Low power mode / Normal mode selection. Default value: 0. 0: normal mode; 1: low power mode.

40 Freescale Semiconductor, Inc. IPOL bit selects the polarity of the interrupt signal. When IPOL is ‘0’ any interrupt event will signalled with a logical 0. connecting multiple interrupt signals on the same interrupt line. Table 58. CTRL_REG3 Description buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application. Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register. IPOL Interrupt polarity active high, or active low. Default value 0. PP_OD Push-pull/Open Drain selection on interrupt pad. Default value 0. Table 59. interrupt Enable Register Description INT_EN_ASLP Interrupt Enable. Default value: 0. 0: Auto-Sleep/Wake interrupt disabled; 1: Auto-Sleep/Wake interrupt enabled. INT_EN_FIFO Interrupt Enable. Default value: 0. 0: FIFO interrupt disabled; 1: FIFO interrupt enabled. INT_EN_TRANS Interrupt Enable. Default value: 0. 0: Transient interrupt disabled; 1: Transient interrupt enabled. Interrupt Enable. Default value: 0. 0: Orientation (Landscape/Portrait) interrupt disabled. 1: Orientation (Landscape/Portrait) interrupt enabled. INT_EN_PULSE Interrupt Enable. Default value: 0. INT_EN_FF_MT_1 Interrupt Enable. Default value: 0. INT_EN_FF_MT_2 Interrupt Enable. Default value: 0. INT_EN_DRDY Interrupt Enable. Default value: 0.

system’s interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin.

6.8 User Offset Co rrection Registers

Table 60. Interrupt Configuration Register Description INT_CFG_ASLP INT1/INT2 Configuration. Default value: 0. INT_CFG_FIFO INT1/INT2 Configuration. Default value: 0. INT_CFG_TRANS INT1/INT2 Configuration. Default value: 0. INT_CFG_LNDPRT INT1/INT2 Configuration. Default value: 0. INT_CFG_PULSE INT1/INT2 Configuration. Default value: 0. INT_CFG_FF_MT_1 INT1/INT2 Configuration. Default value: 0. INT_CFG_FF_MT_2 INT1/INT2 Configuration. Default value: 0. INT_CFG_DRDY INT1/INT2 Configuration. Default value: 0. Table 61. OFF_X Description D7-D0 X -axis offset trim LSB value. Default value: 0000_0000. Table 62. OFF_Y Description D7-D0 Y-axis offset trim LSB value. Default value: 0000_0000. Table 63. OFF_Z Description D7-D0 Z-axis offset trim LSB value. Default value: 0000_0000.

42 Freescale Semiconductor, Inc. Table 64. MMA8450Q Register Map

00 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR

01 OUT_X_MSB 8-bit X Data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4

02 OUT_Y_MSB 8-bit Y Data R YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4

03 OUT_Z_MSB 8-bit Z Data R ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4

04 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR

05 OUT_X_LSB 12-bit X Data R 0 0 0 0 XD3 XD2 XD1 XD0

06 OUT_X_MSB 12-bit X Data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4

07 OUT_Y_LSB 12-bit Y Data R 0 0 0 0 YD3 YD2 YD1 YD0

08 OUT_Y_MSB 12-bit Y Data R YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4

09 OUT_Z_LSB 12-bit Z Data R 0 0 0 0 ZD3 ZD2 ZD1 ZD0

10 F_STATUS FIFO Status R F_OVF F_WMRK_FLA G F_CNT5 F_CNT4 F_CNT3 F_CNT2 F_CNT1 F_CNT0

11 F_8DATA 8-bit FIFO Data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4

12 F_12DATA 12-bit FIFO Data R 0 0 0 0 XD3 XD2 XD1 XD0

13 F_SETUP FIFO Setup R/W F_MODE1 F_MODE0 F_WMRK5 F_WMRK4 F_WMRK3 F_WMRK2 F_WMRK1 F_WMRK0

14 SYSMOD System Mode R PERR FGERR 0 0 0 0 SYSMOD1 SYSMOD0

17 HP_FILTER_CUTOFF HP Filter Setting R/W 0 0 0 0 0 0 SEL1 SEL0

18 PL_STATUS PL Status R NEWLP LO - LAPO[2] LAPO[1] LAPO[0] BAFRO[1] BAFRO[0]

19 PL_PRE_STATUS Previous PL Status R - LO - LAPO[2] LAPO[1] LAPO[0] BAFRO[1] BAFRO[0]

20 PL_L_P_THS_REG1 Landscape-to-Portrait

21 PL_L_P_THS_REG2 Landscape-to-Portrait

22 PL_L_P_THS_REG3 Landscape-to-Portrait

23 FF_MT_CFG_1 FF/Motion Config.

1 R/W ELE OAE ZHEFE ZLEFE YHEFE YLEFE XHEFE XLEFE

24 FF_MT_SRC_1 FF/Motion Source 1 R — EA ZHE ZLE YHE YLE XHE XLE

25 FF_MT_THS_1 FF/Motion Threshold 1 R/W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0

26 FF_MT_COUNT_1 FF/Motion Debounce 1 R/W D7 D6 D5 D4 D3 D2 D1 D0

28 FF_MT_SRC_2 FF/Motion Source 2 R — EA ZHE ZLE YHE YLE XHE XLE

29 FF_MT_THS_2 FF/Motion Threshold 2 R/W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0

30 PULSE_SRC Pulse Source R — EA ZDPE ZSPE YDPE YSPE XDPE XSPE

31 PULSE_THSX Pulse X Threshold R/W 0 0 0 THSX4 THSX3 THSX2 THSX1 THSX0

32 PULSE_THSY Pulse Y Threshold R/W 0 0 0 THSY4 THSY3 THSY2 THSY1 THSY0

33 PULSE_THSZ Pulse Z Threshold R/W 0 0 0 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0

34 PULSE_TMLT Pulse First Timer R/W Tmlt7 Tmlt6 Tmlt5 Tmlt4 Tmlt3 Tmlt2 Tmlt1 Tmlt0

35 PULSE_LTCY Pulse Latency R/W Ltcy7 Ltcy6 Ltcy5 Ltcy4 Ltcy3 Ltcy2 Ltcy1 Ltcy0

36 PULSE_WIND Pulse 2nd Window R/W Wind7 Wind6 Wind5 Wind4 Wind3 Wind2 Wind1 Wind0

37 ASLP_COUNT Auto-Sleep Counter R/W D7 D6 D5 D4 D3 D2 D1 D0

38 CTRL_REG1 Control Reg 1 R/W ASLP_RATE1 ASLP_RATE0 0 DR2 DR1 DR0 FS1 FS0

39 CTRL_REG2 Control Reg 2 R/W ST RST 0 0 0 0 SLPE MODS

44 Freescale Semiconductor, Inc. Table 65. Accelerometer Output Data

Figure 13. Distribution of Pre Board Mounted Devices Tested in Sockets (1 count = 3.9 mg)

46 Freescale Semiconductor, Inc. Figure 14. Distribution of Post Board Mounted Devices (1 count = 3.9 mg)

Figure 15. 2g/4g/8g X-axis TCS (%/°C)

48 Freescale Semiconductor, Inc. Figure 16. 2g/4g/8g Y-axis TCS (%/°C)

Figure 17. 2g/4g/8g Z-axis TCS (%/°C)

50 Freescale Semiconductor, Inc. Figure 18. 2g/4g/8g X-axis TCO (mg/°C)

Figure 19. 2g/4g/8g Y-axis TCO (mg/°C)

52 Freescale Semiconductor, Inc. Figure 20. 2g/4g/8g Z-axis TCO (mg/°C)

Freescale Semiconductor, Inc. 53 PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN

54 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN

Freescale Semiconductor, Inc. 55 PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN

56 Freescale Semiconductor, Inc.

Revision History

Date Description of Changes 9 02/01/2012 • Corrected Pin Diagram: Pin 8, callout from NC to EN. 9.1 04/13/2012  Page 39, Corrected register name fr om 0x3C: CTRL_REG5 register to 0x3B: CTRL_REG4.  Updated case outline drawing from 2077-01, Issue 0 to 2077-02, Issue A.

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