MMA7456L FREESCALE | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 2 Freescale Semiconductor
Features
- Digital Output (I 2C/SPI)
- 3mm x 5mm x 1mm LGA-14 Package
- Self-Test for Z-Axis
- Low Voltage Operation: 2.4 V – 3.6 V
- User Assigned Registers for Offset Calibration
- Programmable Threshold Interrupt Output
- Level Detection for Motion Recogn ition (Shock, Vibration, Freefall)
- Pulse Detection for Single or Double Pulse Recognition
- Sensitivity (64 LSB/g @ 2g and @ 8g in 10-Bit Mode)
- Selectable Sensitivity (±2g, ±4g, ±8g) for 8-bit Mode
- Robust Design, High Shocks Survivability (5,000g)
- RoHS Compliant
- Environmentally Preferred Product
- Low Cost Typical Applications
- Cell Phone/PMP/PDA: Image Stability, Te xt Scroll, Motion Dialing, Tap to Mute
- HDD: Freefall Detection
- Laptop PC: Freefall Detection, Anti-Theft
- Pedometer
- Motion Sensing, Event Recorder
ORDERING INFORMATION
Part Number Temperature Range Package Shipping MMA7456LT –40 to +85°C LGA-14 Tray MMA7456LR1 –40 to +85°C LGA-14 7” Tape & Reel MMA7456LR2 –40 to +85°C LGA-14 13” Tape & Reel MMA7456L MMA7456L: XYZ-AXIS ACCELEROMETER ±2g/±4g/±8g
14 LEAD
Figure 1. Pin Connections
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Table 1. Pin Descriptions <$1C=0001 1100> bit 0 is GND on pin 4. If the pin is programmed it cannot be left NC. Figure 2. Simplified Accelerometer Functional Block Diagram
1 DVDD_IO Digital Power for I/O pads Input
2 GND Ground Input
4 IADDR0 I2C Address Bit 0 (optional)* Input
5 GND Ground Input
6 AVDD Analog Power Input
8 INT1/DRDY Interrupt 1/ Data Ready Output
9 INT2 Interrupt 2 Output
12 SDO SPI Serial Data Output Output
13 SDA/SDI/SDO I
14 SCL/SPC I2C Serial Clock (SCL), SPI Serial Clock (SPC) Input
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WARNING: This device is sensitive to electrostatic discharge. user to protect the chip from ESD. A charge of over 2000 volts can accumulate on the human body or associated test equipment. precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance. Table 2. Maximum Ratings
Table 3. Operating Characteristics Unless otherwise noted: –40°C < TA < 85°C, 2.4 V < AVDD < 3.6 V, Acceleration = 0g, Loaded output. Output Data Rate is 125 Hz when 62.5 bandwidth is selected. Output Data rate is 250 Hz when 125Hz bandwidth is selected.
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Note: The response time is between 10% of full scale VDD input voltage and 90% of the final operating output voltage. *The bandwidth for detecting interrupts in level and pulse is 600Hz which is changed from measurement mode. PRINCIPLE OF OPERATION The Freescale accelerometer is a surface-micromachined integrated-circuit accelerometer. The device consists of a surface mi- cromachined capacitive sensing cell (g-cell) and a signal conditioning ASIC contained in a single package. The sensing element is sealed hermetically at the wafer level using a bulk micromachined cap wafer. The g-cell is a mechanical structure formed from semiconductor materials (polysilicon) using semiconductor processes (masking and etching). It can be modeled as a set of beams attached to a movable central mass that move between fixed beams. The movable beams can be deflected from their rest position by subjecting the system to an acceleration (Figure 3). As the beams attached to the central mass move, the distance from them to the fixed beams on one side will increase by the same amount that the distance to the fixed beams on the other side decreases. The change in distance is a measure of accel- eration. The g-cell beams form two back-to-back capacitors (Figure 3). As the center beam moves with acceleration, the distance between the beams changes and each capacitor's value will change, (C = Aε/D). Where A is the area of the beam, ε is the di- electric constant, and D is the distance between the beams. The ASIC uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the differ- ence between the two capacitors. The ASIC also signal conditions and filters (switched capacitor) the signal, providing a digital output that is proportional to acceleration. Figure 3. Simplified Transducer Physical Model The sensor provides a self-test feature that allows the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. This feature is critical in applications such as hard disk drive protection where system in- tegrity must be ensured over the life of the product. When the self-test function is initiated through the mode control register ($16), accessing the “self-test” bit, an electrostatic force is applied to each axis to cause it to deflect. The Z-axis is trimmed to deflect 1g. This procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. Table 4. Function Parameters for Detection
located in the mode control register. is controlled through the mode control register by accessing the two mode bits as shown in Table 6. (signaled by the DRDY flag), the next measurement will be ready. where X or Y or Z > Threshold vs. doing a detection for freefall where X & Y & Z < Threshold. Table 5. Configuring the g-Select for 8-bit output using Register $16 with GLVL[1:0] bits. Table 6. Configuring the Mode using Register $16 with MODE[1:0] bits.
00 Standby Mode
01 Measurement Mode
10 Level Detection Mode
11 Pulse Detection Mode
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When in Level or Pulse detection mode, it is not advisable to read the XYZ measurements because this can conflict with timing. The interrupts for level and pulse detection are at 600 Hz, while measurement mode is at 125 Hz. It is best to exit the pulse/level mode before taking a measurement on the XYZ. Both the Level Detection and Pulse Detection modes can trigger an interrupt. Typically one interrupt is assigned to either pulse detection or level detection. To detect both at the same time 2 interrupts are required. The level detection mechanism has no timers associated with it. Once a set acceleration level is reached the interrupt pin will go high and remain high until the interrupt pin is cleared (See Assigning, Clearing & Detecting Interrupts). By default all three axes are enabled and the detection range is 8g only. X and/or Y and/or Z can be disabled. There is a choice between detecting an Absolute signal or a Positive or Negative only signal on the enabled axes. There is also a choice between doing a detection for Motion where X or Y or Z > Threshold vs. doing a detection for Freefall where X& Y & Z < Threshold. $18: Control 1 (Read/Write) Setting the Detection Axes for X, Y and Z This allows the user to define how many axes to use for detection. All axes are enabled by default. To disable write 1. XDA: Disable X YDA: Disable Y ZDA: Disable Z $19: Control 2 (Read/Write) Motion Detection (OR Condition) or Freefall Detection (AND Condition LDPL = 0: Level detection polarity is positive and detecting condition is OR for all 3 axes. X or Y or Z > Threshold LDPL = 1: Level detection polarity is negative detecting condition is AND for all 3 axes. X and Y and Z < Threshold $18: Control 1 (Read/Write): Setting the threshold to be an integer value or an absolute value This allows the user to set the threshold to be absolute, or to be based on the threshold value as positive or negative. THOPT = 0 Absolute; THOPT = 1 Positive Negative $1A: Level Detection Threshold Limit Value (Read/Write) When an event is detected the interrupt pin (either INT1 or INT2) will go high. The interrupt pin assignment is set up in Register $18, discussed in the Assigning, Clearing & Detecting Interrupts section. The detection status is monitored by the Detection Source Register $0A. LDTH[7:0]: Level detection threshold value. If THOPT bit in Detection Control Register is “0”, it is unsigned 7 bits value and LDTH[7] should be “0”. If THOPT bit is “1”, it is signed 8 bits value. D7 D6 D5 D4 D3 D2 D1 D0 Reg $18 DFBW THOPT ZDA YDA XDA INTREG[1] INTREG[0] INTPIN Function
00000000 D e f a u l t
D7 D6 D5 D4 D3 D2 D1 D0 Reg $19 -- -- -- -- -- DRVO PDPL LDPL Function D7 D6 D5 D4 D3 D2 D1 D0 Reg $18 DFBW THOPT ZDA YDA XDA INTREG[1] INTREG[0] INTPIN Function D7 D6 D5 D4 D3 D2 D1 D0 Reg $1A LDTH[7] LDTH[6] LDTH[5] LDTH[4] LDTH[3] LDTH[2] LDTH[1] LDTH[0] Function
Freescale Semiconductor 11 MMA7456L THRESHOLD DETECTION FOR MOTION AND FREEFALL CONDITIONS CASE 1: Motion Detection Integer Value: X >Threshold OR Y >Threshold OR Z > Threshold Reg $18 THOPT=1; Reg 19 LDPL=0, Set Threshold to 3g, which is 47 counts (16 counts/g). Set register $1A LDTH = $2F. CASE 2: Motion Detection Reg $18 THOPT=0; Reg 19 LDPL=0, Set Threshold to 3g, which is 47 counts (16 counts/g). Set register $1A LDTH = $2F. CASE 3: Freefall Detection Integer Value: X < Threshold AND Y < Threshold AND Z <Threshold Reg $18 THOPT=1; Reg 19 LDPL=1, Set Threshold to 0.5g, which is 7 counts (16 counts/g). Set register $1A LDTH = $07 CASE 4: Freefall Detection Reg $18 THOPT=0; Reg 19 LDPL=1, Set Threshold to +/-0.5g, which is 7 counts (16 counts/g). Set register $1A LDTH = $07. TH = $2F TH = $2F TH = $D1 TH = $07 TH = $07 TH = $F9
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There are two interrupt pins available for detection of level and pulse conditions. The pulse detection has several timing windows associated with it. A single pulse and a double pulse can be detected. Also freefall can be detected. The interrupt pins can be assigned to detect the first pulse on one interrupt and the second pulse on the other interrupt. This is explained on Page page 15, under the Assigning, Clearing & Detecting Interrupts section. By default all three axes are enabled and the detection range is 8g only. X and/or Y and/or Z can be disabled. There is a choice between doing a detection for Motion detection vs. doing a detection for Freefall. $18: Control 1 (Read/Write): Disable X, Y or Z for pulse detection This allows the user to define how many axes to use for detection. All axes are enabled by default. To disable write 1 XDA: Disable X YDA: Disable Y ZDA: Disable Z. $19: Control 2 (Read/Write): Motion Detection (OR condition) or Freefall Detection (AND condition) PDPL 0: Pulse detection polarity is positive and detecting condition is OR 3 axes. 1: Pulse detection polarity is negative and detecting condition is AND 3 axes. CASE 1: Single Pulse Motion Detection: X or Y or Z > Pulse Threshold for Time < Pulse Duration For motion detection with single pulse the device must be in pulse mode. PDPL in Register $19 =0 for “OR” motion condition. The Pulse threshold must be set in Register $1B and the pulse duration time window must also be set using Register $1C. The pulse must be detected before the time window closes for the interrupt to trigger. D7 D6 D5 D4 D3 D2 D1 D0 Reg $18 DFBW THOPT ZDA YDA XDA INTREG[1] INTREG[0] INTPIN Function D7 D6 D5 D4 D3 D2 D1 D0 Reg $19 -- -- -- -- -- DRVO PDPL LDPL Function $1B: Pulse Detection Threshold Limit Value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reg $1B PDTH[7] PDTH[6] PDTH[5] PDTH[4] PDTH[3] PDTH[2] PDTH[1] PDTH[0] Function $1C: Pulse Duration Value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Reg $1C PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0] Function
00000001 D e f a u l t
Figure 4. Single Pulse Detection threshold longer than the time window for the interrupt to trigger. Figure 5. Freefall Detection in Pulse Mode
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For motion detection with double pulse the device must be in pulse mode. PDPL in Register $19 =0 for “OR” motion condition. The Pulse Threshold must be set in Register $1B and the Pulse Duration Time Window must also be set using Register $1C. monitored by the detection source register $0A. Figure 6. Double Pulse Detection
outlined below in the table for INTREG[1:0]. Table 7. Configuring the Interrupt settings using Register $18 with INTREG[1:0] bits 01: INT1 Register is detecting Pulse while INT2 is detecting Level. time window and second time window>0 then INT2 will detect the double pulse only. clears both INT1 and INT2 register bits and resets the detection operation. Follow the example given for clearing the interrupts. interrupt pin should be enabled to trigger the next detection by setting it to a logic 0.
00 Level detection Pulse Detection
01 Pulse Detection Level Detection
10 Single Pulse detection Single or Double Pulse Detection
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1: Level detection event is detected on X-axis 0: Level detection event is not detected on X-axis LDY 1: Level detection event is detected on Y-axis 0: Level detection event is not detected on Y-axis LDZ 1: Level detection event is detected on Z-axis 0: Level detection event is not detected on Z-axis PDX 1: 1st pulse is detected on X-axis 0: 1st pulse is detected on X-axis PDY 1: 1st pulse is detected on Y-axis 0: 1st pulse is detected on Y-axis PDZ 1: 1st pulse is detected on Z-axis 0: 1st pulse is detected on Z-axis INT1 1: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is detected 0: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is not detected INT2 1: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is detected 0: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is not detected DIGITAL INTERFACE The MMA7456L has both an I2C and SPI digital output available for a communication interface. CS pin is used for selecting the mode of communication. When CS is low, SPI communication is selected. When CS is high, I2C communication is selected. Note: It is recommended to disable I2C during SPI communication to avoid communication errors between devices using a dif- ferent SPI communication protocol. To disable I2C, set the I2CDIS bit in I2C Device Address register using SPI. I2C Slave Interface I2C is a synchronous serial communication between a master device and one or more slave devices. The master is typically a microcontroller, which provides the serial clock signal and addresses the slave device(s) on the bus. The MMA7456L communi- cates only in slave operation where the device address is $1D. Multiple read and write modes are available. The protocol supports slave only operation. It does not support Hs mode, “10-bit addressing”, “general call” and: ”START byte”. SINGLE BYTE READ The MMA7456L has an 10-bit ADC that can sample, convert and return sensor data on request. The transmission of an 8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send the command, note that the data re- turned is sent with the MSB first once the data is received. Figure 7 shows the timing diagram for the accelerometer 8-bit I2C read operation. The Master (or MCU) transmits a start condition (ST) to the MMA7456L, slave address ($1D), with the R/W bit set to “0” for a write, and the MMA7456L sends an acknowledgement. Then the Master (or MCU) transmits the 10-bit address of the register to read and the MMA7456L sends an acknowledgement. The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA7456L ($1D) with the R/W bit set to “1” for a read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NAK) it re- ceived the transmitted data, but transmits a stop condition to end the data transfer. MULTIPLE BYTES READ The MMA7456L automatically increments the received register address commands after a read command is received. Therefore, after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA7456L acknowledgment (AK) is received until a NACK is received from the Master followed by a stop condition (SP) signalling an end of transmission. See Figure 8. $0A: Detection Source Register (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Reg $0A LDX LDY LDZ PDX PDY PDZ INT2 INT1 Function
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an example of how to configure one master with one MMA745xL device. The MMA7456L is always operated as a slave device. Typically, the master device would be a microcontroller which would drive the clock (SPC) and chip select (CS) signals. should be captured at the rising edge of the SPC. Read and write register commands are completed in 16 clock pulses or in multiples of 8, in the case of a multiple byte read/write. timing diagram for an 8-bit read in 4 wire and 3 wire modes, respectively. of an MSB (0=read, 1=write) to indicate writing to the MMA7456L register, followed by a 6-bit address and 1 don’t care bit. The command should then be followed the 8-bit data transfer. See Figure 12 for the timing diagram for an 8-bit data write. Figure 11. SPI Timing Diagram for 8-Bit Register Read (4 Wire Mode) Figure 12. SPI Timing Diagram for 8-Bit Register Read (3 Wire Mode) Figure 13. SPI timing Diagram for 8-Bit Register Write (3 Wire Mode)
Figure 14. Pinout Description Table 8. Pin Descriptions Figure 15. I2C Connection to MCU unconnected or connect to Ground.
4 IADDR0 I
unconnected or connect to Ground. unconnected or connect to Ground.
14 SCL/SPC I2C Serial Clock (SCL), SPI Serial
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Figure 16. SPI Connection to MCU
- Use a 0.1 μF and a 10 μF capacitor on AVDD to and DVDD_IO to decouple the power source.
- Physical coupling distance of the accelerometer to the microcontroller should be minimal.
- PCB layout of power and ground should not couple power supply noise.
- Accelerometer and microcontroller should not be a high current path.
- Any external power supply switching frequency should be sele cted such that they do not interfere with the internal
accelerometer sampling frequency (sampling frequency). This will prevent aliasing errors.
- Physical distance of the two GND pins (Pin2 and Pin5 ) tied together should be at the shortest distance.
Reading low byte XOUTL latches high byte XOUTH to allow 10-bit reads. XOUTH should be read directly following XOUTL read. Table 9. User Register Summary
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Signed byte data (2’s compliment): 0g = 10’h000 Reading low byte XOUTL latches high byte XOUTH to allow 10-bit reads. XOUTH should be read directly following XOUTL read. Signed byte data (2’s compliment): 0g = 10’h000 Reading low byte YOUTL latches high byte YOUTH to allow coherent 10-bit reads. YOUTH should be read directly following YOUTL. Signed byte data (2’s compliment): 0g = 10’h000 Reading low byte ZOUTL latches high byte ZOUTH to allow coherent 10-bit reads. ZOUTH should be read directly following ZOUTL. Signed byte data (2’s compliment): 0g = 10’h000 Reading low byte ZOUTL latches high byte ZOUTH to allow coherent 10-bit reads. ZOUTH should be read directly following ZOUTL. Signed byte data (2’s compliment): 0g = 8’h00 Signed byte data (2’s compliment): 0g = 8’h00 $01: 10bits Output Value X MSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- -- XOUT [9] XOUT[8] Function 0 0 0 0 0 0 0 0 Default $02: 10bits Output Value Y LSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit YOUT [7] YOUT [6] YOUT [5] YOUT [4] YOUT [3] YOUT [2] YOUT [1] YOUT[0] Function 0 0 0 0 0 0 0 0 Default $03: 10bits Output Value Y MSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- -- YOUT [9] YOUT[8] Function 0 0 0 0 0 0 0 0 Default $04: 10bits Output Value Z LSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit ZOUT [7] ZOUT [6] ZOUT [5] ZOUT [4] ZOUT [3] ZOUT [2] ZOUT [1] ZOUT[0] Function 0 0 0 0 0 0 0 0 Default $05: 10bits Output Value X MSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- -- ZOUT [9] ZOUT[8] Function 0 0 0 0 0 0 0 0 Default $06: 8bits Output Value X (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit XOUT[7] XOUT [6] XOUT [5] XOUT [4] XOUT [3] XOUT [2] XOUT [1] XOUT [0] Function 0 0 0 0 0 0 0 0 Default $07: 8bits Output Value Y (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit YOUT[7] YOUT [6] YOUT [5] YOUT [4] YOUT [3] YOUT [2] YOUT [1] YOUT [0] Function 0 0 0 0 0 0 0 0 Default
Freescale Semiconductor 23 MMA7456L Signed byte data (2’s compliment): 0g = 8’h00 DRDY 1: Data is ready 0: Data is not ready DOVR 1: Data is over written 0: Data is not over written PERR 1: Parity error is detected in trim data. Then, self-test is dis- abled 0: Parity error is not detected in trim data LDX 1: Level detection detected on X-axis 0: Level detection not detected on X-axis LDY 1: Level detection detected on Y-axis 0: Level detection not detected on Y-axis LDZ 1: Level detection detected on Z-axis 0: Level detection not detected on Z-axis PDX *Note 1: Pulse is detected on X-axis at single pulse detection 0: Pulse is not detected on X-axis at single pulse detection PDY *Note 1: Pulse is detected on Y-axis at single pulse detection 0: Pulse is not detected on Y-axis at single pulse detection PDZ *Note 1: Pulse is detected on Z-axis at single pulse detection 0: Pulse is not detected on Z-axis at single pulse detection Note: This bit value is not valid at double pulse detection INT1 1: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is detected 0: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is not detected INT2 1: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is detected 0: Interrupt assigned by INTRG[1:0] bits in Control 1 Register ($18) and is not detected *Note: Must define DRDY to be an output to either INT1 or not. This is done through bit DRPD located in Register $16. $08: 8bits Output Value Z (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit ZOUT[7] ZOUT [6] ZOUT [5] ZOUT [4] ZOUT [3] ZOUT [2] ZOUT [1] ZOUT [0] Function 0 0 0 0 0 0 0 0 Default $09: Status Register (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- PERR DOVR DRDY Function 0 0 0 0 0 0 0 0 Default $0A: Detection Source Register (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit LDX LDY LDZ PDX PDY PDZ INT2 INT1 Function 0 0 0 0 0 0 0 0 Default
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0: I2C and SPI are available. 1: I2C is disabled. DVAD[6:0]: I2C device address UI2[7:0]: User information Signed byte data (2’s compliment): User level offset trim value for X-axis *Bit weight is for 8g 10bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. Signed byte data (2’s compliment): User level offset trim value for X-axis Signed byte data (2’s compliment): User level offset trim value for Y-axis *Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. $0D: I2C Device Address (Bit 6-0: Read only, Bit 7: Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit I2CDIS DVAD[6] DVAD[5] DVAD[4] DVAD[3] DVAD[2] DVAD[1] DVAD[0] Function 0 0 0 1 1 1 0 1 Default $0E: User Information (Read Only: Optional) D7 D6 D5 D4 D3 D2 D1 D0 Bit UI[7] UI[6] UI[5] UI[4] UI[3] UI[2] UI[1] UI[0] Function 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP Default $0F: “Who Am I” Value (Read only: Optional) D7 D6 D5 D4 D3 D2 D1 D0 Bit ID[7] ID [6] ID [5] ID [4] ID [3] ID [2] ID [1] ID [0] Function 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP Default $10: Offset Drift X LSB (Read/Write) The following Offset Drift Registers are used for setting and storing the offset calibrations to eliminate the 0g offset. Please refer to Freescale application note AN3745 for detailed instructions on the process to set and store the calibration values. D7 D6 D5 D4 D3 D2 D1 D0 Bit XOFF[7] XOFF [6] XOFF [5] XOFF [4] XOFF [3] XOFF [2] XOFF [1] XOFF [0] Function 0 0 0 0 0 0 0 0 Default Bit XOFF[7] XOFF[6] XOFF[5] XOFF[4] XOFF[3] XOFF[2] XOFF[1] XOFF[0] Weight* 64 LSB 32 LSB 16 LSB 8 LSB 4 LSB 2 LSB 1 LSB 0.5 LSB $11: Offset Drift X MSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- XOFF [10] XOFF [9] XOFF [8] Function 0 0 0 0 0 0 0 0 Default $12: Offset Drift Y LSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit YOFF[7] YOFF [6] YOFF [5] YOFF [4] YOFF [3] YOFF [2] YOFF [1] YOFF [0] Function 0 0 0 0 0 0 0 0 Default Bit YOFF[7] YOFF[6] YOFF[5] YOFF[4] YOFF[3] YOFF[2] YOFF[1] YOFF[0] Weight* 64 LSB 32 LSB 16 LSB 8 LSB 4 LSB 2 LSB 1 LSB 0.5 LSB
*Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. *Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. *Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. Table 10. Configuring the g-Select for 8-bit output using Register $16 with GLVL[1:0] bits. 00: 8g is selected for measurement range. 10: 4g is selected for measurement range. 01: 2g is selected for measurement range.
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Control1($18) INTREG[1:0] setting. Control1($18) INTREG[1:0] setting. 0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A). 01: INT1 Register is detecting Pulse while INT2 is detecting Level. time window and second time window>0 then INT2 will detect the double pulse only. clears both INT1 and INT2 register bits and resets the detection operation. 1: X-axis is disabled for detection. 0: X-axis is enabled for detection. 1: Y-axis is disabled for detection. 0: Y-axis is enabled for detection. 1: Z-axis is disabled for detection. 0: Z-axis is enabled for detection. 1: Integer value is available. Table 11. Configuring the Interrupt settings using Register $18 with INTREG[1:0] bits
Freescale Semiconductor 27 MMA7456L DRVO 0: Standard drive strength on SDA/SDO pin 1: Strong drive strength on SDA/SDO pin LDTH[7:0]: Level detection threshold value. If THOPT bit in Detection Control Register is “0”, it is unsigned 7 bits value and LDTH[7] should be “0”. If THOPT bit is “1”, it is signed 8 bits value. PDTH[6:0]: Pulse detection threshold value (unsigned 7 bits). XPDTH: This bit should be “0”. Min: PD[7:0] = 4’h01 = 0.5 ms Max: PD[7:0] = 4’hFF = 127 ms 1 LSB = 0.5 ms Min: LT[7:0] = 8’h01 = 1 ms Max: LT[7:0] = 8’hFF = 255 ms
1 LSB = 1 ms
Min: TW[7:0] = 8’h01 = 1 ms (Single pulse detection) Max: TW[7:0] = 8’hFF = 255 ms $1A: Level Detection Threshold Limit Value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit LDTH[7] LDTH[6] LDTH[5] LDTH[4] LDTH[3] LDTH[2] LDTH[1] LDTH[0] Function 0 0 0 0 0 0 0 0 Default $1B: Pulse Detection Threshold Limit Value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit XPDTH PDTH[6] PDTH[5] PDTH[4] PDTH[3] PDTH[2] PDTH[1] PDTH[0] Function 0 0 0 0 0 0 0 0 Default $1C: Pulse Duration Value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0] Function 0 0 0 0 0 0 0 0 Default $1D: Latency Time Value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit LT[7] LT[6] LT[5] LT[4] LT[3] LT[2] LT[1] LT[0] Function 0 0 0 0 0 0 0 0 Default $1E: Time Window for 2nd Pulse Value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit TW[7] TW[6] TW[5] TW[4] TW[3] TW[2] TW[1] TW[0] Function 0 0 0 0 0 0 0 0 Default
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The following figure shows sensing direction and the output response for 2g mode. Figure 17. Sensing Direction and Output Response at 2g Mode Table 12. Acceleration vs. Output (8-bit data)
- When positioned as shown, the Earth’s gravity will result in a positive 1g output.
correct size to ensure proper solder connection interface between the board and the package. design boards with a solder mask layer to avoid bridging and shorting between solder pads. sumer applications. Figure 18 shows the recommended PCB land pattern for the package. Figure 18. Recommended PCB Land Pattern for the 5 x 3 mm LGA Package
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designs the package will self-align during the solder reflow process. The following are the recommended guidelines to follow for mounting LGA sensors for consumer applications.
- The PCB land should be designed with Non Solder Mask Defined (NSMD) as shown in Figure 21.
- No additional metal pattern underneath package as shown in Figure 20.
- The solder mask opening is equal to the size of the PCB land pad plus an extra 0.1 mm as shown in Figure 21.
- The stencil aperture size is e qual to the PCB land pad – 0.025mm.
Figure 19. Incorrect PCB Top Metal Pattern Under Figure 20. Correct PCB Top Metal Pattern Under Package Figure 21. Recommended PCB Land Pad, Solder Mask, and Signal Trace Near Package Design
Figure 22. Stencil Design Guidelines
- Do not place any components or vias at a distance less than 2 mm from the package land area. This may cause additional
package stress if it is too close to the package land area.
- Signal traces connected to pads should be as symmetric as possible. Put dummy traces on NC pads in order to have same
package are recommended as shown in Figure 21 and Figure 22. Wider trace can be continued after the 0.5 mm zone.
- Use a standard pick and place process and equi pment. Do not us a hand soldering process.
- It is recommended to use a cleanable solder paste with an additional cleaning step after SMT mount.
- Do not use a screw down or stacking to fix the PCB into an enclosure because this could bend the PCB putting stress on
- The PCB should be rated for the multiple lead-f ree reflow condition with max 260°C temperature.
Please cross reference with the device data sheet for mounting guidelines specific to the exact device used.
32 Freescale Semiconductor
Figure 23. MMA7456L Temperature Coefficient of Offset (TCO) and Figure 24. MMA7456L Current Distribution Charts
Freescale Semiconductor 33 MMA7456L PACKAGE DIMENSIONS CASE 1977-01 ISSUE A 14-LEAD LGA
34 Freescale Semiconductor
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