MMA7455L FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • Digital Output (I 2C/SPI) - 10-Bit at 8g Mode
  • 3mm x 5mm x 1mm LGA-14 Package
  • Low Current Consumption: 400 μA
  • Self Test for Z-Axis
  • Low Voltage Operation: 2.4 V – 3.6 V
  • User Assigned Registers for Offset Calibration
  • Programmable Threshold Interrupt Output
  • Level/Click Detection for Motion Recognition (Shock, Vibration, Freefall)
  • Pulse Detection for Single or Double Pulse Recognition
  • Sensitivity (64 LSB/g @ 2g and @ 8g in 10-Bit Mode)
  • Selectable Sensitivity (±2g, ±4g, ±8g)
  • Robust Design, High Shocks Survivability (10,000 g)
  • RoHS Compliant
  • Environmentally Preferred Product
  • Low Cost Typical Applications
  • Cell Phone/PMP/PDA: Image Stability, Text Scroll, Motion Dialing, E-Compass, Tap to Mute
  • HDD: Freefall Detection
  • Laptop PC: Freefall Detection, Anti-Theft
  • Navigation and Dead Reckoning: Position Detection, Pedometer
  • E-Compass Tilt Compensation
  • 3D Gaming: Tilt and Motion Sensing, Event Recorder

ORDERING INFORMATION

Part Number Temperature Range Package Shipping MMA7455LT –40 to +85°C LGA-14 Tray MMA7455LR1 –40 to +85°C LGA-14 Tape & Reel (7” Reel) MMA7455LR2 –40 to +85°C LGA-14 Tape & Reel (13” Reel) MMA7455L MMA7455L: XYZ AXIS ACCELEROMETER ±2G/±4G/±8G

14 LEAD

Figure 1. Pin Connections

2 Freescale Semiconductor

Figure 2. Simplified Accelerometer Functional Block Diagram

1 DVDD_IO Digital Power for I/O pads Input

2 GND Ground Input

3 N/C No Connection or Connect to Ground Input

4 IADDR0 I

5 GND Ground (optional) Input

6 AVDD Analog Power Input

9 INT2 Interrupt 2 Output

10 N/C Rev 1: No Connection or Ground Input

11 Reserved Ground Input

12 SDO SPI Serial Data Output Output

13 SD(A/I/O) I

14 SCL/SPC I2C Serial Clock (SCL), SPI Serial Clock (SPC) Input

may be detrimental to its performance. Table 1. Maximum Ratings

4 Freescale Semiconductor

Table 2. Operating Characteristics Output Data Rate is 125 Hz when 62.5 bandwidth is selected. Output Data rate is 250 Hz when 125Hz bandwidth is selected.

Note: The response time is between 10% of full scale Vdd input voltage and 90% of the final operating output voltage. Table 3. Function Parameters for Detection Table 2. Operating Characteristics (Continued)

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The Freescale accelerometer is a surface-micromachined integrated-circuit accelerometer. The device consists of a surface micromachined capacitive sensing cell (g-cell) and a signal conditioning ASIC contained in a single package. The sensing element is sealed hermetically at the wafer level using a bulk micromachined cap wafer. The g-cell is a mechanical structure formed from semiconductor materials (polysilicon) using semiconductor processes (masking and etching). It can be modeled as a set of beams attached to a movable central mass that move between fixed beams. The movable beams can be deflected from their rest position by subjecting the system to an acceleration (Figure 3). As the beams attached to the central mass move, the distance from them to the fixed beams on one side will increase by the same amount that the distance to the fixed beams on the other side decreases. The change in distance is a measure of acceleration. The g-cell beams form two back-to-back capacitors (Figure 3). As the center beam moves with acceleration, the distance between the beams changes and each capacitor's value will change, (C = A ε/D). Where A is the area of the beam, ε is the dielectric constant, and D is the distance between the beams. The ASIC uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the difference between the two capacitors. The ASIC also signal conditions and filters (switched capacitor) the signal, providing a high level digital output voltage that is proportional to acceleration. Figure 3. Simplified Transducer Physical Model The sensor provides a self test feature that allows the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. This feature is critical in applications such as hard disk drive protection where system integrity must be ensured over the life of the product. Customers can use self test to verify the solderability to confirm that the part was mounted to the PCB correctly. When the self test function is initiated through the mode control register, accessing the “self test” bit, an electrostatic force is applied to each axis to cause it to deflect. The z-axis is trimmed to deflect 1g. This procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. g-Select The g-Select feature enables the selection between 3 sensitivities for measurement. Depending on the values in the Mode control register ($16), the MMA7455L’s internal gain will be changed allowing it to function with a 2g, 4g or 8g measurement sensitivity. This feature is ideal when a product has applications requiring two or more sensitivities for optimum performance and for enabling multiple functions. The sensitivity can be changed during the operation by modifying the two GLVL bits located in the mode control register. Standby Mode This digital output 3-axis accelerometer provides a standby mode that is ideal for battery operated products. When standby mode is active, the device outputs are turned off, providing significant reduction of operating current. When the device is in standby mode the current will be reduced to 2.5 µA typical. In standby mode the device can read and write to the registers with the I 2C/SPI available, but no new measurements can be taken in this mode as all current consuming parts are off. The mode of the device is controlled through the mode control register by accessing the two mode bits as shown in Table 5. Acceleration $16: Mode control register (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- DRPD SPI3W STON GLVL[1] GLVL[0] MODE[1] MODE[0] Function 0 0 0 0 0 0 0 0 Default Table 4. g-Select Description for 8-Bit Mode Table 5. Mode Descriptions

00 Standby Mode

01 Measurement Mode

10 Level Detection Mode

11 Pulse Detection Mode

During measurement mode, continuous measurements on all three axes enabled. The g-range for 2g, 4g, or 8g are selectable with 8-bit data and the g-range of 8g is selectable with 10-bit data. The sample rate during measurement mode is 125 Hz with 62.5 BW filter selected. The sample rate is 250 Hz with the 125 Hz filter selected. Therefore, when a conversion is complete (signaled by the DRDY flag), the next measurement will be ready. When measurements on all three axes are completed, a logic high level is output to the DRDY pin, indicating “Measurement data is ready.” The DRDY status can be monitored by the DRDY bit in Status Register (Address: $09). The DRDY pin is kept high until one of the three Output Value Registers are read. If the next measurement data is written before the previous data is read, the DOVR bit in the Status Register will be set. Also note that in measurement mode, level detection mode and pulse detection mode are not available. LEVEL DETECTION MODE Level Detection Mode In level detection mode, the measurements for x, y and z are all enabled with 2g/4g and 8g range available.The detection of thresholds for an acceleration signal level for the combinations of one, two or all three axes can be enabled. This is typically used for motion detection where the threshold can be user set depending on the application or user specific requirements. When a motion event is detected, one of the interrupt pins (INT1 or INT2) will output a logic high output signaling the event is detected. Setting for Motion Detection To configure the MMA7455L for motion detection, after all three axes are enabled for detection, set the LDPL bit in Control Register 2 (Address: $19) to 0. When the output value of one of the enabled axes exceeds the threshold limit value, either INT1 or INT2 pin will output a logic High indicating the event was detected. – If LDPL = 0 and all three axes are enabled for detection – When the specified motion condition is dete cted, INT1 or INT2 will output a Logic high –“ X O U T ≥Threshold” or “YOUT ≥Threshold” or “ZOUT ≥Threshold” Threshold limit value is common for all three axes. Positive/negative and absolute value option is available Setting for Freefall Detection LDPL bit in Control Register 2 (Address: $19) should be “1” for freefall detection. When the output values of all enabled axes are below the threshold limit value, logic high level is output to INT1 or INT2 pin and indicates the event was detected. – If LDPL = 1 and all three axes are enabled for detection – When the condition below was detected, Logic high level output to INT1 or INT2 –“ X O U T ≤Threshold" and “YOUT ≤Threshold" and ”ZOUT≤Threshold" – Threshold limit value is common for all three axes. Posi tive/negative and absolute value option is available. – INT1/INT2 pin assignment for level detecti on is controlled by Control Register 1 (Address: $18). Detection status is also able to be monitored by Detection source Register (Address: $0A). Once the event was detected, INT pin or register bit will not be cleared until clear bit in Interrupt Latch Reset Register (Address: $17) is set. For a more detailed description of the Threshold Detect please refer to application note AN3571, “Threshold and Pulse Detect Using the MMA745xL”. $ 1 9 C T L 2 ————— D R V O P D P L L D P L

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Assigning and Clearing the Interrupt Pins INT1/INT2 pin assignment for level detection is controlled by Control Register 1 (Address:$18). Detection status is able to be monitored by Detection Source Register (Address:$0A). Once the configured event is detected, INT pin or register bit will not be cleared until the respective clear bit (CLRINT1 or CLRINT2) in Interrupt Latch Reset Register (Address: $17) is set. CLRINT1 and CLRINT2 should be cleared before starting next detection. Otherwise, INT pin or register will not set. I NOTE: Measurement period and bandwidth for level detection is different from data output rate and the bandwidth of “measurement.” Please refer to Functional Parameter for Detection for more information. PULSE DETECTION MODE Pulse Detection Mode In pulse detection mode, only 8g range is available. It is independent from measurement g-range. Therefore if the measure- ment range is in the 2g or 4g mode, the pulse detection range will still be 8g. Measurements for x, y and z in 2g/4g or 8g mode are enabled. The level detection is also enabled in this mode. The pulse detected by the acceleration signal is enabled with single pulse and double pulse detection allowing the choice of either positive, negative or absolute value pulse detection. Setting for Motion Detection For the PDPL bit in Control Register 2 (Address: $19) the register should be set to “0” for motion detection. When the output value of one of the enabled axes exceeds the threshold limit value, logic high level is output to INT1 or INT2 pin and indicates the event was detected. – If PDPL = 0 and all three axes are enabled for detection – When the condition below was detected, logic high level outputs to INT1 or INT2 –“ X O U T ≥Threshold” or “YOUT ≥Threshold” or “ZOUT ≥Threshold” Setting for Freefall Detection To configure the MMA7455L for freefall detection, set the PDPL bit in Control Register 2 (Address: $19) to 1 and Time Window for 2nd pulse value should be “0” for freefall detection. When the output values of all enabled axes are below the threshold limit continuously during the period specified in Latency Timer Value register, logic high level is output to INT1 or INT2 pin and indi- cates the event was detected. – If PDPL = 1, TW[7:0] = 0 and all three axes are enabled for detection – When the condition below was detected, Logic high level output to INT1 or INT2 –“ X O U T ≤Threshold" and “YOUT ≤Threshold" and ”ZOUT≤Threshold" – INT1/INT2 pin assignment for pulse detection is controlled by Control Register 1 (Address: $18). Detection status is also able to be monitored by Interrupt Source Register. Once the event was detected, INT pin or register bit will not be cleared until clear bit in Interrupt Latch Reset Register (Address: $17) is set. When the output values of all enabled axes are below the threshold limit continuously during the period specified in Latency Timer Value Register, logic high level is output to INT1 or INT2 pin indicating freefall was detected. For a more detailed description of the Threshold Detect please refer to application note AN3571, “Threshold and Pulse Detect Using the MMA745xL”. $18 CTL1 — THOPT ZDA YDA XDA INTRG[1] INTRG[0] INTPIN $ 1 7 I N T R S ————— — ] C L R I N T 2 C L R I N T 1 INTPIN: 0:INT1 will be used for event 1:INT2 will be used for event $ 1 9 C T L 2 ————— D R V O P D P L L D P L $1E TW TW[7] TW[6] TW[5] TW[4] TW[3] TW[2] TW[1] TW[0]

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high, I2C communication is selected and SPI is disabled. by a stop condition (SP) signalling an end of transmission. Master transmits a stop condition (SP) to the data transfer. appropriate register. See Figure 9. Figure 7. Single Byte Read - The Master is reading one address from the MMA7455L Figure 8. Multiple Bytes Read - The Master is reading multiple sequential registers from the MMA7455L Figure 9. Single Byte Write - The Master (MCU) is writing to a single register of the MMA7455L

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Figure 14. Pinout Description Figure 15. I2C Connection to MCU

3 N/C No Connection or Connect to

14 SCL/SPC I

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  1. Use a 1 μF and a 10 μF capacitor on AVDD to and

DVDD_IO to decouple the power source.

  1. Physical coupling distance of the accelerometer to

the microcontroller should be minimal.

  1. Place a ground plane beneath the accelerometer to
  2. PCB layout of power and ground should not couple
  3. Accelerometer and microcontroller should not be a
  4. Any external power supply switching frequency

Table 6. User Register Summary

Freescale Semiconductor 15 MMA7455L REGISTER DEFINITIONS Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte XOUTL latches high byte XOUTH to allow 10-bit reads. XOUTH should be read directly following XOUTL read. Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte XOUTL latches high byte XOUTH to allow 10-bit reads. XOUTH should be read directly following XOUTL read. Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte YOUTL latches high byte YOUTH to allow coherent 10-bit reads. YOUTH should be read directly following YOUTL. Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte ZOUTL latches high byte ZOUTH to allow coherent 10-bit reads. ZOUTH should be read directly following ZOUTL. Signed byte data (2’s compliment): Zero G = 10’h000 Reading low byte ZOUTL latches high byte ZOUTH to allow coherent 10-bit reads. ZOUTH should be read directly following ZOUTL. Signed byte data (2’s compliment): Zero G = 8’h00 $00: 10bits output value X LSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit XOUT [7] XOUT [6] XOUT [5] XOUT [4] XOUT [3] XOUT [2] XOUT [1] XOUT[0] Function 0 0 0 0 0 0 0 0 Default $01: 10bits output value X MSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- -- XOUT [9] XOUT[8] Function 0 0 0 0 0 0 0 0 Default $02: 10bits output value Y LSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit YOUT [7] YOUT [6] YOUT [5] YOUT [4] YOUT [3] YOUT [2] YOUT [1] YOUT[0] Function 0 0 0 0 0 0 0 0 Default $03: 10bits output value Y MSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- -- YOUT [9] YOUT[8] Function 0 0 0 0 0 0 0 0 Default $04: 10bits output value Z LSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit ZOUT [7] ZOUT [6] ZOUT [5] ZOUT [4] ZOUT [3] ZOUT [2] ZOUT [1] ZOUT[0] Function 0 0 0 0 0 0 0 0 Default $05: 10bits output value X MSB (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- -- ZOUT [9] ZOUT[8] Function 0 0 0 0 0 0 0 0 Default $06: 8bits output value X (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit XOUT[7] XOUT [6] XOUT [5] XOUT [4] XOUT [3] XOUT [2] XOUT [1] XOUT [0] Function 0 0 0 0 0 0 0 0 Default

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Signed byte data (2’s compliment): Zero G = 8’h00 Signed byte data (2’s compliment): Zero G = 8’h00 DRDY 1: Data is ready 0: Data is not ready DOVR 1: Data is over written 0: Data is not over written PERR 1: Parity error is detected in trim data. Then, self test is disabled 0: Parity error is not detected in trim data LDX 1: Level detection detected on X axis 0: Level detection not detected on X axis LDY 1: Level detection detected on Y axis 0: Level detection not detected on Y axis LDZ 1: Level detection detected on Z axis 0: Level detection not detected on Z axis PDX *Note 1: Pulse is detected on X axis at single pulse detection 0: Pulse is not detected on X axis at single pulse detection PDY *Note 1: Pulse is detected on Y axis at single pulse detection 0: Pulse is not detected on Y axis at single pulse detection PDZ *Note 1: Pulse is detected on Z axis at single pulse detection 0: Pulse is not detected on Z axis at single pulse detection Note: This bit value is not valid at double pulse detection INT1 1: Interrupt assigned by “Detection control” register is de- tected 0: Interrupt assigned by “Detection control” register is not detected INT2 1: Interrupt assigned by “Detection control” register is de- tected 0: Interrupt assigned by “Detection control” register is not detected *Note: Must define DRDY to be an output to either INT1 or not. Note: Bit weight is for 2g 8 bit data output. Typical value for reference only. Variation is specified in "Electrical Char- acteristics" section. I2CDIS 0: I2C and SPI are available. 1: I2C is disabled. DVAD[6:0]: I2C device address $07: 8bits output value Y (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit YOUT[7] YOUT [6] YOUT [5] YOUT [4] YOUT [3] YOUT [2] YOUT [1] YOUT [0] Function 0 0 0 0 0 0 0 0 Default $08: 8bits output value Z (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit ZOUT[7] ZOUT [6] ZOUT [5] ZOUT [4] ZOUT [3] ZOUT [2] ZOUT [1] ZOUT [0] Function 0 0 0 0 0 0 0 0 Default $09: Status register (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- PERR DOVR DRDY Function 0 0 0 0 0 0 0 0 Default $0A: Detection source register (Read only) D7 D6 D5 D4 D3 D2 D1 D0 Bit LDX LDY LDZ PDX PDY PDZ INT2 INT1 Function 0 0 0 0 0 0 0 0 Default $0D: I2C Device Address (Bit 6-0: Read only, Bit 7: Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit I2CDIS DVAD[6] DVAD[5] DVAD[4] DVAD[3] DVAD[2] DVAD[1] DVAD[0] Function 0 0 0 1 1 1 0 1 Default

Freescale Semiconductor 17 MMA7455L UI2[7:0]: User information Signed byte data (2’s compliment): User level offset trim value for X axis *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. Signed byte data (2’s compliment): User level offset trim value for X axis Signed byte data (2’s compliment): User level offset trim value for Y axis *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. Signed byte data (2’s compliment): User level offset trim value for Y axis *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. $0E: User Information (Read Only: Optional) D7 D6 D5 D4 D3 D2 D1 D0 Bit UI[7] UI[6] UI[5] UI[4] UI[3] UI[2] UI[1] UI[0] Function 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP Default $0F: “Who Am I” value (Read only: Optional) D7 D6 D5 D4 D3 D2 D1 D0 Bit ID[7] ID [6] ID [5] ID [4] ID [3] ID [2] ID [1] ID [0] Function 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP 0/OTP Default $10: Offset drift X LSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit XOFF[7] XOFF [6] XOFF [5] XOFF [4] XOFF [3] XOFF [2] XOFF [1] XOFF [0] Function 0 0 0 0 0 0 0 0 Default Bit XOFF[7] XOFF[6] XOFF[5] XOFF[4] XOFF[3] XOFF[2] XOFF[1] XOFF[0] Weight (*Note) 64 LSB 32 LSB 16 LSB 8 LSB 4 LSB 2 LSB 1 LSB 0.5 LSB $11: Offset drift X MSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- XOFF [10] XOFF [9] XOFF [8] Function 0 0 0 0 0 0 0 0 Default $12: Offset drift Y LSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit YOFF[7] YOFF [6] YOFF [5] YOFF [4] YOFF [3] YOFF [2] YOFF [1] YOFF [0] Function 0 0 0 0 0 0 0 0 Default Bit YOFF[7] YOFF[6] YOFF[5] YOFF[4] YOFF[3] YOFF[2] YOFF[1] YOFF[0] Weight (*Note) 64 LSB 32 LSB 16 LSB 8 LSB 4 LSB 2 LSB 1 LSB 0.5 LSB $13: Offset drift Y MSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- YOFF [10] YOFF [9] YOFF [8] Function 0 0 0 0 0 0 0 0 Default Bit YOFF[10] YOFF[9] YOFF[8] Weight (*Note) Polarity 256 LSB 128 LSB

18 Freescale Semiconductor

Signed byte data (2’s compliment): User level offset trim value for Z axis *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. Signed byte data (2’s compliment): User level offset trim value for Z axis *Note: Bit weight is for 2g 8bit data output. Typical value for reference only. Variation is specified in “Electrical Characteristics” section. GLVL [1:0] 00: 8g is selected for measurement range. 10: 4g is selected for measurement range. 01: 2g is selected for measurement range. STON 0: Self test is not enabled 1: Self test is enabled SPI3W 0: SPI is 4 wire mode 1: SPI is 3 wire mode DRPD 0: Data ready status is output to INT1/DRDY PIN 1: Data ready status is not output to INT1/DRDY PIN $14: Offset drift Z LSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit ZOFF[7] ZOFF[6] ZOFF[5] ZOFF[4] ZOFF[3] ZOFF[2] ZOFF[1] ZOFF[0] Function 0 0 0 0 0 0 0 0 Default Bit ZOFF[7] ZOFF[6] ZOFF[5] ZOFF[4] ZOFF[3] ZOFF[2] ZOFF[1] ZOFF[0] Weight (*Note) 64 LSB 32 LSB 16 LSB 8 LSB 4 LSB 2 LSB 1 LSB 0.5 LSB $15: Offset drift Z MSB (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- ZOFF[10] ZOFF[9] ZOFF[8] Function 0 0 0 0 0 0 0 0 Default Bit ZOFF[10] ZOFF[9] ZOFF[8] Weight (*Note) Polarity 256 LSB 128 LSB $16: Mode control register (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- DRPD SPI3W STON GLVL[1] GLVL[0] MODE[1] MODE[0] Function 0 0 0 0 0 0 0 0 Default MODE[1:0] Function

Freescale Semiconductor 19 MMA7455L CLR_INT1 1: Clear “INT1” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg- ister setting. 0: Do not clear “INT1” LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register. CLR_INT2 1: Clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg- ister setting. 0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register. EXAMPLE: How to clear both interrupt flags This example is to show how to reset the interrupt flags void ClearIntLatch(void) IIC_ByteWrite(INTRST, 0x03); IIC_ByteWrite(INTRST, 0x00); To clear the interrupts you must first write a logic 1 into both registers and then a logic 0 INTPIN 0: INT1 pin is routed to “INT1” register and INT2 pin is routed to “INT2” register. 1: INT2 pin is routed to “INT1” register and INT1 pin is routed to “INT2” register. Note: Assigned to single pulse detection even if double pulse detection is selected. “Double pulse detection se- lected” means “Time window for 2nd pulse” is not equal to zero. When double pulse detection is selected, INT1 reg- ister bit is not able to be cleared by setting CLR_INT1 bit. It’s cleared by setting CLR_INT2 bit. In this case, setting CLR_INT2 clears both INT1 and INT2 register bits and re- set detecting operation itself. XDA 1: X axis is disabled for detection. 0: X axis is enabled for detection. YDA 1: Y axis is disabled for detection. 0: Y axis is enabled for detection. ZDA 1: Z axis is disabled for detection. 0: Z axis is enabled for detection. THOPT (This bit is valid for level detection only, not valid for pulse detection) 0: Threshold value is absolute only 1: Positive/Negative threshold value is available. DFBW 0: Digital filter band width is 62.5 Hz 1: Digital filter band width is 125 Hz $17: Interrupt latch reset (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit -- -- -- -- -- -- CLR_INT2 CLR_INT1 Function 0 0 0 0 0 0 0 0 Default $18: Control 1 (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit DFBW THOPT ZDA YDA XDA INTREG[1] INTREG[0] INTPIN Function 0 0 0 0 0 0 0 0 Default INTREG[1:0] “INT1” register bit “INT2” register bit

00 Level Detection Pulse Detection

01 Pulse Detection Level Detection

10 Single pulse detection (*Note) Pulse Detection

20 Freescale Semiconductor

0: Level detection polarity is positive and detecting condi- tion is OR 3 axes. 1: Level detection polarity is negative detecting condition is AND 3 axes. PDPL 0: Pulse detection polarity is positive and detecting condi- tion is OR 3 axes. 1: Pulse detection polarity is negative and detecting con- dition is AND 3 axes. DRVO 0: Standard drive strength on SDA/SDO pin 1: Strong drive strength on SDA/SDO pin LDTH[7:0]: Level detection threshold value. If THOPT bit in Detection Control Register is “0”, it is unsigned 7 bits value and LDTH[7] should be “0”. If THOPT bit is “1”, it is signed 8 bits value. PDTH[6:0]: Pulse detection threshold value (unsigned 7 bits). XPDTH: This bit should be “0”. Min: PD[7:0] = 4’h01 = 0.5 ms Max: PD[7:0] = 4’hFF = 127 ms 1 LSB = 0.5 ms Min: LT[7:0] = 8’h01 = 1 ms Max: LT[7:0] = 8’hFF = 255 ms

1 LSB = 1 ms

Min: TW[7:0] = 8’h01 = 1 ms (Single pulse detection) Max: TW[7:0] = 8’hFF = 255 ms $19: Control 2 (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit DRVO PDPL LDPL Function 0 0 0 0 0 0 0 0 Default $1A: Level detection threshold limit value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit LDTH[7] LDTH[6] LDTH[5] LDTH[4] LDTH[3] LDTH[2] LDTH[1] LDTH[0] Function 0 0 0 0 0 0 0 0 Default $1B: Pulse detection threshold limit value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit XPDTH PDTH[6] PDTH[5] PDTH[4] PDTH[3] PDTH[2] PDTH[1] PDTH[0] Function 0 0 0 0 0 0 0 0 Default $1C: Pulse duration value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0] Function 0 0 0 0 0 0 0 0 Default $1D: Latency time value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit LT[7] LT[6] LT[5] LT[4] LT[3] LT[2] LT[1] LT[0] Function 0 0 0 0 0 0 0 0 Default $1E: Time window for 2nd pulse value (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Bit TW[7] TW[6] TW[5] TW[4] TW[3] TW[2] TW[1] TW[0] Function 0 0 0 0 0 0 0 0 Default

output response for 2g mode. Figure 18. Sensing Direction and Output Response at 2g Mode Table 7. Acceleration vs. Output

  • When positioned as shown, the Earth’s gravity will result in a positive 1g output.

22 Freescale Semiconductor

between the board and the package. avoid bridging and shorting between solder pads. Figure 19. Recommended PCB Land Pattern for the will self-align during the solder reflow process. for mounting LGA sensors for consumer applications.

  1. The PCB land should be designed with Non Solder

Mask Defined (NSMD) as shown in Figure 22.

  1. No additional metal pattern underneath package as
  2. PCB land pad is 0.9mm x 0.6mm which is the size of

the package pad plus 0.1mm as shown in Figure 22.

  1. The solder mask opening is equal to the size of the
  2. The stencil aperture size is equal to the PCB land pad

24 Freescale Semiconductor

Figure 24. Stencil Design Guidelines (detailed dimensions for corner pads)

  1. Do not place any components or vias at a distance less
  2. Signal traces connected to pads should be as

Figure 24. Wider trace can be continued after the

  1. Use a standard pick and place process and equipment.

Do not us a hand soldering process.

  1. It is recommended to use a cleanable solder paste with

an additional cleaning step after SMT mount.

  1. Do not use a screw down or stacking to fix the PCB into
  2. The PCB should be rated for the multiple lead-free

reflow condition with max 260°C temperature. mounting guidelines specific to the exact device used. be used successfully for soldering the devices.

Freescale Semiconductor 25 MMA7455L PACKAGE DIMENSIONS CASE 1977-01 ISSUE O 14-LEAD LGA

26 Freescale Semiconductor

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