MMA6821BKCW

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 56

Technical content

Features

• ± 2 0 g to ±120 g full-scale range, independently specified for each axis
• 3.3 V or 5 V single supply operation
• SPI-compatible serial interface
• 10-bit digital signed or unsigned SPI data output
• Independent programmable arming functions for each axis
• Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz
• Optional offset cancellation with > 6 s averaging period and < 0.25 LSB/s slew rate
• Pb-Free 16-Pin QFN, 6 mm x 6 mm x 1.98 mm package Referenced Documents
• AEC-Q100, Revision G, dated May 14, 2007 ( http://www.aecouncil.com/ ORDERING INFORMATION* Device X-axis Range Y-axis Range Package Shipping MMA6811BKCW ±60 g ±25 g 98ASA00690D Tubes MMA6813BKCW ±50 g ±50 g 98ASA00690D Tubes MMA6821BKCW ±120 g ±25 g 98ASA00690D Tubes MMA6823BKCW ±120 g ±60 g 98ASA00690D Tubes MMA6825BKCW ±100 g ±100 g 98ASA00690D Tubes MMA6826BKCW ±60 g ±60 g 98ASA00690D Tubes MMA6827BKCW ±120 g ±120 g 98ASA00690D Tubes MMA6811BKTW ±60 g ±25 g 98ASA00090D Tubes MMA6813BKTW ±50 g ±50 g 98ASA00090D Tubes MMA6821BKTW ±120 g ±25 g 98ASA00090D Tubes MMA6823BKTW ±120 g ±60 g 98ASA00090D Tubes MMA6825BKTW ±100 g ±100 g 98ASA00090D Tubes MMA6826BKTW ±60 g ±60 g 98ASA00090D Tubes MMA6827BKTW ±120 g ±120 g 98ASA00090D Tubes MMA6811BKCWR2 ±60 g ±25 g 98ASA00690D Tape & Reel MMA6813BKCWR2 ±50 g ±50 g 98ASA00690D Tape & Reel MMA6821BKCWR2 ±120 g ±25 g 98ASA00690D Tape & Reel MMA68xx Pin Connections Bottom View VREGA VSS N/C VSSA N/C VSSA TEST/VPP MISO MOSI SCLK V CC VSS VREG ARM_X/PCM_X 5 6 7 8 16 15 14 13 CS ARM_Y/PCM_Y Top View Pb-Free 16-Pin QFN 6 mm x 6 mm x 1.98 mm package

2 NXP Semiconductors

• Refer to Section 5.1 for additional information on device suffixes. MMA6823BKCWR2 ±120 g ±60 g 98ASA00690D Tape & Reel MMA6825BKCWR2 ±100 g ±100 g 98ASA00690D Tape & Reel MMA6826BKCWR2 ±60 g ±60 g 98ASA00690D Tape & Reel MMA6827BKCWR2 ±120 g ±120 g 98ASA00690D Tape & Reel MMA6811BKTWR2 ±60 g ±25 g 98ASA00090D Tape & Reel MMA6813BKTWR2 ±50 g ±50 g 98ASA00090D Tape & Reel MMA6821BKTWR2 ±120 g ±25 g 98ASA00090D Tape & Reel MMA6823BKTWR2 ±120 g ±60 g 98ASA00090D Tape & Reel MMA6825BKTWR2 ±100 g ±100 g 98ASA00090D Tape & Reel MMA6826BKTWR2 ±60 g ±60 g 98ASA00090D Tape & Reel MMA6827BKTWR2 ±120 g ±120 g 98ASA00090D Tape & Reel ORDERING INFORMATION* (continued)

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Figure 4. Block Diagram

8 MHz

1 MHz

1 MHz Regulator

1 Pin Connections

Figure 5. 16-Pin QFN Package, Top View Table 2. Pin Description

1 VREGA Analog

connected between this pin and VSSA. Reference Figure 1. 2 VSS Digital GND This pin is the power supply return node for the digital circuitry.

3 VREG Digital

connected between this pin and VSS. Reference Figure 1. 4 VSS Digital GND This pin is the power supply return node for the digital circuitry.

5 ARM_Y/

6 ARM_X/

7 TEST/

8 MISO SPI Data Out This pin functions as the serial data output for the SPI port. 9 VCC Supply This pin supplies power to the device. An external capacitor must be connected between this pin and VSS. 10 SCLK SPI Clock This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin. 11 MOSI SPI Data In This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin. 12 CS Chip Select This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin. 13 VSSA Analog GND This pin is the power supply return node for analog circuitry.

14 N/C No Connect No Connection

15 N/C No Connect No Connection

16 VSSA Analog GND This pin is the power supply return node for analog circuitry. 17 PAD Die Attach Pad This pin is the die attach flag, and is internally connected to VSS. Pads Corner Pads The corner pads are internally connected to VSS.

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2 Electrical Characteristics

2.1 Maximum Ratings

Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.

2.2 Operating Range

The operating ratings are the limits normally expected in the application and define the range of operation. # Rating Symbol Value Unit 1 Supply Voltage VCC –0.3 to +7.0 V (3) 2 CREG, CREGA VREG –0.3 to +3.0 V (3) 3 SCLK, CS, MOSI, VPP/TEST VIN –0.3 to VCC + 0.3 V (3) 4 ARM_X, ARM_Y VIN –0.3 to VCC + 0.3 V (3) 5 MISO (high impedance state) VIN –0.3 to VCC + 0.3 V (3)

6 Acceleration without hitting internal g-cell stops ggcell_Clip ±500 g (3, 18)

7 Acceleration without saturation of internal circuitry g ADC_Clip ±375 g (3)

8 Powered Shock (six sides, 0.5 ms duration) g pms ±1500 g (5, 18) 9 Unpowered Shock (six sides, 0.5 ms duration) g shock ±2000 g (5, 18) 10 Drop Shock (to concrete surface) h DROP 1.2 m (5) Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) V ESD VESD VESD ±2000 ±750 ±200 V V V (5) (5) (5)

14 Storage Temperature Range T

stg –40 to +125 °C (5) 15 Thermal Resistance - Junction to Case θJC 2.5 °C/W (14) # Characteristic Symbol Min Typ Max Units Supply Voltage Standard Operating Voltage, 3.3 V Standard Operating Voltage, 5.0 V V CC VL +3.135 VTYP +3.3 +5.0 V H +5.25 V V (15) (15) Operating Ambient Temperature Range Verified by 100 % Final Test T A TL –40 ⎯ TH +105 C (1) 19 Power-on Ramp Rate (VCC)V CC_r 0.000033 ⎯ 3300 V/ μs (19)

2.3 Electrical Characterist ics - Power Supply and I/O

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic Symbol Min Typ Max Units 20 Supply Current (4) I DD 4.0 ⎯ 9.0 mA (1) Power Supply Monitor Thresholds (See Figure 9) V CC Undervoltage (Falling) VREG Undervoltage (Falling) VREG Overvoltage (Rising) VREGA Undervoltage (Falling) VREGA Overvoltage (Rising) Power Supply Monitor Hysteresis VCC Undervoltage (Falling) VREG Undervoltage, VREG Overvoltage VREGA Undervoltage, VREGA Overvoltage (4) (4) (4) (4) (4) V CC_UV_f VREG_UV_f VREG_OV_r VREGA_UV_f VREGA_OV_r VHYST VHYST VHYST 2.74 2.10 2.65 2.20 2.65 100 100 100 3.02 2.25 2.85 2.35 2.85 110 210 150 V V V V V mV mV mV (3, 6) (3, 6) (3, 6) (3, 6) (3, 6) (3) (3) (3) Power Supply RESET Thresholds (See Figure 6, and Figure 9) V REG Undervoltage RESET (Falling) VREG Undervoltage RESET (Rising) VREG RESET Hysteresis (4) (4) VREG_UVR_f VREG_UVR_r VHYST 1.764 1.876 2.024 2.152 140 V V mV (3, 6) (3, 6) (3) Internally Regulated Voltages V REG VREGA (4) (4) V REG VREGA 2.42 2.42 2.50 2.50 2.58 2.58 V V (1, 3) (1, 3) External Filter Capacitor (C REG, CREGA) Value ESR (including interconnect resistance) C REG ESR 700 1000 1500 400 nF mΩ (19) (19) Power Supply Coupling 50 kHz ≤ f n ≤ 300 kHz

4 MHz ≤ fn ≤ 100 MHz

0.004 0.004 LSB/mv LSB/mv (19) (19) Output High Voltage (MISO, PCM_X, PCM_Y)

3.15 V ≤ (V

CC - VSS) ≤ 3.45 V (ILoad = –1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (ILoad = –1 mA) (4) (4) V OH_3 VOH_5 VCC - 0.2 VCC - 0.4 V V (2,3) (2,3) Output Low Voltage (MISO , PCM_X, PCM_Y) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (ILoad = 1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (ILoad = 1 mA) (4) (4) V OL_3 VOL_5 0.2 0.4 V V (2, 3) (2, 3) Open Drain Output High Voltage (ARM_X, ARM_Y) CC - VSS) ≤ 3.45 V (IARM = –1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (IARM = –1 mA) (4) (4) VODH_3 VODH_5 VCC - 0.2 VCC - 0.4 V V (2, 3) (2, 3) Open Drain Output Pulldown Current (ARM_X, ARM_Y) CC - VSS) ≤ 3.45 V (VARM = 1.5 V) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (VARM = 1.5 V) (4) (4) I ODPD_3 IODPD_5 100 100 μA μA (2, 3) (2,3) Open Drain Output Low Voltage (ARM_X, ARM_Y) CC - VSS) ≤ 3.45 V (IARM = 1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (IARM = 1 mA) (4) (4) VODH_3 VODH_5 0.2 0.4 V V (2, 3) (2, 3) Open Drain Output Pullup Current (ARM_X, ARM_Y) CC - VSS) ≤ 3.45 V (VARM = 1.5 V) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (VARM = 1.5 V) (4) (4) IODPU_3 IODPU_5 –100 –100 –50 –50 μA μA (2, 3) (2, 3)

50 Input High Voltage CS

, SCLK, MOSI (4) V IH 2.0 ⎯⎯ V( 3 , 6 ) 51 Input Low Voltage CS, SCLK, MOSI (4) V IL ⎯⎯ 1.0 V (3, 6) 52 Input Voltage Hysteresis CS, SCLK (4) V I_HYST 0.125 ⎯ 0.500 V (19) Input Current High (at VIH) (SCLK, MOSI) Low (at VIL) (CS) (4) (4) I IH IIL –260 –50 –30 260 μA μA (2, 3) (2, 3)

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2.4 Electrical Characteristi cs - Sensor and Signal Chain

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic Symbol Min Typ Max Units X-axis Digital Sensitivity (SPI, 10-bit Output) 50 g (MMA6813) 60 g (MMA6811, MMA6826) 100 g (MMA6825) 120 g (MMA6821, MMA6823) (4) (4) (4) (4) SENS SENS SENS SENS 9.766 8.192 4.883 4.096 LSB/g LSB/g LSB/g LSB/g (1, 9) (1, 9) (1, 9) (1, 9) Y-axis Digital Sensitivity (SPI, 10-bit Output) 25 g (MMA6811, MMA6821) 50 g (MMA6813QR) 60 g (MMA6823, MMA6826) 100 g (MMA6825) (4) (4) (4) (4) SENS SENS SENS SENS 20.479 9.766 8.192 4.883 LSB/g LSB/g LSB/g LSB/g (1, 9) (1, 9) (1, 9) (1, 9) Sensitivity Error T A = 25°C –40 °C ≤ TA ≤ 105 °C –40°C ≤ TA ≤ 105 °C,VCC_UV_f ≤ VCC - VSS ≤ VL (4) (4) ΔSENS ΔSENS ΔSENS (1) (1) (3) Offset at 0 g (No Offset Cancellation) 10-bits, unsigned 10-bits, signed 10-bits, unsigned, V CC_UV_f ≤ VCC - VSS ≤ VL 10-bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL (4) (4) OFFSET OFFSET OFFSET OFFSET 452 –60 452 –60 512 512 572 +60 572 +60 LSB LSB LSB LSB (1) (1) (3) (3) Offset Monitor Thresholds Positive Threshold (10-bits, unsigned) Negative Threshold (10-bits, unsigned) OFFTHR POS OFFTHRNEG ⎯ 612 412 LSB LSB (7) (7) Range of Output (SPI, 10-bits unsigned) Normal Fault Response Code Unused Codes Unused Codes RANGE FAULT UNUSED UNUSED 993 992 1023 LSB LSB LSB LSB (7) (7) (7) (7) Range of Output (SPI, 10-bits, signed) Normal Fault Response Code Unused Codes Unused Codes RANGE FAULT UNUSED UNUSED –480 –511 481 –512 480 –481 511 LSB LSB LSB LSB (7) (7) (7) (7)

80 Nonlinearity (4) NL

OUT –1 — 1 % FSR (3) System Output Noise RMS (10-bit, All Ranges, 400 Hz, 4-pole LPF) Peak to Peak (10-bit, All Ranges, 400 Hz, 4-pole LPF) n RMS nP-P 0.5 1.0 LSB LSB (3) (3) Cross-axis Sensitivity V ZX VYX VZY VXY (4) (4) (4) (4) V ZX VYX VZY VXY (3) (3) (3) (3) Self-test Output Change (Ref Section 3.6) STMAG_X, STMAG_Y = 0, T A = 25 °C STMAG_X, STMAG_Y = 0, –40 °C ≤ TA ≤ 105 °C STMAG_X, STMAG_Y = 1, TA = 25 °C STMAG_X, STMAG_Y = 1, –40 °C ≤ TA ≤ 105 °C STMAG_X, STMAG_Y = 0, –40 °C ≤ TA ≤ 105 °C VCC_UV_f ≤ VCC - VSS ≤ VL STMAG_X, STMAG_Y = 1, –40 °C ≤ TA ≤ 105 °C VCC_UV_f ≤ VCC - VSS ≤ VL (4) (4) (4) ΔST Low25 ΔSTLow ΔSTHI25 ΔSTHI ΔSTLow ΔSTHI ΔSTMIN 11.25 10.68 22.5 21.37 10.68 21.37 ΔST NOM ΔST MAX 18.75 19.69 37.5 39.38 19.69 39.38 g g g g g g (1) (1) (1) (1) (3) (3) Self-test Cross Axis Output Y-axis Output with X-axis Self-test X-axis Output with Y-axis Self-test ΔSTCrossAxis ΔSTCrossAxis –10 –10 +10 +10 LSB LSB (1) (1) Acceleration (without hitting internal g-cell stops) X/Y-axis, Any Range Positive/Negative g g-cell_Clip 500 560 600 g (19)

2.5 Dynamic Electrical Char acteristics - Signal Chain

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic Symbol Min Typ Max Units DSP Sample Rate (LPF 0, 1, 2, 3, 4, 5) DSP Sample Rate (LPF 8, 9, 10, 11, 12, 13) Interpolation Sample Rate t S tS tINTERP 64/fOSC 128/fOSC tS/2 s s s (7) (7) (7) 100 Datapath Latency (excluding g-cell and Low Pass Filter) TS = 64/fOSC TS = 128/fOSC (4) (4) tDataPath_8 tDataPath_16 33.0 51.9 34.8 54.6 36.5 57.4 μs μs (7, 16) (7, 16) 101 102 103 104 105 106 Low-Pass Filter (t s = 8μs) Cutoff frequency 0: 100 Hz, 4-pole Cutoff frequency 1: 300 Hz, 4-pole Cutoff frequency 2: 400 Hz, 4-pole Cutoff frequency 3: 800 Hz, 4-pole Cutoff frequency 4: 1000 Hz, 4-pole Cutoff frequency 5: 400 Hz, 3-pole (4) (4) (4) (4) (4) (4) f C0(LPF) fC1(LPF) fC2(LPF) fC3(LPF) fC4(LPF) fC5(LPF) 285 380 760 950 380 100 300 400 800 1000 400 105 315 420 840 1050 420 Hz Hz Hz Hz Hz Hz (3, 7, 17) (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) 107 108 109 110 111 112 Low-Pass Filter (t s = 16μs) Cutoff frequency 8: 50 Hz, 4-pole Cutoff frequency 9: 150 Hz, 4-pole Cutoff frequency 10: 200 Hz, 4-pole Cutoff frequency 11: 400 Hz, 4-pole Cutoff frequency 12: 500 Hz, 4-pole Cutoff frequency 13: 200 Hz, 3-pole (4) (4) (4) (4) (4) (4) f C8(LPF) fC9(LPF) fC10(LPF) fC11(LPF) fC12(LPF) fC13(LPF) 47.5 142.5 190 380 475 190 150 200 400 500 200 52.5 157.5 210 420 525 210 Hz Hz Hz Hz Hz Hz (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) 113 114 115 116 117 118 119 Offset Cancellation (Normal Mode, 10-bit Output) Offset Averaging Period Offset Slew Rate Offset Update Rate Offset Correction Value per Update Positive Offset Correction Value per Update Negative Offset Correction Threshold Positive Offset Correction Threshold Negative (4) (4) (4) (4) (4) (4) (4) OFF AVEPER OFFSLEW OFFRATE OFFCORRP OFFCORRN OFFTHP OFFTHN 6.291456 0.2384 1049 0.25 –0.25 0.125 0.125 s LSB/s ms LSB LSB LSB LSB (7) (7) (7) (7) (7) (7) (7)

120 Offset Monitor Bypass Time after Self-test Deactivation t

ST_OMB ⎯ 320 ⎯ tS (3, 7)

121 Time Between Acceleration Data Requests (Same Axis) t ACC_REQ 15 ⎯⎯ μ s (3, 7, 20)

Arming Output Activation Time (ARM_X, ARM_Y, IARM = 200 μA) Moving Average and Count Arming Modes (2, 3, 4, 5) Unfiltered Mode Activation Delay (Reference Figure 28) Unfiltered Mode Arm Assertion Time (Reference Figure 28) tARM tARM_UF_DLY tARM_UF_ASSERT 5.00 1.05 1.05 6.579 μs μs μs (3, 12) (3, 12) (3)

125 Sensing Element Natural Frequency (–40 °C ≤ T

A ≤ 105 °C) f gcell 10791 ⎯ 15879 Hz (19) 126 Sensing Element Cutoff Frequency (–3 dB ref. to 0 Hz, –40 °C ≤ TA ≤ 105 °C) fgcell 0.851 ⎯ 2.29 kHz (19) 127 Sensing Element Damping Ratio (–40 °C ≤ TA ≤ 105 °C) ζgcell 2.46 ⎯ 9.36 ⎯ (19)

128 Sensing Element Delay (@100 Hz, –40 °C ≤ TA ≤ 105 °C) f gcell_delay 70 ⎯ 187 μs (19)

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2.6 Dynamic Electrical Char acteristics - Supply and SPI

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified 1. Parameters tested 100 % at final test. 2. Parameters tested 100 % at wafer probe. 3. Parameters verified by characterization 4. Indicates a critical characteristic. 5. Verified by qualification testing. 6. Parameters verified by pass/fail testing in production. 7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is deter- mined by internal system clock frequency. 8. N/A 9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response. 10.Low-pass filter cutoff frequencies shown are –3dB referenced to 0 Hz response. 11.Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible. 12.Time from falling edge of CS to ARM_X, ARM_Y output valid. 13.N/A 14.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad. 15.Device characterized at all values of V L and VH. Production test is conducted at all typical voltages (VTYP) unless otherwise noted. 16.Data path Latency is the signal latency from g-cell to SPI output disregarding filter group delays. 17.Filter characteristics are specified independently, and do not include g-cell frequency response. 18.Electrostatic Deflection Test completed during wafer probe. 19.Verified by simulation. 20.Acceleration Data Request timing constraint only applies for proper operation of the Arming Function. # Characteristic Symbol Min Typ Max Units 131 132 Power-On Recovery Time(VCC = VCCMIN to first SPI access) Power-On Recovery Time(Internal POR to first SPI access) tOP tOP 840 ms μs (3) (3, 7) 133 134 Internal Oscillator Frequency Test Frequency - Divided from Internal Oscillator (4) f OSC fOSCTST 7.6 0.95 8.4 1.05 MHz MHz (7) (1) 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Serial Interface Timing (See Figure 7, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ) Clock (SCLK) period (10 % of VCC to 10 % of VCC) Clock (SCLK) high time (90 % of VCC to 90 % of VCC) Clock (SCLK) low time (10 % of VCC to 10 % of VCC) Clock (SCLK) rise time (10 % of VCC to 90 % of VCC) Clock (SCLK) fall time (90 % of VCC to 10 % of VCC) CS asserted to SCLK high (CS = 10 % of VCC to SCLK = 10 % of VCC) CS asserted to MISO valid (CS = 10 % of VCC to MISO = 10/90 % of VCC) Data setup time (MOSI = 10/90 % of VCC to SCLK = 10 % of VCC) MOSI Data hold time (SCLK = 90 % of VCC to MOSI = 10/90 % of VCC) MISO Data hold time (SCLK = 90 % of VCC to MISO = 10/90 % of VCC) SCLK low to data valid (SCLK = 10 % of VCC to MISO = 10/90 % of VCC) SCLK low to CS high (SCLK = 10 % of VCC to CS = 90 % of VCC) CS high to MISO disable (CS = 90 % of VCC to MISO = Hi Z) CS high to CS low (CS = 90 % of VCC to CS = 90 % of VCC) SCLK low to CS low (SCLK = 10 % of VCC to CS = 90 % of VCC) CS high to SCLK high (CS = 90 % of VCC to SCLK = 90 % of VCC) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) t SCLK tSCLKH tSCLKL tSCLKR tSCLKF tLEAD tACCESS tSETUP tHOLD_IN tHOLD_OUT tVALID tLAG tDISABLE tCSN tCLKCS tCSCLK 120 526 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) (3) (19) (19) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (19)

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3 Functional Description

3.1 Customer Accessible Data Array

trim values. The customer accessible data is shown in Table 3. Table 3. Customer Accessible Data

3.1.1 Device Serial Number Registers

lot size and quantities, all possible lot numbers and serial numbers may not be assigned. operation or performance, and are only used for traceability purposes.

3.1.2 Reserved Registers

These reserved registers are read-only and have no impact on device operation or performance.

3.1.3 Factory Configuration Registers

configuration information that is programmed by NXP.

3.1.3.1 Self-test Magnitude Sele ction Bits (STMAG_Y, STMAG_X)

in the table below. The Self-test Magnitude is selected independently for each axis. Table 4. Reserved Registers Table 5. Factory Configuration Registers

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3.1.4 Part Number Register (PN)

to identify the axis and range information. The contents of this register have no impact on device operation or performance. Table 6. Part Number Register

3.1.5 Device Control Register (DEVCTL)

initialization and normal operation.

3.1.5.1 Reset Control (RES_1, RES_0)

A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset. register write operations must be consecutive SPI commands in the order shown or the device will not be reset. terminates the reset sequence.

3.1.5.2 Reserved Bits (DEVCTL[5:0])

3.1.6 Device Configuration Register (DEVCFG)

check. Refer to Section 3.2.2 for details.

3.1.6.1 Reserved Bits (Reserved)

3.1.6.2 End of Initialization Bit (ENDINIT)

(reference Section 3.2.2) is only enabled when the ENDINIT bit is set. Table 7. Device Control Register Table 8. Device Configuration Register

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3.1.6.3 SD Bit

g level represented by a nominal value of 0.

3.1.6.4 OFMON Bit

3.1.6.5 ARM Configurat ion Bits (A_CFG[2:0])

The ARM Configuration Bits (A_CFG[2:0]) select the mode of operation for the ARM_X/PCM_X, ARM_Y/PCM_Y pins.

3.1.7 Axis Configuration Registers (DEVCFG_X, DEVCFG_Y)

CRC check. Refer to Section 3.2.2 for details.

1 Unsigned Data Output

0 Signed Data Output

1 Offset Monitor Circuit Enabled

0 Offset Monitor Circuit Disabled

Table 9. Arming Output Configuration Table 10. Axis Configuration Registers

3.1.7.1 Self-test Control (ST_X, ST_Y)

cleared following internal reset. indicate that self-test has been deactivated.

3.1.7.2 Reserved Bits (Reserved)

’0’ for normal device operation and performance.

3.1.7.3 Low-Pass Filter Selection Bits (LPF_X[3:0], LPF_Y[3:0])

3.8.3 for details regarding filter configurations.

3.1.8 Arming Configuration Registers (ARMCFGX, ARMCFGY)

only relevant if the arming function is operating in moving average mode, or count mode. registers are included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 11. Low Pass Filter Selection Bits Table 12. Arming Configuration Register

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3.1.8.1 Reserved Bits (Reserved)

for normal device operation and performance.

3.1.8.2 Arming Pulse Stretch (APS_X[1:0], APS_Y[1:0])

for more details regarding the arming function.

3.1.8.3 Arming Window Size (AWS_Xx[1:0], AWS_Yx[1:0])

Refer to Section 3.8.9 for more details regarding the arming function. Table 13. Arming Pulse Stretch Definitions 1.Pulse stretch times are derived from the internal oscillator, so the tolerance on this oscillator applies. Table 14. X-axis Positive Arming Window Size Definitions (Moving Average Mode) Table 15. X-axis Negative Arming Window Size Definitions (Moving Average Mode) Table 16. Y-axis Positive Arming Window Size Definitions (Moving Average Mode)

Table 17. Y-axis Negative Arming Window Size Definitions (Moving Average Mode) Table 18. Arming Count Limit Definitions (Count Mode) Table 19. Arming Count Limit Definitions (Count Mode)

20 NXP Semiconductors

3.1.9 Arming Threshold Registers (ARMT_XP, ARMT_XN, ARMT_YP, ARMT_YN)

Section 3.8.9 for more details regarding the arming function. registers are included in the writable register CRC check. Refer to Section 3.2.2 for details. If either the positive or negative threshold for one axis is programmed to $00, comparisons are disabled for only that polarity. of the value of the A_CFG bits in the DEVCFG register.

3.1.10 Device Status Register (DEVSTAT)

The device status register is a read-only register. A read of this register clears the status flags affected by transient conditions. Reference Section 4.5 for details on the MMA68xx response for each status condition.

3.1.10.1 Unused Bit (UNUSED)

The unused bit has no impact on operation or performance. When read this bit may be ’1’ or ’0’.

3.1.10.2 Internal Data Error Flag (IDE)

data stored in the fuse array, the fault will be re-asserted even after a device reset. Table 20. Arming Threshold Registers Table 21. Threshold Register Value Examples Table 22. Device Status Register

3.1.10.3 Sigma Delta Modulator Over Range Flag (SDOV)

flag is cleared by a read of the DEVSTAT register.

3.1.10.4 Device Initializ ation Flag (DEVINIT)

initialization. DEVINIT is cleared automatically. The device initialization flag is not affected by a read of the DEVSTAT register.

3.1.10.5 SPI MISO Data Mism atch Error Flag (MISOERR)

flag is cleared by a read of the DEVSTAT register.

3.1.10.6 Offset Monitor Over Range Flags (OFF_X, OFFSET_Y)

The offset monitor over range flags are set if the acceleration signal of the associated axis reaches the specified offset limit. The offset monitor over range flags are cleared by a read of the DEVSTAT register.

3.1.10.7 Device Reset Flag (DEVRES)

3.1.11 Count Register (COUNT)

by one count every 128 μs and the counter rolls over every 32.768 ms.

3.1.12 Offset Correction Value Registers (OFFCORR_X, OFFCORR_Y)

being applied to the SPI output data. The values have a resolution of 1 LSB.

3.1.13 Reserved Registers (Reserved)

Table 23. Count Register Table 24. Offset Correction Value Register Table 25. Reserved Registers

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3.2 Customer Accessible Data Array CRC Verification

3.2.1 OTP Shadow Register Array CRC Verification

The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of g(x) = X 3+ X + 1, with a seed value = ’111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register.

3.2.2 Writable Register CRC Verification

The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ’111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register.

3.3 Voltage Regulators

Figure 1. The voltage regulator module includes voltage monitoring circuitry which indicates a device reset until the external is used by the ΣΔ converters. Figure 8. Power Supply Figure 9. Voltage Monitoring

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3.3.1 C REG Failure Detection

The digital supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREG capacitor becomes open, the digital supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal sample time. This failure will result in one of the following: 1. The DEVRES flag in the DEVSTAT register will be set. MMA68xx will respond to SPI acceleration requests as defined in Table 30. 2. MMA68xx will be held in RESET and be non-responsive to SPI requests.

3.3.2 C REGA Failure Detection

The analog supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREGA capacitor becomes open, the analog supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal sample time. The DEVRES flag in the DEVSTAT register will be set. MMA68xx will respond to SPI acceleration requests as defined in Table 30. Note: This feature is only supported with a VCC supply voltage in the range of 4.75 V to 5.25 V.

3.3.3 V SS and VSSA Ground Loss Monitor

MMA68xx detects the loss of ground connection to either VSS or VSSA. A loss of ground connection to VSS will result in a VREG overvoltage failure. A loss of ground connection to VSSA will result in a VREG undervoltage failure. Both failures result in a device reset.

3.3.4 SPI Initiated Reset

In addition to voltage monitoring, a device reset can be initiated by a specific series of three write operations involving the

3.4 Internal Oscillator

MMA68xx includes a factory trimmed oscillator as specified in Section 2.6.

3.4.1 Oscillator Monitor

The COUNT register in the customer accessible array is a read-only register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator by 1024. Thus, the value in the COUNT register increases by one count every 128 μs, and the register rolls over every 32.768 ms. The SPI master can periodically read the COUNT register, and verify the difference between subsequent register reads against the system time base. 1. The SPI access rates and deviations must be take n into account for this oscillator verification.

3.5 Transducer

The MMA68xx transducer is an overdamped mass-spring-damper system described by the following transfer function: where: ζ = Damping Ratio ωn = Natural Frequency = 2∗Π∗fn Reference Section 2.4 for transducer parameters. Hs() ωn s2 2 ξω n s⋅⋅ ⋅ ω n 2++

3.6 Self-test Interface

DEVCFG register must also be low to enable self-test. A diagram of the self-test interface is shown in Figure 10. Figure 10. Self-test Interface ΔSTMIN The minimum self-test deflection over temperature as specified in Section 2.4. ΔSTMAX The maximum self-test deflection over temperature as specified in Section 2.4.

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stream at a nominal frequency of 1 MHz. Figure 11. ΣΔ Converter Block Diagram

3.8 Digital Signal Processing Block

the signal processing flow is shown in Figure 12. Figure 12. Signal Chain Diagram Table 26. MMA68xx Signal Chain Characteristics

3.8.1 DSP Clock

are processed through independent data paths within the DSP. Figure 13. Clock Generation

3.8.2 Decimation Sinc Filter

filter with a decimation factor of 8 or 16, depending on the Low Pass Filter selected. Figure 14. Sinc Filter Response, tS = 8 μs

8 MHz OSC

6 MHz Digital

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3.8.3 Low Pass Filter

Data from the Sinc filter is processed by an infinite impulse response (IIR) low pass filter. illustrated in Figures 15, 16, 17, 18, 19 and 20. Note: Low Pass Filter Figures do not include g-cell frequency response. Table 27. Low Pass Filter Coefficients

50 Hz LPF 16

100 Hz LPF 8

150 Hz LPF 16

300 Hz LPF 8

200 Hz LPF 16

400 Hz LPF 8

200 Hz LPF

400 Hz LPF

400 Hz LPF 16

800 Hz LPF 8

500 Hz LPF 16

1000 Hz LPF 8

Figure 15. Low-Pass Filter Characteristics: fC = 100 Hz, Poles = 4, tS = 8 μs

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Figure 16. Low-Pass Filter Characteristics: fC = 300 Hz, Poles = 4, tS = 8 μs

Figure 17. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 4, tS = 8 μs

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Figure 18. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 3, tS = 8 μs

Figure 19. Low-Pass Filter Characteristics: fC = 800 Hz, Poles = 4, tS = 8 μs

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Figure 20. Low-Pass Filter Characteristics: fC = 1000 Hz, Poles = 4, tS = 8 μs

3.8.4 Offset Cancellation

in Section 2.4 and in Table 28. Figure 21. Offset Cancellation Block Diagram correction value that will be applied to the acceleration data. During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. Reference Table 28 for offset cancellation timing information during startup and normal operation. tST_OMB to allow the acceleration output to return to its nominal offset.

3.8.5 Offset Monitor

also update at this rate. The time to indicate an Offset Over Range is dependent upon the input signal.

3.8.6 Signal Compensation

is necessary to achieve the specified parameters in Section 2.4. Table 28. Offset Cancellation Timing Specifications

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3.8.7 Data Interpolation

sample times. This operation is illustrated in Figure 22. Figure 22. Data Interpolation Timing Figure 23. Data Interpolation Example Response to SPI acceleration request occurring in this window receives true sample.

3.8.8 Acceleration Data Timing

The MMA68xx SPI uses a request/response protocol, where a SPI transfer is completed through a sequence of 2 phases. Reference Section 4 for more details regarding the SPI protocol. In order to provide the most recent acceleration data for each request, MMA68xx latches the associated data for an acceleration request at the falling edge of CS for the acceleration response message (the subsequent SPI transfer). The most recent sample available from the DSP (including interpolation), is latched, providing a maximum latency of 1* tS relative to the falling edge of CS. SCLK MOSI MISO CS Request X-axis Request Y-axis X-axis Response Y-axis Response Request X-axis Request Y-axis X-axis Response X-axis Data Latched Y-axis Data Latched X-axis Arm Function updated if applicable Y-axis Arm Function updated if applicable

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3.8.9 Arming Function

selected by the state of the A_CFG bits in the DEVCFG register. condition will continue. However, new acceleration reads will not update the arming function regardless of the acceleration value.

3.8.9.1 Arming Function: Moving Average Mode

In moving average mode, the arming function runs a moving average on the offset cancelled output of each acceleration axis. ARMCFGX and ARMCFGY registers. Reference Section 3.1.8 for register details. Where n is the current sample. acceleration data SPI response, the moving average for the associated axis is updated with a new sample. Reference Figure 26. The SPI acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5. and the pulse stretch counter is set as described in Section 3.8.9.4. operation for different SPI conditions. Figure 24. Arming Function Block Diagram - Moving Average Mode

3.8.9.2 Arming Function: Count Mode

acceleration data SPI response, a new sample for the associated axis is compared against the thresholds. Reference Figure 26. The SPI acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5. A sample count limit is programmable via the AWS_Xx[1:0] and AWS_Yx[1:0] bits in the ARMCFGX and ARMCFGY registers. is asserted for the associated axis, and the pulse stretch counter is set as described in Section 3.8.9.4. operation for different SPI conditions. Figure 25. Arming Function Block Diagram - Count Mode Figure 26. X and Y Axis Arming Conditions, Moving Average and Count Mode

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3.8.9.3 Arming Function: Unfiltered Mode

includes an acceleration response for that axis. includes an acceleration response for that axis. The pulse stretch function is not applied in Unfiltered mode. operation under the different SPI request conditions. Figure 27. Arming Function Block Diagram - Unfiltered Mode Figure 28. X and Y Axis Arming Conditions, Unfiltered Mode

3.8.9.4 Arming Pulse Stretch Function

A pulse stretch function can be applied to the arming outputs in moving average mode, or count mode. after the most recent evaluated sample. Reference Figure 26. not reset the pulse stretch counter regardless of the acceleration value.

3.8.9.5 Arming Pin Output Structure

Figure 29. Arming Function - Pin Output Structure

3.8.10 PCM Output Function

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Exception conditions affect the PCM output as listed in Section 4.5. Figure 30. PCM Output Function Block Diagram

9 Bit ADDER

3.9 Serial Peripheral Interface

MMA68xx includes a Serial Peripheral Interface (SPI) to provide access to the configuration registers and digital data. Reference Section 4 for details regarding the SPI protocol and available commands. operates as a single device. The internal independent blocks are transparent. block enables MISO for a response during the next SPI message. Figure 31 shows an internal diagram of the MMA68xx SPI. Figure 31. SPI Diagram

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3.10 Device Initialization

Figure 32. Initialization Process Notes:1) X-axis and Y-axis Self-test can be enabled and evaluated simultaneously to reduce test time. For failure mode coverage of the arming pins and of potential common axis failures, NXP recommends independent self-test activation. 2) tSTRISE and tSTFALL are dependent on the selected LPF group delay.

3.11 Overload Response

3.11.1 Overload Performance

• g-cell damping
• Non-linearity
• Clipping limits
• Symmetry Figure 33 shows the g-cell, ADC and output clipping of MMA68xx over frequency. The relevant parameters are specified in Section 2.1, and Section 2.6.

Figure 33. Output Clipping Vs. Frequency

3.11.2 Sigma Delta Over Range Response

after returning to the normal range of operation due to non-linear effects of the sensor.

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4 SPI Communications

intermediate transfers involving other SPI devices may occur between phase one and phase two. Reference Figure 34. Figure 34. SPI Transfer Detail

4.1 SPI Command Format

and acceleration data requests. Table 29. SPI Command Message Summary

0 AX A OC 0 0 0 0 0 0 0 0 0 SD AR

0 X-axis Acceleration Data

1 Y-axis Acceleration Data

0 Register Operation

1 Acceleration Data

0 Offset Cancelled Data Request

1 Raw Acceleration Data Request

0010000000000000 X - a x i s O C , S i g n e d D a t a , D i s a b l e d / P C M

0010000000000011 X - a x i s O C , S i g n e d D a t a , A R M E n a b l e d

0011000000000100 X-axis Raw, Unsigned Data, Disabled/

0110000000000001 Y - a x i s O C , S i g n e d D a t a , D i s a b l e d / P C M

0110000000000010 Y - a x i s O C , S i g n e d D a t a , A R M E n a b l e d

0111000000000101 Y-axis Raw, Unsigned Data, Disabled/

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4.2 SPI Response Format

Table 30. SPI Response Message Summary

0 Transferred Accel Data is Offset Cancelled Data

1 Transferred Accel Data is Raw Data

0 X-axis Acceleration Data Response

1 Y-axis Acceleration Data Response

10 ST Active, ΣΔ/Offset Over range

000 P 1 1 SD = 1: 00 0000 0000

4.3 Acceleration Data Transfers

data requested, as shown in Table 31. impacts the output data. The requested configuration is compared against the data programmed in the writable register array. Details are shown in Table 32. acceleration data request command must be an odd number.

• The DEVINIT bit in the D EVSTAT register is not set
• The DEVRES bit in the DEVSTAT register is not set
• The IDE bit in the DEVSTAT register is not set (Reference Section 4.5.5)
• No SPI Error is detected (Reference Section 4.5.1)
• No MISO Error is detected (Reference Section 4.5.2)
• No Acceleration Data Request Mismat ch failure is detected (Reference Section 4.5.3.1)
• No Self-test Error is present (reference Section 4.5.5.2) If the above conditions are met, MMA68xx responds with a “valid acceleration data request” response as shown in Table 30. Otherwise, MMA68xx responds as specified in Section 4.5.

4.4 Register Access Operations

by the Access Selection bit (AX) of the command message. operation must be an odd number. Table 31. Acceleration Data Request Table 32. Acceleration Data Request Configuration Information

0 Register Read

1 Register Write

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4.4.1 Register Write Request

written. Writable registers are defined in Table 3.

• No SPI Error is detected (Reference Section 4.5.1)
• No MISO Error is detected (Reference Section 4.5.2)
• The ENDINIT bit is cleared (Reference Section 3.1.6.2) – This applies to all registers with the exception of the DEVCTL register
• No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, MMA68xx responds to the register write request as shown in Table 30. Otherwise, MMA68xx Responds as specified in Section 4.5. Register write operations do not occur internally until the transfer during which they are requested has been completed. In the event that a SPI Error is detected during a register write transfer, the write operation is not completed.

4.4.2 Register Read Request

logic ’0’. Readable registers are defined in Table 3.

• No SPI Error is detected (Reference Section 4.5.1)
• No MISO Error is detected (Reference Section 4.5.2)
• No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, MMA68xx responds to the register read request as shown in Table 30. Otherwise, MMA68xx responds as specified in Section 4.5.

4.5 Exception Handling

The following sections describe the conditions for each detectable exception, and the MMA68xx response for each exception. In the event that multiple exceptions exist, the exception response is determined by the priority listed in Table 33. Table 33. SPI Error Response Priority

1 SPI Error Error Response No Update No Effect

2 SPI MISO Error Error Response No Update No Effect

3 Invalid Request Error Response No Update No Effect

4 DEVINIT Bit Set Error Response No Update Disabled

5 DEVRES Error Error Response No Update Disabled

6 CRC Error Error Response No Update No Effect

7 Self-test Error Error Response No Update No Effect

8 Offset Monitor Over Range No Effect No Effect No Effect

4.5.1 SPI Error

• SCLK is high when CS is asserted the number of SCLK rising edges detected while CS is asserted is not equal to 16
• SCLK is high when CS is negated
• Command message parity error (MOSI)
• Bit 15 of Acceleration Data Request is not equal to ‘0’
• Bits 3 through 11 of an Acceleration Request are not equal to ‘0’
• Bits 0 through 7 of a Register Read Request are not equal to ‘0’ MMA68xx responds to a SPI error with a “SPI Error” response as shown in Table 30. This applies to both acceleration data request SPI errors, and Register Access SPI errors. The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error.

4.5.2 SPI Data Output Verification Error

Fault is detected and the MISOERR flag in the DEVSTAT register is set. affected by the MISO mismatch failure. message. If the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared. DEVSTAT register is completed. Figure 35. SPI Data Output Verification

4.5.3 Invalid Requests

4.5.3.1 Acceleration Data Request Mismatch Failure

is not affected by the “Acceleration Data Request Mismatch” error. Register operations will be executed as specified in Section 4.4.

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4.5.3.2 Invalid Register Request

The following conditions result in an “Invalid Register Request” error:

• An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1, Table 3).
• An attempt is made to write to a register whil e the ENDINIT bit in the DEVCFG register is set – This applies to all registers with the exception of the DEVCTL register
• An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1, Table 3). MMA68xx responds to an “Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 30.

4.5.4 Device Reset Indications

If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 3.1.10, MMA68xx will respond to acceleration data requests with an “Internal Error Present” response until the bits are cleared in the DEVSTAT register. The DEVINIT bit is cleared automatically when device initialization is complete (Reference tOP in Section 2.6). The DEVRES bit is cleared on a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if the DEVINIT or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set.

4.5.5 Internal Error

The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register:

• OTP CRC Failure
• Writable Register CRC Failure
• Self-test Error
• Invalid internal logic states

4.5.5.1 CRC Error

If the IDE bit is set in the DEVSTAT register due to an OTP Shadow Register or Writable Register CRC failure as described in Section 3.2, MMA68xx will respond to acceleration data requests with an “Internal Error Present” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a CRC Error is detected. The PCM output is not affected by the CRC error. If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register. If the CRC error is in the OTP shadow register array, the error cannot be cleared. Register operations will be executed as specified in Section 4.4.

4.5.5.2 Self-test Error

If the IDE bit is set in the DEVSTAT register due to a Self-test activation failure, MMA68xx will respond to acceleration data requests with a “Self-test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a Self-test Error is detected. The PCM output is not affected by the Self - test Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal failure is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set. Register operations will be executed as specified in Section 4.4.

4.5.6 Offset Monitor Over Range

If an offset monitor over range is present as described in Section 3.8.5, MMA68xx will respond to an acceleration request for the corresponding axis with a “Valid Acceleration Data Request” response, but the Status bits (S[1:0]) will be set to ‘10’. The arming function will be updated on Acceleration Data Request commands even if an Offset Monitor Over Range is detected. Once the over range condition is removed, MMA68xx will respond to acceleration requests with a “Valid Acceleration Data Request” response with the Status bits (S[1:0]) set to ’10’ on the next SPI transfer, and a “Valid Acceleration Data Request” response with normal status on subsequent SPI transfers. The OFFSET_X or OFFSET_Y bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs. The PCM output is not affected by the offset monitor over range condition. Register operations will be executed as specified in Section 4.4.

transfers. The SDOV bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs. The PCM output is not affected by the ΣΔ over range condition. Register operations will be executed as specified in Section 4.4.

4.6 Initialization SPI Response

function will not be updated on Acceleration Data Request commands until the DEVRES bit in the DEVSTAT register is cleared.

4.7 Acceleration Data Representation

some nominal acceleration values are shown in the following table. Table 34. Nominal Acceleration Data Values

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relevant parameters are specified in Section 2.4. Figure 36. Acceleration Data Output Vs. Acceleration Input

5 Package

5.1 Case Outline Drawing

Reference NXP Case Outline Drawing # 98ASA00690D for the MMA68xxBKC part numbers. Reference NXP Case Outline Drawing # 98ASA00090D for the MMA68xxBKT part numbers.

5.2 Recommended Footprint

6 Revision History

Table 35. Revision History 4 12/2011 • Updated ordering table to include MMA6825BKW device options.  Removed “For user register...” comment on page 1 under ordering table.  Electrical Characteristics: Removed “QR2” suffix from device numbers lines 56 through 61. Added 100g (MMA6825) option.  Updated equation in section 3.6, Self-test Interface. 6 10/2014  Changed device numbers in ordering table for location code changes.  Updated Part Marking Diagram.  Changed application note reference from AN3111 to AN1902.  Added additional package for C suffix device options. 7 01/2016  Changed format to new corporate style.

Document Number: MMA68xx Rev. 7 Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: NXP.com/ salestermsandconditions. How to Reach Us: Home Page: NXP .com Web Support: NXP .com/support NXP , the NXP logo, Freescale, the Freescale logo, and SafeAssure are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2016 NXP B.V.