MMA6700EG FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • XY-axis of sensitivity in one device
  • 10- or 11-bit digital data output
  • ±3.5 g or ±5 g full-scale range per axis - MMA6700EG: ±3.5 g (11-bit data sensitivity = 3.43 mg/digit typical at 25º C) - MMA6701EG: ±5 g (11-bit data sensitivity = 4.91 mg/digit typical at 25ºC)
  • SPI-compatible serial interface
  • Bidirectional internal self-test
  • On-chip temperature sensor and voltage regulator
  • Support for signed or unsigned output data
  • Selection of integrated signal conditioning low-pass filters
  • Capture/hold input for system-wide synchronization support
  • 3.3 V or 5 V single supply operation
  • Ratiometric analog voltage output
  • Traceability through programmable registers, 3 8-bit.
  • Customer-assigned one-time-programmable Registers (2 8-bit Registration)
  • Minimal external component requirements
  • Wide operating temperature r ange from -40ºC to +125ºC
  • 20-pin SOIC wide-body RoHS-compliant package
  • Minimum external components, 4 capacitors Typical Applications
  • With a +3.5 g or +5 g full scale range, the newly designed, high accuracy sensor enables electronic stability control (ESC) designers to accommodate higher original signal noise level without sacrificing resolution.
  • Tilt Measurement

ORDERING INFORMATION

Device Temp. Range Case No. Package MMA6700EGR2 – 40 to +125°C 475A-02 SOIC-20, Tape and Reel MMA6700AEGR2 – 40 to +125°C 475A-02 SOIC-20, Tape and Reel MMA6701EGR2 – 40 to +125°C 475A-02 SOIC-20, Tape and Reel MMA6701AEGR2 – 40 to +125°C 475A-02 SOIC-20, Tape and Reel MMA6700EG MMA6701EG DUAL AXIS LOW g INERTIAL SENSOR EG SUFFIX (Pb-free) 20-LEAD SOIC CASE 475A-02 PIN CONNECTIONS N/C VSS N/C VCC XOUT N/C VPP/TEST VSSA CAP/HOLD SCLK CREGA 20-PIN SOIC PACKAGE Y OUT DIN CREG CS/RESET DOUT CREF CREF CREGA N/C N/C: NO INTERNAL CONNECTION X = 0g Y = 1g X = 0g Y = -1g X = 1g Y = 0g X = -1g Y = 0g PRELIMINARY

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Figure 1. Block Diagram

Supply Voltage VCC -0.3 to 7.0 Vdc CREG, CREGA , VREF VREG -0.3 to 3.0 Vdc VPP/TEST VPP -0.3 to 11.0 Vdc SCLK, CS, DIN/ST,CAP/HOLD VIN -0.3 to VCC + 0.3 Vdc DOUT/STATUS (high impedance state) VOUT -0.3 to VCC + 0.3 Vdc XOUT,YOUT (DACEN=0) VDAC -0.3 to VCC + 0.3 Vdc Current Drain Per Pin Excluding VCC and VSS I 10 mAmps Powered Shock (six sides, 0.5 ms duration) gpms +1500 g Unpowered Shock (six sides, 0.5 ms duration) gshock +2000 g Drop Shock (to concrete surface hdrop 1.2 m Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM VESD VESD VESD +2000 +500 +200 V V V Storage Temperature Range Tstg -40°C to +125°C °C PRELIMINARY

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PERFORMANCE CHARACTERISTICS Parameter Symbol Min Typ MAX UNITS Supply Voltage Standard Operating Voltage, 3.3 V Standard Operating Voltage, 5V VCC VCC VL +3.15 +4.75 +3.3 +5.0 VH +3.45 +5.25 V V Operating Temperature Range TA TL -40 - TH +125 °C Supply Current Standard Operating Voltage, 5.0 V (Digital with Analog Enabled) Idd - - +9.5 mAmp Programming Voltage Applied to VPP/TEST Programming Current Applied to VPP/TEST IPP - - 160 mAmp Test Mode Activation Voltage Applied to VPP/TEST VTEST +6.5 +7.2 +7.5 V Measurement Range, XY axis g -3.5 - +3.5 g Digital Sensitivity (DOUT) SENS 3.43 mg/digit Analog Sensitivity (XOUT, YOUT) Ratiometric to VCC SENS 115 mV/V/g Sensitivity Error (DOUT) TA = +25°C SENS SENS SENS -3.0 -4.0 -6.0 +3.0 +4.0 +6.0 Offset at 0g, SPI. 11-Bit unsigned data Analog Output DOUT AOUT 1024 0.5VCC - Digit V Offset Error at 0g, SPI, 11-Bit Unsigned Data TA = +25°C DOUT DOUT -15 -22 +15 +22 Digit Digit Offset Error at 0g, analog output TA = +25°C AOUT AOUT Digit Digit DSP Low-Pass Filter (2nd or 4th Order Selectable) Filter Option $00, $13 Filter Option $01, $14 Filter Option $03, $16 Filter Option $02, $15 Filter Option $04, $17 Filter Option $06, $19 Filter Option $05, $18 Filter Option $07 Filter Option $1A fC(LPF) fC(LPF) fC(LPF) fC(LPF) fC(LPF) fC(LPF) fC(LPF) fC(LPF) fC(LPF) 8.4 12.4 41.9 47.5 62.8 66.5 83.9 134 8.8 13.1 44.1 50.0 66.1 70.0 88.3 100 141 9.2 13.8 46.3 52.5 69.4 73.5 92.7 105 148 Hz Hz Hz Hz Hz Hz Hz Hz Hz Cross- Axis Sensitivity -4.0 - +4.0 % SPI Clock Rate tSCLK 8.33 - - MHz Noise (1Hz – 1kHz) nSD - - 140 µg/Hz Output Loading (DOUT/STATUS) Load Resistance Load Capacitance ZOUT COUT k pF PRELIMINARY

supply rail filter capacitor condition, which puts the device into reset should this fault occur. Figure 2. Recommended External Component Configuration

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