MMA6255KEGR2

MMA6222KEG FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Available in ±20/20g, ±50/50g, or ±100/100g versions. Additional g-ranges between 20 and 100g may be available upon request
• Full-scale range is independently specified for each axis
• 400 Hz low-pass filter, 0.1 Hz high-pass filter, 4-pole, 16 μs sample time, additional filter options are available
• Ratiometric analog voltage output
• 10-bit digital signed data output
• SPI-compatible serial interface
• Capture/hold input for system-wide synchronization support
• 3.3 or 5 V single supply operation
• On-chip temperature sensor and voltage regulator
• Bidirectional internal self-test
• Minimal external component requirements
• Pb-free 20-pin SOIC package
• Qualified AEC-Q100, Rev. F Grade 2 (-40 °C/ +105°C) Typical Applications
• Crash Detection (Airbag)
• Impact and vibration monitoring
• Shock Detection

ORDERING INFORMATION

Device Name X-Axis, g-Level Y-Axis, g-Level Temperature Range Package Packaging MMA6222EG 20 20 -40 to +105°C 475A-02 Tubes MMA6222EGR2 20 20 -40 to +105°C 475A-02 Tape & Reel MMA6222KEG* 20 20 -40 to +105°C 475A-02 Tubes MMA6222KEGR2* 20 20 -40 to +105°C 475A-02 Tape & Reel MMA6255EG 50 50 -40 to +105°C 475A-02 Tubes MMA6255EGR2 50 50 -40 to +105°C 475A-02 Tape & Reel MMA6255KEG* 50 50 -40 to +105°C 475A-02 Tubes MMA6255KEGR2* 50 50 -40 to +105°C 475A-02 Tape & Reel MMA621010EG 100 100 -40 to +105°C 475A-02 Tubes MMA621010EGR2 100 100 -40 to +105°C 475A-02 Tape & Reel MMA621010KEG* 100 100 -40 to +105°C 475A-02 Tubes MMA621010KEGR2* 100 100 -40 to +105°C 475A-02 Tape & Reel *Part number sourced from a different facility. MMA6222KEG MMA6255KEG MMA621010KEG 2-AXIS SPI-COMPATIBLE ACCELEROMETER KEG SUFFIX (Pb-free) 20-LEAD SOIC CASE 475A-02 PIN CONNECTIONS N/C VSS N/C VCC XOUT N/C VPP VSSA CAP/HOLD SCLK CREGA 20-PIN SOIC PACKAGE Y OUT DIN CREG CS/RESET DOUT CREF CREF CREGA N/C N/C: NO INTERNAL CONNECTION

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Figure 1-1 Simplified Airbag Application Diagram

1.1 INTRODUCTION

The MMA62XXKEG is intended for applications which utilize serial communications as the primary data transfer mechanism. In addition, an analog output with lower accuracy is available. Device serial number, acceleration range, filter characteristics and status information are available along with acceleration data via the SPI interface. A pair of digital-to-analog converters is enabled to provide ratiometric voltage outputs in addition to the digital acceleration value accessible via the SPI. 1 μF100 nF 1 μF VCC MMA62XXKEG VCC CREG CREGA VSS VPP/TEST CS SCLK DI DO CS_A SCLK1 MOSI1 Main MCU MISO1 CS_D SCLK2 MOSI2 MISO2 CS SCLK DI DO Deployment IC VSSA CREF 100 nF XOUT YOUT ADC Safing Sensor(s) / Comparator Filter DEPLOY_EN1 DEPLOY_EN2 Note: If one axis of the MMA62XXKEG sensor is expected to be used as a confirmation of the other axis, Freescale recommends that MMA62XXKEG used in conjunction with an additional sensing/safing device for each axis.

1.2 BLOCK DIAGRAM

A block diagram illustrating the major components of the design is shown in Figure 1-2. Figure 1-2 MMA62XXKEG Block Diagram Figure 1-3 MMA62XXKEG DSP Block Diagram NOTE: Models of signal chain are available upon request. SPI VCC VSS DIN DOUT SCLK CS SELF-TEST CREG CREF VPP XOUT INTERFACE TEMP. SENSOR SD CONVERTER VOLTAGE REGULATOR g-CELL (Y) g-CELL (X) CONTROL LOGIC UNIT DATA ARRAY PROGRAMMABLE SD CONVERTER CLOCK INTERNAL MONITOR CREGA CAP/HOLD DAC YOUT Y IN X IN DIGITAL Y OUT X OUT DSP TEMP (SEE FIGURE 1-2) OUT CONTROL IN STATUS OUT DAC CREF CREGA VSSA CLOCK PRIMARY OSCILLATOR REFERENCE OSCILLATOR SINC FILTER SINC FILTER OFFSET, Y IN HIGH-PASS FILTER LOW-PASS FILTER TO X DAC GAIN, LINEARITY ADJUST OUTPUT SCALING OUTPUT SCALING DSP CONTROL TO Y DAC DIGITAL OUT X IN TEMP CONTROL IN OFFSET MONITOR OUT

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1.3 PIN FUNCTIONS

The pinout for the MMA62XXKEG device is illustrated in Figure 1-4. Pin functions are described below. When self-test is active, the output becomes more positive in both axes if ST1 is cleared, or more negative in both axes if ST1 is set, as described in Section 3.1.1. Figure 1-4 MMA62XXKEG Pinout N/C VSS N/C VCC XOUT N/C VPP VSSA CAP/HOLD SCLK CREGA 20-PIN SOIC PACKAGE Y OUT DIN CREG CS/RESET DOUT CREF CREF CREGA N/C N/C: NO INTERNAL CONNECTION X: 0g Y: -1g X: +1g Y: 0g X: 0g Y: +1g X: -1g Y: 0g Response to static orientation within 1g field. TO CENTER OF GRAVITATION FIELD

1.4 PIN FUNCTION DESCRIPTIONS

1.4.1 V CC

This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best performance. An external bypass capacitor between this pin and VSS is required, as described in Section 1.5.

1.4.2 V SS

This pin is the power supply return node for the digital circuitry on the MMA62XXKEG device.

1.4.3 V SSA

This pin is the power supply return node for analog circuitry on the MMA62XXKEG device. An external bypass capacitor between this pin and VCC is required, as described in Section 1.5.

1.4.4 C REG

This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between this pin and VSS, as described in Section 1.5.

1.4.5 C REGA

These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must be connected between these pins and VSSA, as described in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5.

1.4.6 C REF

These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external filter capacitors must be connected between these pins and VSSA, as described shown in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5.

1.4.7 VPP

This pin should be tied directly to VSS.

1.4.8 SCLK

This input pin provides the serial clock to the SPI port. The state of this pin is also used as a qualifier for externally-controlled reset. An internal pull-down device is connected to this pin. This input may be left unconnected unless it is desired to initiate de- vice reset as described in Section 1.4.9.

1.4.9 CS /RESET

This pin provides two functions. When the SPI is enabled, this pin functions as the chip select input for the SPI port. The state of the DIN pin during low-to-high transitions of SCLK is latched internally and DOUT is enabled when CS is at a logic low level. This pin may also be used to initiate a hardware reset. If CS is held low and SCLK is held high for 512 μs, the internal reset signal is asserted. An internal pull-up device is connected to this pin.

1.4.10 D OUT

This pin functions as the serial data output for the SPI port. Immediately following device reset, D OUT is placed in a high impedance state for approximately 800 μs. At the end of this time, DOUT is driven high and a 3ms stabilization delay required by the internal circuitry begins. Reset is reported by the device so the system can be aware of potential difficulties if unexpected resets occur.

1.4.11 D IN

This pin functions as the serial data input to the SPI.

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1.4.12 CAP /HOLD

When this input pin is low, the SPI acceleration result registers are updated by the DSP whenever a data sample becomes available. Upon a low-to-high transition of CAP/HOLD, the contents of the acceleration result registers are frozen. The result registers will not be updated so long as this pin remains at a logic ‘1’ level. This pin may be tied directly to VSS if the hold function is not desired.

1.4.13 X OUT, YOUT

Two Digital-to-Analog Converters (DACs) translate output of the DSP block into voltage levels proportional to the magnitude of the numerical result and ratiometric to VCC. The DAC outputs have an inherent accuracy of about ±12%.

1.5 EXTERNAL COMPONENTS

The connections illustrated below are recommended. Careful printed wiring board layout and component placement is essential for best performance. Low ESR capacitors must be connected to CREG and CREGA pins for the best performance. A grounded land area with solder mask should be placed under the package for improved shielding of the device from external effects. If a land area is not provided, no signals should be routed beneath the package. See Figure 1-1.

SECTION 2 PERFORMANCE SPECIFICATION

2.1 MAXIMUM RATINGS

Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep input and output voltages within the range VSS ≤ V ≤ VCC. Notes: 1. Verified by characterizati on, not tested in production.

2.2 OPERATING RANGE

The operating ratings are the limits normally expected in the application and define the range of operation. Notes: 1. Characterized at all values of V L and VH. Production test is conducted at typical voltage unless otherwise noted. 2. Parameters tested 100% at final test. Ref Rating Symbol Value Unit 1 Supply Voltage VCC -0.3 to +7 V (1) 2 CREG, CREGA, CREF VREG -0.3 to +3 V (1) 3 VPP VREG -0.3 to +11 V (1) 4 SCLK, CS, DIN, CAP/HOLD VIN -0.3 to VCC + 0.3 V (1) 5 DOUT (high impedance state) VIN -0.3 to VCC + 0.3 V (1)

6 Current Drain per Pin Excluding VCC and VSS I 10 mA (1)

7 Acceleration (without hitting internal g-cell stops) gmax ±800 g (1)

8 Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g (1) 9 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (1) 10 Drop Shock (to concrete surface) hDROP 1.2 m (1) Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) VESD VESD VESD ±2000 ±500 ±200 V V V (1) (1) (1)

14 Storage Temperature Range Tstg -40 to +125 °C (1)

Ref Characteristic Symbol Min Typ Max Units Supply Voltage Standard Operating Voltage, 3.3V operating range Standard Operating Voltage, 5V operating range VCC VCC VL +3.15 +4.75 +3.3 +5.0 VH +3.45 +5.25 V V (1) (1) Operating Temperature Range TA TL -40 ⎯ TH +105 C (2)

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2.3 ELECTRICAL CHARACTERISTICS

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 1. Parameters tested 100% at final test. 2. Verified by characterization, not tested in production. 3. Tested at V CC = VL and VCC = VH. 4. Power supply ripple at frequencies greater than 900 kH z should be minimized to the greatest extent possible. 5. Devices are trimmed at 100 Hz with 1000 Hz low pass filter selected. (#) Indicates a FSL significant parameter (CPK > 1.33). (*) Indicates a FSL critical parameter (CPK > 1.67). Ref Characteristic Symbol Min Typ Max Units Supply Current Drain VCC = 5.25 V, tS = 16 μs # IDD ⎯ ⎯ 9.5 mA (2) Power-On Recovery Threshold (See Figure 2-1) VCC CREG CREGA CREF Power-On Reset Threshold (See Figure 2-1) VCC CREG CREGA CREF Hysteresis (VPOR_N - VPOR_A, See Figure 2-1) VCC CREG CREGA CREF VPOR_N VPOR_N VPOR_N VPOR_N VPOR_A VPOR_A VPOR_A VPOR_A VHYST VHYST VHYST VHYST 2.77 1.80 2.18 1.11 2.77 1.80 2.18 1.11 3.15 2.32 2.50 1.29 2.95 2.10 2.31 1.19 388 300 261 150 V V V V V V V V mV mV mV mV (2) (2) (2) (2) (2) (2) (2) (2) 32 Minimum Functional Voltage (See Figure 2-1) VDACU ⎯ ⎯ 2.0 V (2) Internally Regulated Voltages CREG CREGA (3) CREF VDD V2.5 VREF 2.42 2.42 1.20 2.50 2.50 1.25 2.58 2.58 1.29 V V V (1) (1) (1) External Filter Capacitor (CREG, CREGA) Value ESR (including interconnect resistance) CREG ESR 800 1000 200 nF mΩ (2) (2) Power Supply Coupling (4) Digital output Analog output ⎯ ⎯ 0.004 digit/mv (2) (2) See Figure 2-2 Digital Sensitivity (DOUT) 20 g Range 35 g Range 50 g Range 100 g Range Sensitivity Error T A = 25°C -40°C ≤ TA ≤ 105°C SENS SENS SENS SENS ΔSENS ΔSENS 0.04097 0.0717 0.1024 0.2048 g/digit g/digit g/digit g/digit (1)(5) (1)(5) (1)(5) (1)(5) (1)(5) (1)(5)

2.3 ELECTRICAL CHARACTERISTICS (CONTINUED)

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 1. Parameters tested 100% at final test. 2. Verified by characterizati on, not tested in production. 5. Functionality verified 100% via scan. (*) Indicates a FSL critical parameter (CPK > 1.67). Ref Characteristic Symbol Min Typ Max Units Analog Sensitivity (XOUT, YOUT) 20 g Range 35 g Range 50 g Range 100 g Range Sensitivity Error T A = 25°C -40°C ≤ TA ≤ 105°C ASENS ASENS ASENS ASENS ΔSENS ΔSENS -16 -16 23.4 13.40 9.37 4.68. +16 +16 mV/V/g mV/V/g mV/V/g mV/V/g (1) (1) (1) (1) (1) (1) Offset at 0 g (High-pass filter disabled) 10-bits, signed Analog output trimmed for digital operation DOUT AOUT -40 0.44 × VCC 0.5 × VCC +40 0.56 × VCC digit V (1) (1) Range of Output (DOUT, 10 bits, signed) Normal Positive Acceleration Overflow Code Positive Acceleration Overrange Code Negative Acceleration Underrange Code Negative Acceleration Underlfow Code Unused Code Unused Code RANGE OFS ORS URS UFS UNUSED UNUSED -509 510 509 -510 -511 511 -512 508 digit digit digit digit digit digit digit (5) (5) (5) (5) (5) (5) (5) Output value on overrange 20 g Range 35 g Range 50 g Range 100 g Range Output value on underrange 20 g Range 35 g Range 50 g Range 100 g Range gOVER gOVER gOVER gOVER gUNDER gUNDER gUNDER gUNDER +20.0 +35.0 +50.0 +100.1 -20.1 -35.1 -50.0 -100.1 +20.9 +36.6 +52.1 +104.3 -20.9 -36.6 -52.2 -104.5 +22.1 +38.7 +55.3 +110.5 -22.2 -38.8 -55.4 -110.7 g g g g g g g g (2) (2) Maximum acceleration without saturation of internal circuitry All ranges gSAT -200 — +200 g (2)

70 Nonlinearity NLOUT -1 — 1 % FSR (2)

71 Noise (1Hz-1kHz) nSD — — 1.1 mg/√Hz (2) Positive Self Test Output Change (DOUT, digital) TA = 25°C -40°C ≤ TA ≤ 105°C (XOUT, YOUT, analog) TA = 25°C -40°C ≤ TA ≤ 105°C ΔST ΔST ΔST ΔST digit digit % FS % FS (1) (1) (1) (1)

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VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 1. Parameters tested 100% at final test. 2. Verified by characterization, not tested in production. 6. Parameters tested 100% at unit probe. Ref Characteristic Symbol Min Typ Max Units Negative Self Test Output Change (DOUT, digital) TA = 25°C -40°C ≤ TA ≤ 105°C (XOUT, YOUT, analog) TA = 25°C -40°C ≤ TA ≤ 105°C ΔST ΔST ΔST ΔST -78 -82 -18 -18 -72 -72 -66 -62 -10 -10 digit digit % FS % FS (6) (6) (6) (6) Cross-Axis Sensitivity VZX VYX VZY VXY VZX VYX VZY VXY (6) (6) (6) (6) DAC Characteristics (XOUT, YOUT) Minimum Output Level, IOUT = -200 μA Maximum Output Level, IOUT = 200 μA Offset Error Gain Error Differential Nonlinearity Integral Nonlinearity T A = 25°C -40°C ≤ TA ≤ 105°C AVLOW AVHIGH OFST GERR DNL INL INL VCC - 0.25 -0.2 -0.3 -3.5 0.25 +0.2 +0.3 +3.5 V V %FSR %FSR digit digit digit (2) (2) (2) (2) (2) (2) (6) Output High Voltage DOUT (ILoad = -100 μA) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOH VOH 3.25 3.75 V V (2) (2) Output Low Voltage DOUT, (ILoad = 100 μA) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOL VOL 0.4 0.4 V V (2) (2) Output Loading (DOUT) Load Resistance Load Capacitance ZOUT COUT kΩ pF (6) (6) Output Loading (XOUT, YOUT) Load Resistance Load Capacitance ZOUT COUT kΩ pF (6) (6) 100 Input High Voltage CS/RESET, SCLK, DIN/ST, CAP/HOLD 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIH VIH 1.5 2.5 V V (2) (2) 101 102 Input Low Voltage CS/RESET, SCLK, DIN/ST, CAP/HOLD 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIL VIL 0.85 1.0 V V (2) (2) 103 104 105 Input Current High (at VIH) SCLK, DIN, CAP/HOLD VPP/TEST (internal pulldown resistor) Low (at VIL) CS/RESET IIH RIN IIL -30 190 -50 270 -260 350 260 μA kΩ μA (2) (2) (2)

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2.4 CONTROL TIMING

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 1. Functionality verified 100% via scan. Ti ming characteristic is directly determined by internal oscillator frequency. 2. Verified by characterizati on, not tested in production. 3. Parameters tested 100% at final test. 4. Parameters tested 100% at unit probe. 5. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. 6. Cutoff frequencies shown are -4dB referenced to 0 Hz response, to correspond with previous specifications. Ref Characteristic Symbol Min Typ Max Units 106 107 DSP Low-Pass Filter (5) Cutoff frequency (6) DSP Low-Pass Filter Cutoff frequency (-3dB, referenced to 0 Hz) 380 335 400 353 420 371 Hz Hz (1) (1) 108 109 DSP High-Pass Filter Cutoff frequency Filter Order fC(HPF) OHPF 0.095 0.1 0.105 Hz (1) (1) 110 111 Power-On Recovery Time POR negated to CS low Power applied to XOUT, YOUT valid tOP tXY 840 μs ms (1) (2) 112 Internal Oscillator Frequency fOSC 3.8 4.0 4.2 MHz (3) 113 Clock Monitor Threshold fMON 3.6 — 4.4 MHz (1)

114 Chip Select to Internal Reset (See Figure 2-3) tCSRES 486 512 538 μs (1)

Serial Interface Timing (See Figure 2-4) Clock period CS asserted to SCLK high Data setup time Data hold time SCLK low to data out SCLK high to CS negated CS negated to CS asserted tSCLK tCSCLK tDC tCDIN tCDOUT tCHCSH tCSN 120 526 ns ns ns ns ns ns ns (1) (1) (1) (1) (1) (1) (1) 122 DAC Low-Pass Filter Cutoff Frequency fC 5 10 20 kHz (4)

123 Sensing Element Rolloff Frequency (-3 dB) BWGCELL — 3 — kHz (2)

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Figure 2-1 Power-Up Timing Figure 2-2 Power Supply Coupling - DAC Outputs VCC tXY XOUT/YOUT 5.5V VPOR_N VPOR_A VDACU DAC OUTPUT UNCERTAIN POR

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SECTION 3 INTERNAL MODULES

3.1 ONE-TIME PROGRAMMABLE DATA ARRAY

A 400-bit programmable data array allows each device to be customized. The array interface incorporates parity circuitry for fault detection along with a locking mechanism to prevent unintended changes. Portions of the array are reserved for factory-pro- grammed trim values. Customer accessible data stored in the array are shown in the table below. Addresses $00 - $0D are associated with the programmable data array. A writable register at address $0E is provided for device control operations. Two read-only registers at addresses $0F and $10 provide status information. Unused bits within the data array are always read as ‘0’ values. Unprogrammed OTP bits are also read as ‘0’ values. Type codes F: Factory programmed OTP location R: Read-only register R/W: Read/write register N/A: Not applicable 3.1.1 ‘DEVICE CONTROL REGISTER (DEVCTL) A read-write register at address $0E supports a number of device control operations as described below. Reserved bits within DEVCTL are always read as logic ‘0’ values. Table 3-1 Customer Accessible Data Location Bit Function Type Address Register 7 6 5 4 3 2 1 0 $00 SN0 SN[7] SN[6] SN[5] SN[4] SN[3] SN[2] SN[1] SN[0] F $01 SN1 SN[15] SN[14] SN[13] SN[12] SN[11] SN[10] SN[9] SN[8] $02 SN2 SN[23] SN[22] SN[21] SN[20] SN[19] SN[18] SN[17] SN[16] $03 SN3 SN[31] SN[30] SN[29] SN[28] SN[27] SN[26] SN[25] SN[24] $04 DEVCFG0 Factory Programmed $05 DEVCFG1 Factory Programmed $06 DEVCFG2 Factory Programmed $07 DEVCFG3 Factory Programmed $08 DEVCFG4 Factory Programmed $09 DEVCFG5 LOCK2 PAR2 COMP1 COMP0 SPARE DACEN AD3 AD2 $0A AXCFG_X RNG_X[2] RNG_X[1] RNG_X[0] LPF_X[4] LPF_X[3] LPF_X[2] LPF_X[1] LPF_X[0] $0B AXCFG_Y RNG_Y[2] RNG_Y[1] RNG_Y[0] LPF_Y[4] LPF_Y[3] LPF_Y[2] LPF_Y[1] LPF_Y[0] $0C Unused N/A $0E DEVCTL RES_1 RES_0 CE Reserved HPFB YINV ST1 ST0 R/W $0D DSPCFG SPARE SPARE INTERP OVLD SD HPFD HPFSEL OFMON F $0F TEMP TEMP[7] TEMP[6] TEMP[5] TEMP[4] TEMP[3] TEMP[2] TEMP[1] TEMP[0] R$10 DEVSTAT IDE OSCF DEVINIT TF HPF OFF_Y OFF_X DEVRES $11 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0] Table 3-2 Device Control Register Address Register Bit 7 6 5 4 3 2 1 0 $0E DEVCTL RES1 RES0 CE Reserved HPFB YINV ST1 ST0

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3.1.1.1 Reset Control (RES_1, RES_0)

A specific series of three write operations involving these two bits will cause the internal digital circuitry to be reset. The state of the remaining bits in the DEVCTL register do not affect the reset sequence, however any write operation involving this register in which both RES_1 and RES_0 are cleared will terminate the sequence. To reset the internal digital circuitry, the following register write operations must be performed in the order shown: 1. Set RES1. RES0 must remain cleared. 2. Set RES1 and RES0. 3. Clear RES1 and set RES0. RES1 and RES0 are always read as logic ‘0’ values. After reset sequence has been completed DEVCTL register will read 0X00. It should be noted that after a reset or power-cycle sequence is completed the DEVCTL register reset to the value 0X00.

3.1.1.2 Clear Error (CE)

Setting this bit to a logic ‘1’ state will clear transient error status conditions. It is necessary to either set this bit or perform a device reset if an error condition has been reported by the device before acceleration data transfer can be resumed. The device reset condition may be cleared only after device initialization has completed. Error conditions and classification are described in Section 4.2. The state of this bit is always read as logic ‘0’.

3.1.1.3 High-Pass Filter Bypass (HPFB)

Setting this bit will remove the high-pass filter from the signal chain within the DSP block. The state of this bit is indicated when DEVCTL is read. This bit is always cleared following reset. The state of the high-pass filter is frozen when this bit is at a logic ‘1’ level.

3.1.1.4 Self-Test Control (ST1, ST0)

Bidirectional self-test control is provided through manipulation of these bits. ST1 controls direction while ST0 enables and dis- ables the self-test circuitry. ST1 and ST0 are always cleared following internal reset. When ST0 is set, the high-pass filter is by- passed and the values within the high-pass filter are frozen. Both axes are affected simultaneously by the state of these bits. If the offset monitor is enabled, self-test activation in a single direction should be limited to less than 30 ms. The state of the ST0 bit is indicated as part of all acceleration results.

3.1.1.5 Y-Axis Signal Inversion Control (YINV)

This control function is provided as a means to verify operation of the two-channel multiplexor which alternately provides X-axis and Y-axis data to the DSP. An inverter block and multiplexor at the Y-axis input to the DSP are controlled by the YINV bit. Setting this bit when ST0 is set has the effect of changing the sign of acceleration in the Y-axis. Operation of the YINV bit is illustrated in Figure 3-1 below. Y-axis inversion may be selected only during self-test; the state of this bit has no effect when ST0 is cleared. Figure 3-1 Y-Axis Inversion Function DSP YINV ΣΔ CONVERTER SINC FILTERX ΣΔ CONVERTERY SINC FILTER ST0

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Self-test operations controlled by YINV along with ST1 and ST0 are summarized in the following table. NOTE: Offset correction is applied within the DSP, and is not affected by the state of the YINV bit. Conse- quently, inversion of the Y-axis signal may result in saturation of the Y-axis output value. Table 3-3 Self-Test Control Operations YINV ST1 ST0 Self-Test Operation X-Axis Y-Axis X X 0 Self Test Disabled, Y-Axis Signal Inversion Disabled 0 0 1 Positive Deflection 0 1 1 Negative Deflection 1 0 1 Positive Deflection Negative Deflection 1 1 1 Negative Deflection Positive Deflection

Freescale Semiconductor 17 Correct operation of the DSP input multiplexor may be confirmed by performing the operations shown in Figure 3-2. Figure 3-2 DSP Input Multiplexor Verification Flow Chart

3.1.2 Temperature Sensor Value (TEMP)

This read-only register contains a signed value which provides a relative temperature indication. The temperature sensor is un- calibrated and its output for a given temperature will vary from one device to the next. The value in this register increases with temperature.

3.1.3 Device Status Register (DEVSTAT)

This read-only register is accessible in all modes.

3.1.3.1 Internal Data Error Flag (IDE)

This flag will be set if a register data parity fault or a marginally programmed fuse is detected. Device reset is required to clear this fault condition. If a parity error is associated with the data stored in the fuse array, this fault condition cannot be cleared. This flag is disabled when the device is in test mode. Table 3-4 Temperature Sensor Value Register Location Bit Function Address Register 7 6 5 4 3 2 1 0 $0F TEMP TEMP[7] TEMP[6] TEMP[5] TEMP[4] TEMP[3] TEMP[2] TEMP[1] TEMP[0] Table 3-5 Device Status Register Location Bit Function Address Register 7 6 5 4 3 2 1 0 $10 DEVSTAT IDE OSCF DEVINIT TF HPF OFF_Y OFF_X DEVRES YINV = 0, ST1 = 0, ST0 = 1 READ ACCELERATION (R1) MULTIPLEXOR R1 > R2 Y N YINV = 0, ST1 = 1, ST0 = 1 READ ACCELERATION (R2) YINV = 1, ST1 = 0, ST0 = 1 READ ACCELERATION (R3) YINV = 1, ST1 = 1, ST0 = 1 READ ACCELERATION (R4) R3 ≤ R4 Y N VERIFICATION SUCCESSFUL MULTIPLEXOR VERIFICATION FAILED YINV = 0, ST1 = 0, ST0 = 1 READ ACCELERATION (R1) MULTIPLEXOR R1 > R2 Y N YINV = 0, ST1 = 1, ST0 = 1 READ ACCELERATION (R2) YINV = 1, ST1 = 0, ST0 = 1 READ ACCELERATION (R3) YINV = 1, ST1 = 1, ST0 = 1 READ ACCELERATION (R4) R3 ≥ R4 Y N VERIFICATION SUCCESSFUL MULTIPLEXOR VERIFICATION FAILED X-axis Y-axis

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3.1.3.2 Oscillator Fault Flag (OCSF)

This flag will be set if the primary oscillator and reference oscillator frequencies vary by an amount greater than the specified tolerance. In normal operating mode, an oscillator fault condition will result in DOUT being driven high when CS is asserted.

3.1.3.3 Device Initiali zation Flag (DEVINIT)

This flag is set during the interval between negation of internal reset and completion of device initialization. DEVINIT is cleared automatically.

3.1.3.4 Temperature Fault Flag (TF)

This flag is set if the value reported by the on-chip temperature sensor exceeds specified limits. TF may be cleared by writing a logic ‘1’ value to the CE bit in DEVCTL, provided that the fault condition is no longer detected.

3.1.3.5 High-Pass Filter Status (HPF)

This bit is set when a high-pass filter is present in the DSP signal chain when the HPFB bit has been set.

3.1.3.6 Y-Axis Offset Error Flag (OFF_Y)

3.1.3.7 X-Axis Offset Error Flag (OFF_X)

The offset error flags are set if the associated signal reaches the specified offset limit. These flags may be cleared by writing a logic ‘1’ value to the CE bit in DEVCTL. Offset faults are not reported for 1.5 seconds following reset.

3.1.3.8 Device Reset Flag (DEVRES)

This flag is set during device initialization. A logic ‘1’ must be written to the CE bit in the Device Control register (DEVCTL) to clear this bit.

3.1.4 Counter Register (COUNT)

This read-only register provides the value of a free-running 8-bit counter derived from the primary oscillator. A five-bit prescaler divides the 4 MHz primary oscillator frequency by 32. Thus, the value in the register increases by one count every 8 μs, and the counter rolls over every 2.048 ms. Table 3-6 Counter Register Location Bit Function Address Register 7 6 5 4 3 2 1 0 $11 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0]

Freescale Semiconductor 19 SECTION 4 SERIAL COMMUNICATIONS Digital data communication with MMA62XXKEG is completed through synchronous serial transfers via the SPI port. Conventional SPI protocol is employed, with MMA62XXKEG acting as a slave device observing CPOL = 0, CPHA = 0, MSB first. A number of data integrity features are incorporated into the transfer protocol.

4.1 SPI PROTOCOL

4.1.1 Overview

Each transfer is completed through a sequence of two operations, termed phases. During the first phase, the type of transfer and associated control information is transmitted from the SPI master to MMA62XXKEG. Data from MMA62XXKEG is transmitted during the second phase. Single-level queuing is employed as illustrated in Figure 4-1. Figure 4-1 Transfer Phase Detail Any activity on DIN or SCLK is ignored when CS is negated. Consequently, intermediate transfers involving other SPI devices may occur between Phase One and Phase Two. Figure 4-2 Single-Level Communications Queuing Detail SCLK DIN DOUT CS Phase One: Type and Control Phase Two: DataRequest Error Request Error only reported on first access following reset SCLK DIN DOUT CS T1P1 T2P1 T1P2 T2P2 T3P1 T3P2

20 Freescale Semiconductor

The first data transmitted by MMA62XXKEG following reset is the Request Error message shown below. This occurs because MMA62XXKEG transmits during Phase Two and there is no corresponding Phase One for the first transfer. Figure 4-3 Request Error Frame

4.1.2 Command Format

The following abbreviations are used in the following figures. Commands are transferred from the SPI master to MMA62XXKEG. Commands fall into three categories: acceleration data re- quests, register operations and device test. Acceleration data requests are initiated when bit 13 from the master is set to a logic ‘1’ state. Register operations and device test are when bit 13 is set to logic’0’ and are further distinguished by the states of bits 15 and 14.

4.1.3 Acceleration Data Transfers

Acceleration data requests are initiated when bit 15 from the master is set to a logic ‘0’ state and bit 13 is set to a logic ‘1’ state. The axis associated with the acceleration to be transferred is determined by DIN bit 14. Figure 4-4 Acceleration Command Format Bit Name Description Bit Address DIN DOUT A[4:0] Register address 12:8 12:8 D[9:0] 10-bit acceleration data N/A 9:0 Acc Acceleration data indicator 13 13 AXIS Axis specifier 14 14 P Parity N/A 12 S[1:0] Status N/A 11:10 SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00P01 1 1 000 00R E00 SCLK BIT DIN CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AXIS0 A c c XXXXXXXXXXXXX

Freescale Semiconductor 21 Acceleration data is returned as illustrated below. In addition to the acceleration value, the axis associated with the measurement is indicated in bit 13, while bits 11 and 10 provide status information. Figure 4-5 Acceleration Command Response Figure 4-6 Acceleration Command Response, Self-Test Active

4.1.4 AXIS Bit

Bit 13 indicates the axis associated with acceleration data, as shown below.

4.1.5 Status Bits

Data bits 11 and 10 convey additional information regarding the acceleration data being transmitted. If an error condition is indi- cated, bits D9 through D0 contain flags which further describe the nature of the error. The combination S1 = 0, S0 = 0 is never transmitted by MMA62XXKEG in response to an acceleration data command. Table 4-1 AXIS Bit Definitions AXIS Selected Axis 0 X 1 Y Table 4-2 STATUS Bit Definitions Status Bit Definition S1 S0 0 0 Not Applicable 0 1 Acceleration Data 1 0 Self-test Data 1 1 Error SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 AXIS P D 4D 3D 2D 1 D0D6 D50 S1 S0 D9 D8 D7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

22 Freescale Semiconductor

4.1.6 Acceleration Response Error Status

Several error conditions may be detected and reported in response to an acceleration data command. Figure 4-7 ND/HE Error Frame

4.1.6.1 ND - No Data Available

Bit 4 will be set to indicate a “No Data” condition if acceleration data is requested while the device is undergoing device initializa- tion following reset. To ensure that an unexpected device reset will always be detectable regardless of the interval at which the sensor is accessed, “No Data” status will be returned in response to the first acceleration data request following device initializa- tion.

4.1.6.2 HE - Hardware Error

A fault has been detected within the MMA62XXKEG device. Detectable fault conditions are listed below

• Device over-temperature
• Offset error
• Internal parity error Specific error conditions are indicated in the device status register. The contents of this register are returned in response to a device test operation, as described in Section 4.1.10. Oscillator fault status will be reported only if the internal oscillator is func- tional but frequency comparison between the primary and reference oscillators fails. If an oscillator fault condition exists, the de- vice will respond as described in Section 4.2.2.2.

4.1.6.3 CNC - Cond itions Not Correct

Acceleration data will not be provided when bit 15 of command is detected as logic ‘1’. The response to such requests is illus- trated below. Should a No Data Available or Hardware Error condition also exist, it will be reported as well. Figure 4-8 CNC Error Frame

4.1.7 Non-Acceleration Transfers

Three different types of non-acceleration transfers are supported; register write, register read and device test. Non-acceleration data transfers are initiated when bit 13 from the master is set to a logic ‘0’ state. The operation to be performed is indicated by bits 15 and 14. Table 4-3 Non-Acceleration Operations Bit 15 Bit 14 Operation 0 0 Unused 0 1 Register Write 1 0 Register Read 1 1 Device Test SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0A X I SP N D01 1 0 000 0HE 00 SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 AXIS P01 1 0 000 010ND HE

Freescale Semiconductor 23 Non-acceleration transfers will always succeed except in the case of oscillator fault, SPI error or request error conditions. Only oscillator failure, SPI error or request error conditions are reported in response to non-acceleration commands. Other error con- dition are reported as hardware errors in response to acceleration data requests.

4.1.8 Register Write Operations

Register write operations are initiated when bits 15 and 13 from the master is set to a logic ‘0’ and bit 14 is set to a logic ‘1’. Bits 12 through 8 contain a five-bit address, while the last eight bits contain the data value to be written. Only the DEVCTL register is writable. If an attempt is made to write to any register other than DEVCTL, a request error response (see Figure 4-15) will occur. Figure 4-9 Register Write Command Response to a register write operation is illustrated below. DEVCTL bits which can be read as logic ‘1’ (HPFB, ST1 and ST0) will be indicated during the last eight clock cycles, as shown. Figure 4-10 Register Write Command Response

4.1.9 Register Read Operations

Register read operations are initiated when bit 15 from the master is set to a logic ‘1’ state and bits 14 and 13 are driven to a logic low level. The address of the register to be accessed is contained in bits 12 through 8. DIN bits 7 through 0 are ignored by MMA62XXKEG during register read command transfers. Figure 4-11 Register Read Command Data read from the selected register is returned in bits 7 through 0, as shown below. Figure 4-12 Register Read Command Response SCLK BIT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN 1 0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D00 SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

01 P 0 HPFB 0 ST1 ST0000 111 0 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN 0 0 A4 A3 A2 A1 A0 X X X X X X X X1 SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

10 P D 4D 3D 2D 1 D0D6 D50 111 0 D7

24 Freescale Semiconductor

4.1.10 Device Test Operation

A device test operation is conducted when DIN bits 15 and 14 are at a logic high level and bit 13 is driven to a logic low level. Figure 4-13 Device Test Command The content of the device status register are transmitted in bits D7 through D0 in response to a device test operation. Refer to Section 3.1.3 for details regarding the device status register Figure 4-14 Device Test Command Response Status register bit 0 is set following any device reset. This bit will remain set until explicitly cleared by writing the CE bit in the device control register, as described in Section 3.1.1.

4.1.11 Non-Acceleration Request Error

An error condition is indicated if a non-acceleration command is detected and DIN bits 15 and 14 are both zero, as no operation is specified for this combination. Figure 4-15 Non-Acceleration Request Error

4.1.12 SPI Error Response

The following conditions detected at DIN will result in a SPI error. Since the error condition likely indicate a corrupted transfer, the response frame is the same regardless of the state of bit 13 at DIN.

• SCLK high when CS asserted
• Fewer than 16 rising edges of SCLK detected while CS is asserted
• Greater than 16 rising edges of SCLK detected while CS is asserted
• SCLK high when CS negated SCLK BIT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN 1 0 XXXXXXXXXXXXX1 SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

11 PD 4 D 3 D 2 D 1 D0D6 D50 111 0 D7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00P01 1 1 000 100 00

Freescale Semiconductor 25 The response to a SPI error condition is shown below. Figure 4-16 SPI Error Response

4.1.13 Initial Response

During initialization phase one, the device does not respond to SPI access attempts. During the second initialization phase, reg- ister operations complete normally, however the device will respond to sensor data requests with No Data (ND) status. The first acceleration request following completion of device initialization will also result in a No Data response. This ensures that an un- expected reset will always be detectable, even in systems which poll the device at longer intervals than required for device ini- tialization.

4.2 ERROR CONDITIONS

A number of error conditions may be detected. If an error condition is detected, MMA62XXKEG will always transmit an error in- dicator in place of acceleration data. Error indicators are defined in the following sections.

4.2.1 Error Condition Classification

Error conditions fall into five classes, as described below.

4.2.1.1 Critical Errors

Error condition affects device operation. Critical errors are always reported regardless of other error conditions which may be detected.

4.2.1.2 Initialization

Initialization is a special case condition which occurs after reset until internal circuitry is ready to provide accurate acceleration results. The duration of the initialization period depends upon whether a high-pass filter has been selected or not. If no high-pass filter has been selected, initialization requires approximately 3 ms after power-up. If a high-pass filter has been selected, an ad- ditional 200 ms is required. During the device initialization period, this status is reported in response to any acceleration data request, however normal register access operations may be performed. Device initialization status is cleared automatically.

4.2.1.3 Reset

Reset is also a special case condition. Reset will occur at power-on, as the result of a temporary undervoltage condition, or in response to explicit actions taken by the controller. Upon negation of the internal reset signal, the DEVRES flag in the device status (DEVSTAT) register is set. Because it is critically important that the system can detect any unintended reset condition, this flag may only be cleared by writing a logic ‘1’ to the CE bit in the device control register (DEVCTL) after device initialization has completed.

4.2.1.4 Transient Errors

An error condition which may be the result of a condition which precludes an accurate acceleration measurement but which may not persist. Transient errors are reported in response to acceleration data transfer requests. If a transient error condition has been detected, a logic ‘1’ may be written to the clear error (CE) bit in the device control (DEVCTL) register to clear the associated flag. Should the error condition still exists, the flag will only be cleared momentarily. SCLK BIT DOUT CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00P01 1 1 000 100 00

26 Freescale Semiconductor

4.2.1.5 External Errors

An error condition resulting from an invalid command input or corrupted data transfer. External errors are reported only once. Errors are prioritized as shown in the table. In the event that multiple error conditions are detected, the highest priority error will be reported.

4.2.2 Error Definitions

4.2.2.1 Internal Data Error

Class: Critical error A parity fault has been detected in the internal data registers. In the event of a soft error (bit-flip within the register), an internal data error may be recoverable by resetting the device.

4.2.2.2 Internal Oscillator Fault

Class: Critical error If an oscillator fault condition is detected, DOUT is driven high continuously when CS is asserted, as illustrated below. Figure 4-17 Oscillator Failure Response

4.2.2.3 Device Initialization

Class: Reset Following a reset condition, the device requires a period of time to complete initialization of the DSP and internal registers. If multiple SPI transfers are attempted during this initialization period, the second and all subsequent transfers will result in this status. The first transfer following reset, regardless of the state of initialization returns device reset status.

4.2.2.4 Temperature Fault

Class: Transient error The internal temperature sensor value exceeds the allowable limits for the device.

4.2.2.5 Unexpected Axis Selection

Class: External error An acceleration data request has been received with an axis specification which is not supported.

4.2.2.6 Offset Error

Class: Transient error This condition exists if the output of the offset monitor circuit reaches 10% of the full-scale value and the OFMON bit is set in the DSPCFG1 register.

4.2.2.7 Device Reset

Class: Reset Following any reset operation, the device returns this status during the first acceleration data access.

4.2.2.8 SPI Clock Fault

Class: External error A SPI clock fault may result from the following conditions:

• The number of rising clock edges detected while CS is asserted is not equal to 16
• SCLK is high when CS is asserted

4.3 ACCELERATION DATA REPRESENTATION

Acceleration values may be determined from the 10-bit digital output (DV) as follows: SCLK DOUT CS

Freescale Semiconductor 27 a = sensitivity × DV (signed data representation) Sensitivity is determined by nominal full-scale range (FSR), linear range of digital values and a scaling factor to compensate for sensitivity error. The linear range of digital values for MMA62XXKEG is limited to accommodate overrange values produced by the DSP along with two reserved end values. The linear range of digital values and signed values is from -509 to +508. Note that the ranges are asymmetrical by 1 LSB. The sensitivity error scaling factor is determined as follows: scale_factor = (100.0 - error_tolerance) / 100.0 Finally, the nominal sensitivity in terms of acceleration per LSB is determined: 1 LSB = (FSR / scale_factor) / ((Max_Linear_Value - Min_Linear_Value) / 2.0); For the linear ranges of digital values indicated and projected sensitivity values, the nominal value of 1 LSB for each full-scale range is shown in the table below. Table 4-4 Nominal Sensitivity (10-bit data) Full-Scale Range (g) Nominal Sensitivity (g/digit) Sensitivity Error = 4% 100 0.2048 50 0.1024 35 0.07170 20 0.04097

28 Freescale Semiconductor

Table 4-5 Nominal Signed Acceleration Data Values Digital Value Nominal Acceleration 10-Bit Range (Self Test Disabled) 20 g 35 g 50 g 100 g

511 Reserved

510 Overflow

509 Overrange

-510 Underrange -511 Underflow -512 Reserved

Freescale Semiconductor 29

4.3.1 Overrange Response

Positive acceleration levels which exceed the full-scale range of the device fall into two categories: overrange and overflow. Over- range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the DSP. An overflow condition occurs if the output of the low-pass filter equals or exceeds the maximum digital value which can be output from the sinc filter. Sinc filter saturation will occur before the internal datapath width is exceeded. At 25°C the sinc filter will not saturate at sustained acceleration levels with the range of ±200 g. The DSP operates predictably under all cases of over- range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. If an overflow condition occurs, the signal is internally clipped. The DSP will recover from an overflow condition within a few sample times after the input signal returns to the input range of the DSP. Due to internal clipping within the DSP, some high-frequency artifacts may be present in the output following an overflow condition. For negative acceleration levels, corresponding underrange and underflow conditions are defined.

4.4 CAP /HOLD INPUT

The CAP/HOLD input provides a system-level synchronization mechanism. When driven high, transfer of acceleration results from the DSP to the SPI buffers does not occur. The DSP continues its normal operation regardless of the state of CAP/HOLD. Data read from the device when CAP/HOLD is high will reflect the last values available from the DSP at the time of the signal transition.

30 Freescale Semiconductor

MMA62XXKEG operates in one of two modes, factory test programming mode and normal operating mode. Factory test and programming mode is entered only when certain conditions are met, and provides support for programming of customer-defined data. Normal mode is entered by default when the device is powered on.

5.1 NORMAL OPERATING MODE

Normal mode is entered whenever the device is powered and the VPP pin is held at or below the level of VCC. In normal mode, acceleration data and device support data transfers are supported.

5.1.1 Power-On Reset

Upon application of voltage at the VCC pin, the internal regulators will begin driving the internal power supply rails. The CREG and CREGA pins are tied to the internal rails. As voltages at VCC, CREG and CREGA rise, the device becomes operational. An internal reset signal is asserted at this time. Separate comparators on monitor all three voltages, and when all are above specified thresh- olds, the reset signal is negated and the device begins its initialization process.

5.1.2 Device Initialization

Following any reset, the device completes a sequence of operations which initialize internal circuitry. Device initialization is com- pleted in two phases. During the first phase, the fuse array is read and its contents are transferred to mirror registers. Power to the fuse array is then removed to reduce supply current load. A voltage reference used within the sensor interface stabilizes dur- ing the second phase. If the HPFSEL bit is set in the DSP configuration register (DSPCFG), the high-pass filter is also initialized during phase two. The device will not respond to SPI accesses during initialization phase one. Acceleration results are not available during initial- ization phase two, however the SPI is functional and register operations may be performed. If an acceleration data access is attempted, the device will respond with non-acceleration data. The first initialization phase requires approximately 800 μs to complete. The second phase completes in approximately 3 ms if no high-pass filter is selected, and 200 ms if the HPFSEL bit is programmed to a logic ‘1’ state. The DEVINIT bit in the device status register (DEVSTAT) remains set following reset until the second phase of device initialization completes.

Freescale Semiconductor 31 APPENDIX A Table A-1: Low-Pass Filter Options Filter Option Cutoff Frequency fC (HZ) Equivalent Poles Sample Time tS μs LPF_X[4] LPF_Y[4] LPF_X[3] LPF_Y[3] LPF_X[2] LPF_Y[2] LPF_X[1] LPF_Y[1] LPF_X[0] LPF_Y[0] Reference 0 0 0 0 0 0 10 256 0 0 0 0 1 1 15 128 0 0 0 1 0 2 30 64 0 0 0 1 1 3 50 0 0 1 0 0 4 75 32 0 0 1 0 1 5 100 0 0 1 1 0 6 130 0 0 1 1 1 7 160 0 1 0 0 0 8 200 16 0 1 0 0 1 9 250 0 1 0 1 0 10 300 0 1 0 1 1 11 350 0 1 1 0 0 12 400 0 1 1 0 1 13 500 0 1 1 1 0 14 600 0 1 1 1 1 15 700 1 0 0 0 0 16 800 1 0 0 0 1 17 900 1 0 0 1 0 18 1000 1 0 0 1 1 19 10 1 0 1 0 0 20 15 1 0 1 0 1 21 30 32 1 0 1 1 0 22 50 1 0 1 1 1 23 75 1 1 0 0 0 24 100 1 1 0 0 1 25 130 1 1 0 1 0 26 160 16 1 1 0 1 1 27 200 1 1 1 0 0 28 250 1 1 1 0 1 29 300 1 1 1 1 0 30 350 1 1 1 1 1 31 400

32 Freescale Semiconductor

Freescale Semiconductor 33 PACKAGE DIMENSIONS

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