MMA6222AEG FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- Available in ±20/20g, ±50/50g, or ±100/100g versions. Additional g-ranges between 20 and 100g may be available upon request
- Full-scale range is independently specified for each axis
- 400 Hz, 4 Pole, 16 µs sample time, additional filter options are available
- Ratiometric analog voltage output
- Capture/hold input for system-wide synchronization support
- 3.3 or 5 V single supply operation
- On-chip temperature sensor and voltage regulator
- Internal self-test
- Minimal external component requirements
- Pb-free 20-pin SOIC package
- Automotive AEC -Q100 qualified Typical Applications
- Crash detection (Airbag)
- Impact and vibration monitoring
- Shock detection
ORDERING INFORMATION
Device Name X-Axis g-Level Y-Axis g-Level Temperature Range Package Packaging MMA6222AEG 20 20 -40 to +105°C 475A-02 Tubes MMA6222AEGR2 20 20 -40 to +105°C 475A-02 Tape & Reel MMA6255AEG 50 50 -40 to +105°C 475A-02 Tubes MMA6255AEGR2 50 50 -40 to +105°C 475A-02 Tape & Reel MMA621010AEG 100 100 -40 to +105°C 475A-02 Tubes MMA621010AEGR2 100 100 -40 to +105°C 475A-02 Tape & Reel MMA6222AEG MMA6255AEG MMA621010AEG 2-AXIS ACCELEROMETER EG SUFFIX (Pb-free) 20-LEAD SOIC CASE 475A-02 PIN CONNECTIONS N/C VSS N/C VCC XOUT N/C VPP VSSA CAP/HOLD SCLK CREGA 20-PIN SOIC PACKAGE Y OUT ST CREG RESET STATUS CREF CREF CREGA N/C N/C: NO INTERNAL CONNECTION
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Figure 1-1 Simplified Airbag Application Diagram
1.1 INTRODUCTION
The MMA62XXEG is trimmed to provide the most accurate voltage representation of acceleration at XOUT and YOUT. This is done by adjusting the signal within the DSP to compensate for errors within the digital-to-analog converters. The SPI is disabled when the device is in normal operating mode, and dedicated ST (self-test activation) and STATUS pin functions are assigned. 1 μF100 nF 1 μF VCC MMA62XXAEG VCC CREG CREGA VSS VPP/TEST CS SCLK ST STATUS CS_A SCLK1 I/O Main MCU I/O CS_D SCLK2 MOSI2 MISO2 CS SCLK DI DO Deployment IC VSSA CREF 100 nF XOUT YOUT ADC Safing Sensor(s) / Comparator Filter DEPLOY_EN1 DEPLOY_EN2 Note: If one axis of the MMA62XXAEG sensor is expected to be used as a confirmation of the other axis, Freescale recommends that MMA62XXAEG used in conjunction with an additional sensing/safing device for each axis.
1.2 BLOCK DIAGRAM
A block diagram illustrating the major components of the design is shown in Figure 1-2. Figure 1-2 MMA62XXAEG Block Diagram Figure 1-3 MMA62XXAEG DSP Block Diagram NOTE: Models of signal chain are available upon request VCC VSS ST STATUS SCLK RESET SELF-TEST CREG CREF VPP XOUT INTERFACE TEMP. SENSOR SD CONVERTER VOLTAGE REGULATOR g-CELL (Y) g-CELL (X) CONTROL LOGIC UNIT DATA ARRAY PROGRAMMABLE SD CONVERTER CLOCK INTERNAL MONITOR CREGA CAP/HOLD DAC YOUT Y IN X IN DIGITAL Y OUT X OUT DSP TEMP (SEE FIGURE 1-2) OUT CONTROL IN STATUS OUT DAC CREF CREGA VSSA CLOCK PRIMARY OSCILLATOR REFERENCE OSCILLATOR SINC FILTER SINC FILTER OFFSET,LOW-PASS FILTER TO X DAC GAIN, LINEARITY ADJUST OUTPUT SCALING DSP CONTROL TO Y DAC TEMP CONTROL IN OFFSET MONITOR Y IN X IN OUT
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1.3 PIN FUNCTIONS
The pinout for the MMA62XXAEG device is illustrated in Figure 1-4. Pin functions are described below. When self-test is active, the output becomes more positive in both axes if ST1 is cleared, or more negative in both axes if ST1 is set. Figure 1-4 MMA62XXAEG Pinout N/C VSS N/C VCC XOUT N/C VPP VSSA CAP/HOLD SCLK CREGA 20-PIN SOIC PACKAGE YOUT ST CREG RESET STATUS CREF CREF CREGA N/C N/C: NO INTERNAL CONNECTION X: 0g Y: -1g X: +1g Y: 0g X: 0g Y: +1g X: -1g Y: 0g Response to static orientation within 1g field. TO CENTER OF GRAVITATION FIELD
1.4 PIN FUNCTION DESCRIPTIONS
1.4.1 V CC
This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best per- formance. An external bypass capacitor between this pin and VSS is required, as described in Section 1.5.
1.4.2 V SS
This pin is the power supply return node for the digital circuitry on the MMA62XXEG device.
1.4.3 V SSA
This pin is the power supply return node for analog circuitry on the MMA62XXAEG device. An external bypass capacitor between this pin and VCC is required, as described in Section 1.5.
1.4.4 C REG
This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between this pin and VSS, as described in Section 1.5.
1.4.5 C REGA
These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must be connected between these pins and VSSA, as described in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5.
1.4.6 C REF
These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external filter capacitors must be connected between these pins and VSSA, as described shown in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5.
1.4.7 VPP
This pin should be tied directly to VSS.
1.4.8 SCLK
This input may be left unconnected unless it is desired to initiate device reset as described in Section 1.4.9.
1.4.9 RESET
This pin may be used to initiate a hardware reset. If RESET is held low and SCLK is held high for 512 μs, the internal reset signal is asserted. An internal pull-up device is connected to this pin.
1.4.10 STATUS
This pin provides an indicator of internal status. The STATUS output will be driven to a logic high level should any of the following fault conditions be detected:
- Internal parity fault
- Over-temperature condition
- Internal clock frequency fault
- Device reset
- Device initialization Immediately following device reset, STATUS is placed in a high impedance state for approximately 800 μs. At the end of this time, STATUS is driven high and a 3ms stabilization delay required by the internal circuitry begins. The STATUS condition may not be cleared during the stabilization delay. Reset is reported by the device so the system can be aware of potential difficulties if unex- pected resets occur. Once asserted, the STATUS output will remain high until the ST pin is driven from a logic low to a logic high state. If a fault con- dition persists, the STATUS output will be driven high again as soon as it is cleared.
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1.4.11 ST This pin performs a dual function. When driven to a logic high level, the internal self-test voltage generator is activated. A low-to- high transition on this pin will clear the internal STATUS latch. Note that under certain fault conditions, the STATUS latch will be immediately reset, indicating a terminal fault condition. A diagram illustrating operation of the STATUS latch following device initialization is illustrated in Figure 1-5. Figure 1-5 ST and STATUS Interaction
1.4.12 CAP /HOLD
When this input pin is low, acceleration data is updated by the DSP whenever a data sample becomes available. Upon a low-to- high transition of CAP/HOLD acceleration data is frozen. Acceleration data is not updated as long as the pin remains at a logic ‘1’ level. This pin may be tied directly to VSS if the hold function is not desired.
1.4.13 X OUT, YOUT
Two digital-to-analog converters (DACs) are provided. These converters translate output of the DSP block into voltage levels pro- portional to the magnitude of the numerical result and ratiometric to VCC.
1.5 EXTERNAL COMPONENTS
The connections illustrated in Figure 1-1 are recommended. Careful printed wiring board layout and component placement is es- sential for best performance. Low ESR capacitors must be connected to CREG and CREGA pins for the best performance. A grounded land area with solder mask should be placed under the package for improved shielding of the device from external effects. If a land area is not provided, no signals should be routed beneath the package. See Figure 1-1. ST FAULT DETECT SELF TEST ENABLE VDD D R Q STATUS
SECTION 2 PERFORMANCE SPECIFICATION
2.1 MAXIMUM RATINGS
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device con- tains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep input and output voltages within the range VSS ≤ V ≤ VCC. Notes: 1. Verified by characterizati on, not tested in production.
2.2 OPERATING RANGE
The operating ratings are the limits normally expected in the application and define the range of operation. Notes: 1. Characterized at all values of V L and VH. Production test is conducted at typical voltage unless otherwise noted. 2. Parameters tested 100% at final test. Ref Rating Symbol Value Unit 1 Supply Voltage VCC -0.3 to +7 V (1) 2 CREG, CREGA, CREF VREG -0.3 to +3 V (1) 3 VPP VREG -0.3 to +11 V (1) 4 SCLK, ST, CAP/HOLD VIN -0.3 to VCC + 0.3 V (1) 5 STATUS (high impedance state) VIN -0.3 to VCC + 0.3 V (1) 6 XOUT, YOUT (DACEN = 0) VDAC -0.3 to VCC + 0.3 V (1)
7 Current Drain per Pin Excluding VCC and VSS I 10 mA (1)
8 Acceleration (without hitting internal g-cell stops) gmax ±800 g (1)
9 Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g (1) 10 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (1) 11 Drop Shock (to concrete surface) hDROP 1.2 m (1) Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) VESD VESD VESD ±2000 ±500 ±200 V V V (1) (1) (1)
15 Storage Temperature Range Tstg -40 to +125 °C (1)
Ref Characteristic Symbol Min Typ Max Units Supply Voltage Standard Operating Voltage, 3.3V operating range Standard Operating Voltage, 5V operating range VCC VCC VL +3.15 +4.75 +3.3 +5.0 VH +3.45 +5.25 V V (1) (1) Operating Temperature Range TA TL -40 ⎯ TH +105 C (2)
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2.3 ELECTRICAL CHARACTERISTICS
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 1. Parameters tested 100% at final test. 2. Verified by characterization, not tested in production. 3. Tested at V CC = VL and VCC = VH. 4. Power supply ripple at frequencies greater than 900 kH z should be minimized to the greatest extent possible. 5. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. (#) Indicates a FSL significant parameter (CPK > 1.33). (*) Indicates a FSL critical parameter (CPK > 1.67). Ref Characteristic Symbol Min Typ Max Units Supply Current Drain Analog-only output configuration IDD ⎯ 9.0 mA (1) Power-On Recovery Threshold (See Figure 2-1) VCC CREG CREGA CREF Power-On Reset Threshold (See Figure 2-1) VCC CREG CREGA CREF Hysteresis (VPOR_N - VPOR_A, See Figure 2-1) VCC CREG CREGA CREF VPOR_N VPOR_N VPOR_N VPOR_N VPOR_A VPOR_A VPOR_A VPOR_A VHYST VHYST VHYST VHYST 2.77 1.80 2.18 1.11 2.77 1.80 2.18 1.11 3.15 2.32 2.50 1.29 2.95 2.10 2.31 1.19 388 300 261 150 V V V V V V V V mV mV mV mV (2) (2) (2) (2) (2) (2) (2) (2) 32 Minimum Functional Voltage (See Figure 2-1) VDACU ⎯ ⎯ 2.0 V (2) Internally Regulated Voltages CREG CREGA (3) CREF VDD V2.5 VREF 2.42 2.42 1.20 2.50 2.50 1.25 2.58 2.58 1.29 V V V (1) (1) (1) External Filter Capacitor (CREG, CREGA) Value ESR (including interconnect resistance) CREG ESR 800 1000 200 nF mΩ (2) (2) Power Supply Coupling (4) Analog output See Figure 2-2 (2) Analog Sensitivity (XOUT, YOUT) 20g Range 35g Range 50g Range 100g Range Sensitivity Error T A = 25°C 40°C ≤ TA ≤ 105°C ASENS ASENS ASENS ASENS ΔSENS ΔSENS 23.40 13.40 9.37 4.68 mV/V/g mV/V/g mV/V/g mV/V/g (1)(5) (1)(5) (1)(5) (1)(5) (1)(5) (1)(5) Offset at 0g Analog output (XOUT, YOUT) * AOUT 0.46 × VCC 0.5 × VCC 0.54 × VCC V (1)(5)
2.3 ELECTRICAL CHARACTERISTICS (CONTINUED)
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 1. Parameters tested 100% at final test. 2. Parameters tested 100% at unit probe. 3. Verified by characterizati on, not tested in production. Ref Characteristic Symbol Min Typ Max Units Output value on overrange 20g Range 35g Range 50g Range 100g Range Output value on Underrange 20g Range 35g Range 50g Range 100g Range gOVER gOVER gOVER gOVER gUNDER gUNDER gUNDER gUNDER +20.0 +35.0 +50.0 +100.1 -20.1 -35.1 -50.1 -100.3 +20.9 +36.6 +52.1 +104.3 -20.9 -36.6 -52.2 -104.5 +22.1 +38.7 +55.3 +110.5 -22.2 -38.8 -55.4 -110.7 g g g g g g g g (3) (3) (3) (3) (3) (3) (3) (3) Maximum acceleration without saturation of internal circuitry All ranges gSAT -200 — +200 g (3)
55 Nonlinearity NLOUT -1 — 1 % FSR (3)
56 Noise (1Hz-1kHz) nSD — — 1.1 mg/√Hz (3) Positive Self Test Output Change (XOUT, YOUT, analog) TA = 25°C -40°C ≤ TA ≤ 105°C ΔST ΔST % FS % FS (1) (1) Cross-Axis Sensitivity VZX VYX VZY VXY VZX VYX VZY VXY (3) (3) (3) (3) DAC Characteristics (XOUT, YOUT) Minimum Output Level, IOUT = -200 μA Maximum Output Level, IOUT = 200 μA Offset Error Gain Error Differential Nonlinearity Integral Nonlinearity T A = 25°C -40°C ≤ TA ≤ 105°C AVLOW AVHIGH OFST GERR DNL INL INL VCC - 0.25 -0.2 -0.3 -3.5 0.25 +0.2 +0.3 +3.5 V V %FSR %FSR digit digit digit (2) (2) (2) (2) (2) (2) (3) Output High Voltage STATUS (ILoad = -100 μA) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOH VOH 3.25 3.75 V V (2) (2) Output Low Voltage STATUS (ILoad = 100 μA) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOL VOL 0.4 0.4 V V (2) (2) Output Loading (STATUS) Load Resistance Load Capacitance ZOUT COUT kΩ pF (3) (3)
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VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 2. Parameters tested 100% at unit probe. 3. Verified by characterization, not tested in production. Ref Characteristic Symbol Min Typ Max Units Output Loading (XOUT, YOUT) Load Resistance Load Capacitance ZOUT COUT kΩ pF (3) (3) Input High Voltage RESET, SCLK, ST, CAP/HOLD 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIH VIH 1.5 2.5 V V (2) (2) Input Low Voltage RESET, SCLK, ST, CAP/HOLD 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIL VIL 0.85 1.0 V V (2) (2) Input Current High (at VIH) SCLK, ST, CAP/HOLD VPP/TEST (internal pulldown resistor) Low (at VIL) RESET IIH RIN IIL -30 190 -50 270 -260 350 260 μA kΩ μA (2) (2) (2)
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2.4 CONTROL TIMING
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Notes: 1. Parameters tested 100% at final test. 2. Parameters tested 100% at unit probe. 3. Verified by characterizati on, not tested in production. 7. Functionality verified 100% via scan. Ti ming characteristic is directly determined by internal oscillator frequency. 9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. 10. Low-pass filter characterist ics match those of other Freescale accelerometer devices. Cutoff frequencies shown are -4dB referenced to 0 Hz response, to correspond with previous specifications. Ref Characteristic Symbol Min Typ Max Units DSP Low-Pass Filter (Note 9) Cutoff frequency (Note 10)
86 Filter Option $0C, $1F fC(LPF) 380 400 420 Hz (7)
Cutoff frequency (-3dB, referenced to 0 Hz) Filter $0C, $1F fC(LPF) 335 353 371 Hz (7) Filter Order Filter $00 - $12 OLPF — 4 — 1 (7) Power-On Recovery Time Power applied to XOUT, YOUT valid tXY —— — 10 ms (1) 90 Internal Oscillator Frequency fOSC 3.8 4.0 4.2 MHz (1) 91 Clock Monitor Threshold fMON 3.6 — 4.4 MHz (7)
92 Chip Select to Internal Reset (See Figure 2-3) tCSRES 486 512 538 μs (7)
(1) (7)
95 Sensing Element Rolloff Frequency (-3 dB) BWGCELL — 3 — kHz (1)
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Figure 2-1 Power-Up Timing Figure 2-2 Power Supply Coupling - DAC Outputs VCC tXY XOUT/YOUT 5.5V VPOR_N VPOR_A VDACU DAC OUTPUT UNCERTAIN POR
Freescale Semiconductor 13 Figure 2-3 CS Reset Timing INTERNAL RESET CS tCSRES SCLK
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Freescale Semiconductor 15 PACKAGE DIMENSIONS
Rev. 1 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2008. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http:/www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
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