MMA2612NKW

MMA26XXNKW FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• ±25g to ±312.5g Nominal Full-Scale Range
• Selectable 180 Hz, 2-pole, 400 Hz, 4-pole, or 800 Hz, 4-pole LPF
• DSI2.5 Compatible with full support of Mandatory Commands
• 16 μs internal sample rate, with interpolation to 1 ms
• -40°C to 125°C Operatin g Temperature Range
• Pb-Free 16-Pin QFN, 6 by 6 Package
• Qualified AECQ100, Revision G, Grade 1 (-40 °C to +125°C) (http://www.aecouncil.com/ Typical Applications
• Airbag Front and Side Crash Detection For user register array programming, please consult your Freescale representative.

ORDERING INFORMATION

Device Axis Range Package Shipping MMA2602NKW X 25g 2086-01 Tubes MMA2605NKW X 50g 2086-01 Tubes MMA2606NKW X 62.5g 2086-01 Tubes MMA2612NKW X 125g 2086-01 Tubes MMA2618NKW X 187g 2086-01 Tubes MMA2631NKW X 312g 2086-01 Tubes MMA2602NKWR2 X 25g 2086-01 Tape & Reel MMA2605NKWR2 X 50g 2086-01 Tape & Reel MMA2606NKWR2 X 62.5g 2086-01 Tape & Reel MMA2612NKWR2 X 125g 2086-01 Tape & Reel MMA2618NKWR2 X 187g 2086-01 Tape & Reel MMA2631NKWR2 X 312g 2086-01 Tape & Reel MMA26xxNKW 16-PIN QFN CASE 2086-01 PIN CONNECTIONS Bottom View Top View TEST2 BUSRTN TEST7 VSS TEST6 TEST5 BUSIN HCAP CREGA TEST4 C REG TEST3 TEST1 BUSOUT VSSA PCM 5 6 7 8 16 15 14 13

Figure 3. Block Diagram

4 Freescale Semiconductor, Inc.

1 Pin Connections

Figure 4. Block Diagram Table 1. Pin Description 1 TEST2 Test Pin This pin must be left unconnected in the application. 2 TEST3 Test Pin This pin must be grounded in the application. 3 TEST1 Test Pin This pin must be grounded in the application. 4 BUSRTN Ground This pin is the common return for power and signalling.

5 PCM PCM

6 VSSB Ground This pin must be grounded in the application.

7 BUSIN Supply /

This pin is connected to the DSI positive bus node and provides the power supply and communication to the system master. An external capacitor must be connected to between this pin and the BUSRTN pin. Reference Figure 1.

8 HCAP Hold Capacitor

be connected between this pin and the BUSRTN pin to store energy for operation during master communication signalling.

9 CREG

this pin and VSS. Reference Figure 1. 10 TEST4 Test Pin This pin must be grounded in the application.

11 CREGA

this pin and VSSA. Reference Figure 1. 12 VSSA Analog GND This pin is the power supply return node for analog circuitry. 14 TEST6 Test Pin This pin must be grounded in the application. 15 TEST7 Test Pin This pin must be grounded in the application. 16 VSS Digital GND This pin is the power supply return node for the digital circuitry. 17 PAD Die Attach Pad This pin is the die attach flag, and should be connected to VSS in the application. Reference Section 5. Pads Corner Pads The corner pads are internally connected to VSS.

Freescale Semiconductor, Inc. 5 MMA26xxNKW

2 Electrical Characteristics

2.1 Maximum Ratings

Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. Do not apply voltages higher than those shown in the table below.

2.2 Operating Range

The operating ratings are the limits normally expected in the application. VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified. # Rating Symbol Value Unit Supply Voltage (continuous) (BUSIN, HCAP) Supply Voltage (pulsed < 400 ms, repetition rate 60s) (BUSIN, HCAP) V CC VCC -0.3 to +30.0 -0.3 to +34.0 V V (3) (3) REG, CREGA, PCM, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 -0.3 to +3.0 V (3) BUSIN, BUSRTN and HCAP Current Maximum duration 1 s Continuous I IN IIN 400 mA mA (3) (3) 6 Powered Shock (six sides, 0.5 ms duration) g pms ±2000 g (5) 7 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (5) 8 Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation) hDROP 1.2 m (5) Electrostatic Discharge (per AECQ100) HBM (100 pF, 1.5 kΩ) CDM (R = 0Ω) MM (200 pF, 0Ω) VESD VESD VESD ±2000 ±500 ±200 V V V (5) (5) (5) Temperature Range Storage Junction T stg TJ -40 to +125 -40 to +150 (3) (3)

14 Thermal Resistance θ

JC 2.5 °C/W (11) # Characteristic Symbol Min Typ Max Units Supply Voltage V HCAP BUSIN VHCAP VBUS VL 6.3 -0.3 V H V V (1,12) (1,12) Programming Voltage Applied to BUSIN (DSI) V PP 14.0 ⎯ 30.0 V (3) Programming Current BUSIN IPP 85 ⎯⎯ mA (3) Operating Temperature Range T A TA TL -40 -40 T H +105 +125 (1) (3)

6 Freescale Semiconductor, Inc. MMA26xxNKW

2.3 Electrical Characteristics - Supply and I/O

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.

2.4 Electrical Characteristics - DSI

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units 21 Quiescent Supply Current * I DD ⎯⎯ 8.0 mA (1) Inrush Current (excluding HCAP Capacitor charge current) Power On until VREG Stable IINRUSH ⎯⎯ 20 mA (3) Internally Regulated Voltages VREG VREGA VREG VREGA 2.425 2.425 2.50 2.50 2.575 2.575 V V (1) (1) V HCAP Under-Voltage Detection (See Figure 5) Under-Voltage Detection Threshold V HCAP Recovery Threshold Hysteresis (VPORHCAP_r - VPORHCAP_f) VPORHCAP_f VPORHCAP_r VHYST_HCAP 5.8 6.0 100 6.2 6.3 140 V V mV (3,6) (3,6) (3) Internal Regulator Low Voltage Detection Threshold V REG Falling VREGA Falling Hysteresis VREG VREGA VPORVREG_f VPORVREGA_f VHYST_VREG VHYST_VREGA 2.15 2.15 0.05 0.05 2.25 2.25 0.10 0.10 2.40 2.40 0.15 0.15 V V V V (3.6) (3.6) (3) (3) External Capacitor (CREG, CREGA) Capacitance ESR (including interconnect resistance) CREG, CREGA RCREGESR, RCREGAESR 500 1000 1500 200 nF mΩ (9) (9) Output High Voltage (PCM) I Load = 100 μAV OH VREG - 0.1 ⎯⎯ V( 9 ) Output Low Voltage (PCM) ILoad = 100 μAV OL ⎯⎯ 0.1 V (9) Temperature Monitoring Under-Temperature Monitor Threshold Over-Temperature Monitor Threshold T UNDER TOVER 155 -55 (9) (9) # Characteristic Symbol Min Typ Max Units HCAP Rectifier Leakage Current VBUSIN = 0V, VHCAP = 9.0V * I RLKG ⎯⎯ 100 μA( 1 ) BUSIN to HCAP Rectifier Voltage Drop (VBUSIN = 7V) IHCAP = -15 mA IHCAP = -100 mA V RECT VRECT 0.75 0.9 1.0 1.2 V V (1) (1) BUSIN Bias Current V BUSIN = 8.0V, VHCAP = 9.0V VBUSIN = 4.5V, VHCAP = 24V, No Response Current *I BUSIN_BIAS IBUSIN_BIAS -100 -100 100 100 μA μA (1) (1) BUSIN Response Current V BUSIN = 4.0V * IRESP 9.9 11 12.1 mA (1) BUSIN Logic Thresholds Signal Threshold Frame Threshold V THS VTHF 2.8 5.5 3.0 6.0 3.2 6.5 V V (1) (1) BUSIN Logic Hysteresis Signal Frame V HYSS VHYSF 100 300 mV mV (3) (3)

Freescale Semiconductor, Inc. 7 MMA26xxNKW

2.5 Electrical Characte ristics - Signal Chain

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units Sensitivity (10-bit @ 100 Hz referenced to 0 Hz) 25g Range 50g Range 62.5g Range 125g Range 187g Range 312g Range Total Sensitivity Error (including non-linearity) T A = 25°C TL ≤ TA ≤ TH SENS SENS SENS SENS SENS SENS ΔSENS_25 ΔSENS 20.48 10.24 8.192 4.096 2.731 1.638 LSB/g LSB/g LSB/g LSB/g LSB/g LSB/g (1,14) (1,14) (1,14) (1,14) (1,14) (1,14) (1) (1) Digital Offset 10-bit output * OFF 10Bit 460 512 564 LSB (1) Range of Output (10-Bit Mode) Acceleration Internal Error RANGE ACC RANGEERR 1023 LSB LSB (3) (3) Cross-Axis Sensitivity Z-axis to X-axis Y-axis to X-axis V ZX VYX (3) (3)

61 ADC Output Noise Peak (1 Hz - 1 kHz, 10-Bit) n

SD -4 — +4 LSB (3) 62 System Output Noise (10-Bit, RMS, All Ranges) nRMS ⎯⎯ +1.2 LSB (3) Non-linearity (all ranges) 10-bit output, Range < 50g 10-bit output, 50g ≤ Range ≤ 312.5g NLOUT_sub50g NLOUT_sub250g (3) (3)

8 Freescale Semiconductor, Inc. MMA26xxNKW

2.6 Electrical Characteristics - Self-Test and Overload

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units Acceleration (without hitting internal g-cell stops) ±25g, ±50g, ±62.5g, ±125g g g-cell_Clip60X 400 456 500 g (9) Acceleration (without hitting internal g-cell stops) ±187g, ±312g gg-cell_Clip240X 1750 2065 2300 g (9) ΣΔ and Sinc Filter Clipping Limit ±25g g ADC_Clip60X 98 108 121 g (9) ΣΔ and Sinc Filter Clipping Limit ±50g g ADC_Clip60X 191 210 232 g (9) ΣΔ and Sinc Filter Clipping Limit ±62.5g g ADC_Clip60X 191 210 232 g (9) ΣΔ and Sinc Filter Clipping Limit ±125g gADC_Clip120X 353 379 409 g (9) ΣΔ and Sinc Filter Clipping Limit ±187g g ADC_Clip240X 1690 1876 2106 g (9) ΣΔ and Sinc Filter Clipping Limit ±312g g ADC_Clip480X 1690 1876 2106 g (9) Deflection, 10-Bit, Self-Test - Offset, 30 sample ave, T A = 25°C) ±25g Range ±50g Range ±62.5g Range ±125g Range ±187g Range ±312g Range ΔDFLCT_X25 ΔDFLCT_X50 ΔDFLCT_X62 ΔDFLCT_X125 ΔDFLCT_X187 ΔDFLCT_X312 246 123 LSB LSB LSB LSB LSB LSB (1) (1) (1) (1) (1) (1))

79 Self-test deflection range, T

A = 25 °C ΔDFLCT -10 ⎯ +10 % (1)

80 Self-test deflection range, T L ≤ TA ≤ TH ΔDFLCT -20 ⎯ +20 % (1)

Freescale Semiconductor, Inc. 9 MMA26xxNKW

2.7 Dynamic Electrical Characteristics - DSI

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units Reset Recovery (See Figure 20) POR negated to 1st DSI Command (Initialization Command) POR negated to Acceleration Data Valid (Including LPF Init) DSI Clear Command to 1st DSI Command (Initialization Command) DSI Clear Command to Acceleration Data Valid (Including LPF Init) t DSI_INIT tDSP_INIT tDSI_INIT tDSP_INIT 400 / f OSC 400 / fOSC 10000 / fOSC 10000 / fOSC s s s s (7) (7) (7) (7) HCAP Under-Voltage Reset Delay (See Figure 5) V HCAP < VPORHCAP_f to POR assertion tHCAP_POR ⎯ 880 / fOSC ⎯ s( 7 ) VREG Under-Voltage Reset Delay (See Figure 6) VREG < VPORVREG_f to POR assertion tVREG_POR ⎯⎯ 5 μs( 3 ) VREGA Under-Voltage Reset Delay (See Figure 7) VREGA < VPORVREGA_f to POR assertion tVREGA_POR ⎯⎯ 5 μs( 3 ) VREG, VREGA Capacitor Monitor POR to first Capacitor Test Disconnect Disconnect Time () Disconnect Rate () tPOR_CAPTEST tCAPTEST_TIME tCAPTEST_RATE 12000 / fOSC 6 / fOSC 256 / fOSC s s s (7) (7) (7)

91 Communication Data Rate DRATE 100 ⎯ 200 kbps (7)

Maximum time below frame threshold t TO 2.00 ⎯ 4.00 ms (7) BUSIN Response Current Slew Rate BUSIN Timing to Response Current BUSIN Negative Voltage Transition =3.0V to IRSP = 7.0 mA rise BUSIN Negative Voltage Transition =3.0V to IRSP = 5.0 mA fall tRSP_R tRSP_F 2.50 2.50 μs μs (7) (7) DSI BUSIN Signal Duty Cycle Logic ‘0’ Logic ‘1’ D CL DCH (7) (7) 100 Inter-frame Separation Time (See Figure 8) Following Read Write NVM Command Following Initialization Following other DSI bus commands t IFS tIFS tIFS ms μs μs (7) (7) (7)

101 DSI Data Latency t

LAT_DSI 4 / fOSC ⎯ 5 / fOSC s( 7 ) 102 OTP Program Timing Time to program one OTP bit t PROG_BIT 64 ⎯ 256 μs( 7 ) 103 104 105 106 107 108 Self-Test Response Time Self-Test Activation time (EOF Slave to 90% ΔDFLCT_xxx, 180 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 180 Hz LPF) Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 400 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 400 Hz LPF) Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 800 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 800 Hz LPF) tST_ACT_180 tST_DEACT_180 tST_ACT_400 tST_DEACT_400 tST_ACT_800 tST_DEACT_800 2.00 2.00 1.00 1.00 0.50 0.50 5.00 5.00 2.50 2.50 1.75 1.75 ms ms ms ms ms ms (7) (7) (7) (7) (7) (7) 109 Error Detection Response Time Mirror Register CRC Error to Status Flag (S) set (Factory or User Array) t CRC_Err ⎯ 75 / fOSC ⎯ s( 7 )

10 Freescale Semiconductor, Inc. MMA26xxNKW

2.8 Dynamic Electrical Char acteristics - Signal Chain

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified. Notes: 1. Parameters tested 100% at final test at -40°C, 25°C, and 105°C. 2. Parameters tested 100% at probe. 3. Verified by characterization. 4. * Indicates critical characteristic. 5. Verified by qualification testing, not tested in production. 6. Parameters verified by pass/fail testing in production. 7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is determined by internal system clock frequency. 8. Verified by user system level characterization, not tested in production, or at component level. 9. Verified by Simulation. 10.Measured at final test. Self-test activation occurs under control of the test program. 11.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad. 12.Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100% to 24V at final test. 13.N/A. 14.Sensitivity, and overload capability specifications will be reduced when 80Hz filter is selected. 15.Filter cutoff frequencies are directly dependent upon the internal oscillator frequency. 16.Target values. Actual values to be determined during device characterization. # Characteristic Symbol Min Typ Max Units 110 Internal Oscillator Frequency * f OSC 3.80 4 4.20 MHz (1)

111 Data Interpolation Latency tLAT_INTERP 64 / fOSC ⎯ 65 / fOSC s( 7 )

Cutoff frequency LPF0 (referenced to 0 Hz) Filter Order LPF0 Cutoff frequency LPF1 (referenced to 0 Hz) Filter Order LPF1 Cutoff frequency LPF2 (referenced to 0 Hz) Filter Order LPF2 f C_LPF0 OLPF0 fC_LPF1 OLPF1 fC_LPF2 OLPF2 171 380 760 180 400 800 189 420 840 Hz Hz Hz (7) (7) (7) (7) (7) (7) 118 119 Sensing Element Rolloff Frequency (-3 db) ±187g, ±312g f gcell_3dB_xlo fgcell_3dB_xhi 938 3952 2592 14370 Hz Hz (9) (9) 120 121 Sensing Element Natural Frequency ±187g, ±312g f gcell_xlo fgcell_xhii 12651 26000 13871 28700 Hz Hz (9) (9) 122 123 Sensing Element Damping Ratio ±187g, ±312g ζ gcell_xlo ζgcell_xhi 2.760 1.260 6.770 3.602 (9) (9) 124 125 Sensing Element Delay (@100 Hz) ±187g, ±312g f gcell_delay100_xlo fgcell_delay100_xhi 170 μs μs (9) (9) Package 100 ⎯⎯ kHz (9)

12 Freescale Semiconductor, Inc. Figure 8. DSI Bus Inter-frame Timing

3 Functional Description

3.1 User Accessible Data Array

grammed trim values. The user accessible data is shown in the table below. F: Freescale programmed OTP locationU/F:User and/or Freescale programmed OTP location. R: Read-only registerU:User Programmed OTP location. Note: Unused and Unprogrammed Spare bits always read ‘0’.

3.1.1 Device Serial Number Registers

lot size and quantities, all possible lot numbers and serial numbers may not be assigned. performance, and are only used for traceability purposes. Table 2. User Accessible Data

14 Freescale Semiconductor, Inc.

3.1.2 Device Type Register (TYPE)

factory programmed and are included in the factory programmed OTP CRC verification. These bits are read only to the user. Bit 7 - Bit 6 are user programmable OTP bits and are included in the user programmable OTP CRC verification.

3.1.2.1 Low-Pass Filter Select ion Bits (LPF[1:0]) (TYPE[7:6])

This filter option is not implemented. LPF[1:0] must not be set to this value to guarantee proper operation and performance.

3.1.2.2 Range Selection Bits (RNG[3:0]) (TYPE[3:0])

The Range Selection Bits indicate the full-scale range of the device, as shown below. These bits are factory programmed. Table 3. Factory Configuration Register

0000 N /A N/A

0111 N /A N/A

3.1.3 Device Configuration Register (DEVCFG)

3.1.3.1 Device ID Bit (DEVCFG[7])

DSI command. This bit can be factory or user programmed.

3.1.3.2 User Configuration CRC (CRC_U[2:0], DEVCFG[2:0])

Section 3.2.2 for details regarding the CRC for the user programmable OTP array. These bits can be factory or user programmed.

3.1.4 Device Configuration Register 1 (DEVCFG1)

register is included in the user register CRC check. Refer to Section 3.2.2 for details.

3.1.4.1 User Specific Data 00 Bits (UD00[5:0], DEVCFG1[7:2])

assembly specific information. These bits can be factory or user programmed.

3.1.4.2 Attribute Bits (AT_OTP[1:0], DEVCFG1[1:0])

Enable Self-Test Stimulus DSI commands. The transmitted values are qualified by the LOCK_U bit as shown in the table below. These bits can be factory or user programmed. Table 4. Device Control Register Table 5. Device Control Register 1

16 Freescale Semiconductor, Inc.

3.1.5 Device Configuration 2 Register (DEVCFG2)

3.1.5.1 User Configuration Loc k Bit (LOCK_U, DEVCFG2[7])

The LOCK_U bit is a factory or user programmed OTP bit which inhibits writes to the user configuration array when active. Reference Section 3.2.2 for details regarding the LOCK_U bit and CRC verification.

3.1.5.2 PCM Bit (DEVCFG2[5])

output. When the PCM output is cleared, the PCM output pin is actively pulled low. This bit can be factory or user programmed.

3.1.5.3 Device Address (ADDR[3:0], DEVCFG2[3:0])

3.1.6 User Data Registers (UDx)

Section 3.2.2 for details regarding the user register CRC check. These registers can be factory or user programmed. Table 6. Device Control Register

Freescale Semiconductor, Inc. 17 MMA26xxNKW

3.2 OTP Array Lock and CRC Verification

3.2.1 Factory Programmed OTP Array Lock and CRC Verification

The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the Factory programmed OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which the internal lock bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received. The Factory programmed OTP array is locked by Freescale and will always be active after POR. The CRC is continuously calculated on the factory programmed OTP array, which includes the registers listed below: Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification uses a generator polynomial of g(x) = X3 + X +1, with a seed value = ‘111’. The calculated CRC is compared against the CRC_F[2:0] bits. If a CRC mismatch is detected, an internal data error is set and the device responds to DSI messages as spec- ified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.

3.2.2 User Programmable OTP Array Lock and CRC Verification

The User Programmable OTP array is independently verified for errors with a 3-bit CRC. The CRC verification is enabled only when the User Programmable OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which the LOCK_U bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received. Once the LOCK_U bit is active, the CRC is continuously calculated on the user programmable OTP Array, which includes the registers listed below: Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification uses a generator polynomial of g(x) = X 3 + X+ 1, with a seed value = ‘111’. The calculated CRC is compared against the user programmed CRC, CRC_U[2:0], which is also included in the user programmable array. If a CRC mismatch is detected, an in- ternal data error is set, and the device responds to DSI messages as specified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values. Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a change to the CRC calculation regard- less of the state of the LOCK_U bit. A CRC mismatch will only be detected if the LOCK_U bit is active. Factory Lock Bit Value in Fuse Array Lock Bit Value in Mirror Register After Automatic Readout Lock Bit Active? CRC Verification Enabled?

0 N/A NO NO

Register Name Register Addresses Included in Factory CRC? Serial Number Registers SN0, SN1, SN2, SN3 Yes Type Register TYPE[5:0] Yes Factory Programmable Device Configuration Bits Internal Register Map Yes Factory OTP Array CRC CRC_F[2:0] No Factory OTP Array Lock Bit LOCK_F No Factory Lock Bit Value in Fuse Array Lock Bit Value in Mirror Register After Automatic Readout Lock Bit Active? CRC Verification Enabled? Register Name Register Addresses Included in User CRC? Type Register TYPE[7:6] Yes Device ID Bit DEVCFG[7]: 1 Yes User Data Register 0 DEVCFG1[7:2]: UD00[5:0] Yes Attribute Bits DEVCFG1[1:0]: AT_OTP[1:0] Yes PCM Bit DEVCFG2[5]: PCM Yes RESERVED Bit DEVCFG2[4] Yes Device Address DEVCFG2[3:0]: ADDR[3:0] Yes User Data Registers 1 - 8 UD01 - UD08 Yes User Programmable OTP Array CRC DEVCFG[2:0]: CRC_U[2:0] No User Programmable OTP Array Lock Bit DEVCFG2[7]: LOCK_U No

18 Freescale Semiconductor, Inc.

3.3 Voltage Regulators

regulators for the analog (VREGA) and digital circuitry (VREG). External filter capacitors are required, as shown in Figure 1. which is used by the ΣΔ converter. Figure 9. Voltage Regulation and Monitoring

3.3.1 C REG and CREGA Regulator Capacitor

stability. Figure 1 shows the recommended types and values for each of these capacitors.

3.3.2 V HCAP Voltage Monitor

Section 2, the device will be reset within the reset delay time (tHCAP_POR) specified in Section 2.7.

3.3.3 V REG, and VREGA Under-Voltage Monitor

tVREGA_POR) specified in Section 2.7.

3.3.4 V REG and VREGA Capacitance Monitor

the internal reset threshold, forcing a device reset. Figure 10. VREG Capacitor Monitor Figure 11. VREGA Capacitor Monitor

3.4 Internal Oscillator

The device includes a factory trimmed oscillator as specified in Section 2.8.

20 Freescale Semiconductor, Inc.

3.5 Acceleration Signal Path

3.5.1 Transducer

Reference Section 2.8 for transducer parameters. data stream at a nominal frequency of 1 MHz. Figure 12. ΣΔ Converter Block Diagram

3.5.3 Digital Signal Processing Block

the signal processing flow within the DSP block is shown in Figure 13. Figure 13. Signal Chain Diagram

3.5.3.1 Decimation Sinc Filter

filter with a decimation factor of 16. Figure 14. Sinc Filter Response, tS = 16 μs Table 7. Signal Chain Characteristics

22 Freescale Semiconductor, Inc.

3.5.3.2 Low-Pass Filter

Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter. The device provides the option for one of three low-pass filters. The filter is selected with the LPF[1:0] bits in the TYPE register. tion 2.8. Filter characteristics are illustrated in the figures below. Note: Low-Pass Filter Figures do not include g-cell frequency response. Table 8. Low-Pass Filter Coefficients

180 Hz LPF

400 Hz LPF

800 Hz LPF

Figure 15. Low-Pass Filter Characteristics: fC = 180 Hz, 2-Pole, tS = 16 μs

24 Freescale Semiconductor, Inc. Figure 16. Low-Pass Filter Characteristics: fC = 400 Hz, 4-Pole, tS = 16 μs

Figure 17. Low-Pass Filter Characteristics: fC = 800 Hz, 4-Pole, tS = 16 μs

26 Freescale Semiconductor, Inc.

3.5.3.3 Compensation

The device includes internal compensation circuitry to compensate for sensor offset, sensitivity and non-linearity.

3.5.3.4 Data Interpolation

time. Reference Figure 8 for more information regarding interpolation and data latency.

3.5.3.5 Output Scaling

the device. Figure 18 shows the method used to establish the acceleration data word from the 26-bit DSP output. Figure 18. Output Scaling Diagram

3.5.3.6 PCM Output Function

Figure 19. PCM Output Function Block Diagram

10 Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 Using Truncation

9 Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 Using Truncation

8 Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 Using Truncation

9 Bit ADDER

3.6 Device Initialization

Figure 20. Initialization Timing Table 9. Powerup or Under-Voltage Reset Initialization Process

1 Power up to a Known State 0 N/A N/A No Response

3 Read Fuse Array and Copy to Memory Array (Mirror Registers) 1 0 No Response

4 Initialize DSI State Machine (the device is ready for DSI Messages) t DSI_INIT 10 DSI Read Acceleration Data Short response = zero. DSI Read Acceleration Data Long response = invalid data.

5 Initialize the DSP (Acceleration Data is Valid) t DSP_INIT 0 0 Normal

Table 10. DSI Clear Command Initialization Process 4 Initialize DSI State Machine (the device is ready for DSI Messages) t DSI_INIT 10 DSI Read Acceleration Data Short response = zero. DSI Read Acceleration Data Long response = invalid data.

28 Freescale Semiconductor, Inc.

3.7 Overload Response

3.7.1 Overload Performance

• g-cell damping
• Non-linearity
• Clipping limits
• Symmetry Figure 21 shows the g-cell, Sigma Delta, and output clipping of the device over frequency. The relevant parameters are spec- ified in Section 2.

Figure 21. Output Clipping Vs. Frequency

3.7.2 Sigma Delta Overrange Response

turning to the normal range of operation due to non-linear effects of the sensor.

4 DSI Protocol Layer

4.1 Communication Interface Overview

The device is compatible with the DSI Bus Standard V2.5.

4.1.1 DSI Physical Layer

Reference DSI Bus Standard V2.5, Section 3 for information regarding the physical layer.

4.1.2 DSI Data Link Layer

the DSI data link layer features supported.

4.2 DSI Protocol

4.2.1 DSI Bus Commands

DSI Bus Commands are summarized in Table 11. The device supports only the command formats specified in Section 4.2.1. received, the device will not respond. Table 11. DSI Bus Command Summary

30 Freescale Semiconductor, Inc.

4.2.1.1 Initialization Command

standard long initialization command is received. If the BS bit is set in the initialization command, the device will be reset within tBSOPEN. If the device has been preprogrammed, PA[3:0] and A[3:0] must match the preprogrammed address. Programmable OTP array CRC is calculated and verified using the OTP programmed values of A[3:0] = ‘0000’. Once initialized, the device will no longer recognize or respond to Initialization commands. Table 12. Initialization Command Table 13. Initialization Command Bit Definitions PA[3:0] DSI Address to be programmed. These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command oper ation. ther details regarding register programming and bank selection. device during subsequent Read Write NVM commands. Table 14. Initialization Command Response Table 15. Initialization Response Bit Definitions These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command oper ation. ther details regarding register programming and bank selection. NVM Program Enable. This bit indicates if programming of the user-accessible OTP is enabled. This bit indicates the success or failure of the bus test performed as part of the Initialization command.

4.2.1.2 Request Status Command

• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11) The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’. The data bits D[7:0] in the command are only used in the CRC calculation.

Table 16. Request Status Command Table 17. Request Status Command Bit Definitions Table 18. Short Response - Request Status Command Table 19. Long Response - Request Status Command Table 20. Request Status Response Bit Definitions This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. Reference Table 59 for conditions that set the S bit. U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details. NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled. A[3:0] DSI device address. This field contains the device address.

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4.2.1.3 Read Acceleration Data Command

• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 )
• Enhanced Short Command as configured by the Form at Control Command (Reference Section 4.2.1.11) The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’. The data bits D[7:0] in the command are only used in the CRC calculation. The device truncates the LSBs for Acceleration Data Responses of length less than 10. If the result of the truncation is 0, the minimum acceleration value is transmitted as defined in Table 26.

Table 21. Read Acceleration Data Command Table 22. Read Acceleration Data Command Bit Definitions Table 23. Short Response - Read Acceleration Data Command

8 AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2]

9 AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1]

15 AT_OTP[1]

Table 24. Long Response - Read Acceleration Data Command Table 25. Read Acceleration Response Bit Definitions AD[9:0] 10-bit acceleration result produced by the device. This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. Reference Table 59 for conditions that set the S bit. A[3:0] DSI device address. This field contains the device address.

4.2.1.4 DSI Command #3

DSI Command ‘0011’ is not implemented. The device ignores all command formats with a command ID of ‘0011’. Table 26. Acceleration Data Values

111111 M aximum negative acceleration value

000000 S ensor Error

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4.2.1.5 Request ID Information Command

• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 )
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11 ) The device ignores the Request ID Information command if the DSI device address is set to the DSI Global Device Address of ‘0000’. The data bits D[7:0] in the command are only used in the CRC calculation.

4.2.1.6 DSI Command #5

DSI Command ‘0101’ is not implemented. The device ignores all command formats with a command ID of ‘0101’.

4.2.1.7 DSI Command #6

DSI Command ‘0110’ is not implemented. The device ignores all command formats with a command ID of ‘0110’. Table 27. Request ID Information Command Table 28. Request ID Information Command Bit Definitions Table 29. Short Response - Request ID Information Command Table 30. Long Response - Request ID Information Command Table 31. Request ID Response Bit Definitions V[2:0] Version ID. This field indicates t he device / silicon revision of the device. A[3:0] DSI device address. This field contains the device address.

4.2.1.8 Clear Command

• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 )
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11 ) When the device successfully decodes a Clear Command, and the address field matches either the assigned device address (PA[3:0]) or the DSI Global address of ‘0000’ the device logic is reset. Reference Section 3.6 for the initialization sequence fol- lowing a Clear Command. The data bits D[7:0] in the command are only used in the CRC calculation. There is no response to the Clear Command.

4.2.1.9 DSI Command #8

DSI Command ‘1000’ is not implemented. The device ignores all command formats with a command ID of ‘1000’. Table 32. Clear Command Table 33. Clear Command Bit Definitions Device Address of ‘0000’ the device logic is reset. Reference Section 3.6 for the initialization sequence following a Clear Command. Device Address of ‘0000’. Otherwise, the command is ignored.

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4.2.1.10 Write NVM Command

• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 ) The device ignores the Write NVM command if the command is in any other format, or if the DSI device address is set to the DSI Global Device Address of ‘0000’. The Write NVM command uses the nibble address definitions in Table 2 and summarized in Table 39. NV bit is cleared when the command is executed, the mirror registers addressed by WA[3:0] are updated with the contents of RD[3:0] and the DSI Device Address is returned regardless of the WA[3:0] value. If the Write NVM command is a request to change the Device Address, the new Device Address is returned. The DSI Bus idle voltage must exceed the minimum VPP voltage when programming the OTP array. No internal verification of the VPP voltage is completed while writing is in process. To verify proper writes, it is recommend that the registers be read back after writes to verify proper contents. The total Execution time for the Write NVM command is tPROG_BIT times the number of bits being programmed (1 - 4 bits). Inter-frame spacing between the Write NVM command and the subsequent DSI command must accommodate this timing. Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a change to the CRC calculation regardless of the state of the NV bit and the LOCK_U bit. A CRC mismatch will only be detected if the LOCK_U bit is active (reference Section 3.2.2).

Table 34. Write NVM Command Table 35. Write NVM Command Bit Definitions RD[3:0] RD[3:0] contains the data to be written to the OT P location addressed by WA[3:0] when the NV bit is set. WA[3:0] WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set. Table 36. Long Response - Write NVM Command (NV = 1) Table 37. Long Response - Write NVM Command (NV = 0) Table 38. Write NVM Response Bit Definitions Bnk[1:0] These bits provide the bank address selected in the Initialization command. RD[3:0] RD[3:0] contains the contents of the registers a ddressed by WA[3:0] after the execution of the NVM write. WA[3:0] WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.

Table 39. OTP Register Nibble Address Assignments

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4.2.1.11 Format Control Command

• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 ) The device ignores the Format Control command if the command is in any other format. The device supports the Format Con- trol command with the DSI Global Address of ‘0000’, but does not provide a response. The format control registers defined in the DSI Bus Standard V2.5 are shown in Table 44. The reset values assigned to each register are also indicated.

Table 40. Format Control Command Table 41. Format Control Command Bit Definitions FD[3:0] Data to be written to the Format Control Register addressed by FA[2:0] if the R/W bit is set to ‘1’. FA[2:0] The Address of the Format Control Register to read or written. Read/Write determines if the register at address FA[2:0] is to be read or written. Table 42. Long Response - Format Control Command Table 43. Format Control Response Bit Definitions FD[3:0] The contents of the Format Control Register addressed by FA[2:0]. FA[2:0] The Address of the Format Control Register that was read or written. Read/Write indicates if the register at address FA[2:0] was read or written. A[3:0] DSI device address. This field contains the device address. Table 44. Format Control Register Values

• Writes to the CRC Length Register of values greater than 8 are ignored. The contents of the register are unchanged.
• Writes to the Short Word Data Length register of values less than 8 are ignored. The contents of the register are unchanged. The contents of the Format Selection register determine whether the standard DSI values or the values in the format control registers are used. If the Format Selection register contains ‘1111’, the Format Control register values are active. Any write to the Format Control registers will become active upon completion of the write. In this case, the response to a Format Control Com- mand will maintain the format of the previous command resulting in an invalid response. A write of ‘0000’ to the Format Selection register activates the standard DSI values. A write to the Format Selection register of any other value is ignored.

4.2.1.12 Read Register Data Command

• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 ) The device ignores the Register Data command if the command is in any other format, or if the DSI device address is set to the DSI Global Device Address of ‘0000’. The read register command uses the byte address definitions shown in Table 2. Readable registers along with their Byte ad- dresses are shown in Table 2.

Table 45. Read Register Data Command

0000 R A [ 3 ] R A [ 2 ] R A [ 1 ] R A [ 0 ] A [ 3 ] A [ 2 ] A [ 1 ] A [ 0 ] 1011 0 t o 8 b i t s

Table 46. Read Register Data Command Bit Definitions RA[3:0] RA[3:0] contains the byte address of the register to be read. Table 47. Long Response - Read Register Data Command Table 48. Read Register Data Response Bit Definitions RD7:0] RD[7:0] contains the data of the register addressed by RA[3:0]. RA[3:0] RA[3:0] contains the byte address of the register to be read.

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4.2.1.13 Disable Self-Test Command

• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 )
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11 ) The data bits D[7:0] in the command are only used in the CRC calculation. The device supports the Disable Self-Test command with the DSI Global Address of ‘0000’, but does not provide a response. The Disable Self-Test Command removes the voltage from the self-test plate of the transducer which results in the acceleration output value returning to the 0g offset value within tST_DEACT_xxx, as specified in Section 2. A self-test lockout is activated when the device receives two consecutive Disable Self-Test commands Once self-test lockout is activated, the internal self-test circuitry is disabled until one of the following conditions occurs:
• HCAP under-voltage
• A Clear command is received
• Internal regulator under-vo ltage resulting in a reset
• A Frame Timeout resulting in a reset

Table 49. Disable Self-Test Command Table 50. Disable Self-Test Command Bit Definitions Table 51. Short Response - Disable Self-Test Command Table 52. Long Response - Disable Self-Test Command Table 53. Disable Self-Test Response Bit Definitions This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. Reference Table 59 for conditions that set the S bit. U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details. NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled. A[3:0] DSI device address. This field contains the device address.

4.2.1.14 Enable Self-Test Command

• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11 )
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11 ) The data bits D[7:0] in the command are only used in the CRC calculation. The device ignores the Enable Self-Test command when it is sent to the DSI Global Address of ‘0000’. The Enable Self-Test Command applies a voltage to the self-test plate of the transducer which results in a delta in the accel- eration output value of ΔDFLCT_xxx within tST_ACT_xxx, as specified in Section 2. This remains present until the Disable Self-Test command is received. Activation of the self-test circuit is inhibited if the self-test locking has been activated. If self-test locking is activated, the internal

Table 54. Enable Self-Test Command Table 55. Enable Self-Test Command Bit Definitions Table 56. Short Response - Enable Self-Test Command Table 57. Long Response - Enable Self-Test Command Table 58. Enable Self-Test Response Bit Definitions This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. Reference Table 59 for conditions that set the S bit. U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details. NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled. A[3:0] DSI device address. This field contains the device address.

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4.2.1.15 DSI Command #14

DSI Command ‘1110’ is not implemented. The device ignores all command formats with a command ID of ‘1110’.

4.2.1.16 Reverse Initialization Command

4.3 Exception Handling

Table 59 summarizes the exception conditions detected by the device and the response for each exception. Table 59. Exception Handling – No response to DSI commands. – No response to DSI commands. – DSI Read Acceleration Data Short response = zero. – DSI Read Acceleration Data Long response = normal. – DSI Read Acceleration Data Short response = self-test data. – DSI Read Acceleration Data Long response = self-test data. – No response to DSI commands. capacitor failure is removed. – No response to DSI commands. – Device must be re-initialized when capacitor failure is removed. voltage returns above VTHF or a supply under-voltage condition occurs. – No response to DSI commands. 100 – DSI Read Acceleration Data Short response = zero. – DSI Read Acceleration Data Long response = normal. 110 – DSI Read Acceleration Data Short response = zero. – DSI Read Acceleration Data Long response = self-test data. 100 – DSI Read Acceleration Data Short response = zero. – DSI Read Acceleration Data Long response = normal. 110 – DSI Read Acceleration Data Short response = zero. – DSI Read Acceleration Data Long response = self-test data. Disabled. 100 – DSI Read Acceleration Data Short response = zero. – DSI Read Acceleration Data Long response = normal. Enabled. 110 – DSI Read Acceleration Data Short response = zero. – DSI Read Acceleration Data Long response = self-test data. – Internal self-test circuitry enabled. – DSI Read Acceleration Data Short response = self-test data. – DSI Read Acceleration Data Long response = self-test data. – Internal self-test circuitry disabled. response to Enable Self-Test DSI command except the ST bit is not set. – DSI Clear command or Reset disables lockout.

5 Package

5.1 Case Outline Drawing

5.2 Recommended Footprint

Table 60. Revision History

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