Driver IC

MM912H634CV1AE

Freescale Semiconductor...

Integrated S12 Based Relay Driver with LIN

Manufacturer: Freescale Semiconductor...

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Technical content

Features

16-Bit S12 CPU, 64/48 kByte P-FLASH,
6.0 kByte RAM; 4/2 kByte D-FLASH
Background debug (BDM) & debug module (DBG)
Die to Die bus interface for transparent memory mapping
On-chip oscillator & two independent watchdogs
LIN 2.1 Physical Layer Interface with integrated SCI
10 digital MCU GPIOs shared with SPI (PA7…0, PE1…0)
10-Bit, 15 Channel - Analog to Digital Converter (ADC)
16-Bit, 4 Channel - Timer Module (TIM16B4C)
8-Bit, 2 Channel - Pulse width modulation module (PWM)
Six high voltage / Wake-up inputs (L5…0)
Three low voltage GPIOs (PB2…0)
Low power modes with cyclic sense & forced wake-up
Current sense module with selectable gain
Reverse battery protected voltage sense module
Two protected low side outputs to drive inductive loads
Two protected high side outputs
Chip temperature sensor
Hall sensor supply & integrated voltage regulator(s)

Figure 1. Simplified Application Diagram

ORDERING INFORMATION

See Page 2. MM912_634 48-PIN LQFP, 7.0 mm x 7.0 mm AE SUFFIX: Exposed Pad Option AP SUFFIX: Non Exposed Pad Option MM912_634 VSENSE VS1 VS2 LIN VDD AGND RESET RESET_A PA0/MISO LS1 LS2 ISENSEH* HS1 HS2* TEST_A LGND Battery Sense M TCLK L4* ISENSEL* PGND L5* Hall Sensor HSUP Hall Sensor PTB0/AD0/RX/TIM0CH0 PTB1/AD1/TX/TIM0CH1 PTB2/AD2/PWM/TIM0CH2 PA1/MOSI PA2/SCK PA3/SS PA4 PA5 PA6 PA7 BKGD/MODC PE0/EXTAL PE1/XTAL TEST ADC25 VDDD2D VDDX VDDRX DGND VSSRX VSSD2D Power Supply LIN Interface ADC Supply

2.5 V Suppy

5.0 V Supply

5.0 V Digital I/O

Feature not availablre in all Analog Options Low Side Drivers Current Sense Moe Hall Sensor Supply

5.0 V GPI/O with optional

pull-up (shared with ADC, PWM, Timer, and SCI)

12 V Light/LED and

(High Voltage and Wake-up capable) Analog Test

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 2

1 Ordering Information

Table 1. ORDERING INFORMATION

The 48 kB Flash option (MM912 G634) using the same S12I64 MCU with the tested FLASHSIZE reduced to 48 kB. This will limit the

usable Flash area to the first 48 kB (0x3_4000-0x3_FFFF).

The 48 kB Flash option (MM912 G634) using the same S12I64 MCU with the tested Data - FLASHSIZE reduced to 2.0 kB. This will limit

the usable Data Flash area to the first 2.0 kB (0x0_4400-0x0_4BFF).

The 48 kB Flash option (MM912 G634) using the same S12I64 MCU with the tested RAMSIZE reduced to 2.0 kB. This will limit the

usable RAM area to the first 2.0 kB (0x0_2800-0x0_2FFF). Table 2. Analog Options(5)

This table only highlights the analog die differences between t he derivatives. Features highlighted as “NO” or the Lx Inputs not

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 3 The device part number is following the standard scheme in Table 3: Table 3. Part Numbering Scheme

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 4 Table of Contents

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 5

Figure 2. Device Block Diagram

4 Channel Timer

2 Channel

2 Pin Assignment

Figure 3. MM912_634 Pin Out

2.1 MM912_634 Pin Description

Table 4. MM912_634 Pin Description

2 PE0/EXTAL MCU Oscillator

and Section 4.28, “Port Integration Module (S12IPIMV1).

3 PE1/XTAL MCU Oscillator

and Section 4.28, “Port Integration Module (S12IPIMV1). pin must be tied to EVSS in user mode.

7 PA3 MCU PA3 / SS General purpose port A input or output pin 3, shared with the SS signal of the

integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1).

8 PA2 MCU PA2 / SCK General purpose port A input or output pin 2, shared with the SCLK signal of the

integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1).

9 PA1 MCU PA1 / MOSI General purpose port A input or output pin 1, shared with the MOSI signal of the

integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1).

10 PA0 MCU PA0 / MISO General-purpose port A input or output pin 0, shared with the MISO signal of the

integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1). 11 VSSRX MCU 5.0 V Ground Ground for the MCU 5.0 V power supply. “MM912_634 - MCU Die Overview. 13 VSSD2D MCU 2.5 V Ground Ground for the MCU 2.5 V power supply. “MM912_634 - MCU Die Overview.

15 VDD Voltage Regulator

16 VDDX Voltage Regulator Output

LGND, and AGND are internally connected to PGND via a back to back diode.

18 VSENSE Voltage Sense

An optional filter capacitor CVSENSE is recommended to be placed between the board connector and DVSENSE to GND for increased

19 VS1 Power Supply Pin 1

20 VS2 Power Supply Pin 2 This pin is the device power supply pin 2. VS2 supplies the High Side Drivers (HSx).

21 HS1 High Side Output 1

22 HS2 High Side Output 2

23 HSUP Hall Sensor Supply Output

available on all device configurations.

24 LIN LIN Bus I/O

internally connected to PGND via a back to back diode.

26 PTB0 General Purpose I/O 0

PTB0 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor.
AD0 - Analog Input Channel 0, 0…2.5V (ADC2p5) analog input
TIM0CH0 - Timer Channel 0 Input/Output
Rx - Selectable connection to LIN / SCI See Section 4.18, “General Purpose I/O - PTB[0…2] .

27 PTB1 General Purpose I/O 1

PTB1 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor.
AD1 - Analog Input Channel 1, 0…2.5 V (ADC2p5) analog input
TIM0CH1 - Timer Channel 1 Input/Output
Tx - Selectable connection to LIN / SCI See Section 4.18, “General Purpose I/O - PTB[0…2] .

28 PTB2 General Purpose I/O 2

PTB2 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor.
AD2 - Analog Input Channel 2, 0…2.5V (ADC2p5) analog input
TIM0CH2 - Timer Channel 2 Input/Output
PWM - Selectable connection to PWM Channel 0 or 1 See Section 4.18, “General Purpose I/O - PTB[0…2] . 29 ADC2p5 ADC Reference Voltage This pin represents the ADC reference voltage and has to be connected to a filter capacitor. See Section 4.20, “Analog Digital Converter - ADC 30 AGND Analog Ground Pin This pin is the device Analog to Digital converter ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode.

31 L0 High Voltage Input 0

L0 - Digital High Voltage Input 0. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7)
AD3 - Analog Input 3 with selectable divider for 0…5.0 V and 0…18 V measurement range.
WU0 - Selectable Wake-up input 0 fo r wake up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx

32 L1 High Voltage Input 1

L1 - Digital High Voltage Input 1. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7)
AD4 - Analog Input 4 with selectable divider for 0…5.0 V and 0…18 V measurement range.
WU1 - Selectable Wake-up input 1 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx

33 L2 High Voltage Input 2

L2 - Digital High Voltage Input 2. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7)
AD5 - Analog Input 5 with selectable divider for 0…5.0 V and 0…18 V measurement range.
WU2 - Selectable Wake-up input 2 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations.

34 L3 High Voltage Input 3

L3 - Digital High Voltage Input 3. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7)
AD6 - Analog Input 6 with selectable divider for 0…5.0 V and 0…18 V measurement range.
WU3 - Selectable Wake-up input 3 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations.

35 L4 High Voltage Input 4

L4 - Digital High Voltage Input 4. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7)
AD7 - Analog Input 7 with selectable divider for 0…5.0 V and 0…18 V measurement range.
WU4 - Selectable Wake-up input 4 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations.

36 L5 High Voltage Input 5

L5 - Digital High Voltage Input 5. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7)
AD8 - Analog Input 8 with selectable divider for 0…5.0 V and 0…18 V measurement range.
WU5 - Selectable Wake-up input 5 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations. Note: 7. An optional filter capacitor CLX is recommended to be plac ed between the board connector and RLX to GND for increased ESD performance.

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 11

2.2 MCU Die Signal Properties

This section describes the external MCU signals. It includes a table of signal properties.

37 LS1 Low Side Output 1

Low Side output 1 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.13, “Low Side Drivers - LSx 38 PGND Power Ground Pin This pin is the device Low Side Ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode.

39 LS2 Low Side Output 2

Low Side output 2 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.13, “Low Side Drivers - LSx

40 ISENSEL Current Sense Pin L

Current Sense differential input “Low”. This pin is used in combination with ISENSEH to measure the voltage drop across a shunt resistor. See Section 4.21, “Current Sense Module - ISENSE. Note: This pin function is not available on all device configurations.

41 ISENSEH Current Sense Pin H

Current Sense differential input “High”. This pin is used in combination with ISENSEL to measure the voltage drop across a shunt resistor. Section 4.21, “Current Sense Module - ISENSE. Note: This pin function is not available on all device configurations. 42 NC Not connected This pin is reserved for alter native function and should be left floating. 43 TEST_A Test Mode Analog die Test Mode pin for Test Mode only. This pin must be grounded in user mode!

44 TCLK Test Clock Input

Test Mode Clock Input pin for Test Mode only. The pin can be used to disable the internal watchdog for development purpose in user mode. See Section 4.10, “Window Watchdog. The pin is recommended to be grounded in user mode. 45 RESET_A Reset I/O Bidirectional Reset I/O pin of the analog die. Active low signal. Internal pull-up. VDDX based. See Section 4.8, “Resets. To be externally connected to the RESET pin.

46 RESET MCU Reset

The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device to EVDDX.

47 BKGD MCU Background Debug

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET . The BKGD pin has a pull-up device. 48 PA7 MCU PA7 General purpose port A input or output pin 7. See Section 4.28, “Port Integration Module (S12IPIMV1) Table 5. Signal Properties Summary

Description

OSCPINS_EN DOWN Port E I/O, Oscillator pin PE1 XTAL V DDRX PUPBE/ OSCPINS_EN DOWN Port E I/O, Oscillator pin RESET — VDDRX PULLUP External reset TEST — N.A. RESET pin DOWN Test input BKGD MODC VDDRX BKPUE UP Background debug PA7 — VDDRX NA NA Port A I/O

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 12 PA6 — VDDRX NA NA Port A I/O PA5 — VDDRX NA NA Port A I/O PA4 — VDDRX NA NA Port A I/O PA3 SS VDDRX NA NA Port A I/O, SPI PA2 SCK VDDRX NA NA Port A I/O, SPI PA1 MOSI VDDRX NA NA Port A I/O, SPI PA0 MISO VDDRX NA NA Port A I/O, SPI PC1 D2DINT VDDD2D PUPCE/ D2DEN Disabled Port C I/O, D2DI PC0 D2DCLK VDDD2D NA NA Port C I/O, D2DI PD7-0 D2DDAT7-0 VDDD2D PUPDE/ D2DEN Disabled Port D I/O, D2DI

3 Electrical Characteristics

3.1 General

3.2 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. to ground, unless otherwise noted. Table 6. Absolute Maximum Electrical Ratings - Analog Die

See Section 3.9, “Additional Test Information ISO7637-2

3.3 Operating Conditions

Table 7. Maximum Electrical Ratings - MCU Die(9)

5.0 V Supply Voltage (Supplying the MCU internal regulator for core and

All digital I/O pins are internally clamped to VSSRX and VDDRX.

Table 8. Maximum Thermal Ratings

Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

Freescale’s Package Reflow capability meets Pb-free requi rements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 9. Operating Conditions

During power up and power down sequence always V DDD2D < VDDRX
f BUSMAX frequency ratings differ by device and is specified in Table 1

3.4 Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for the measurements.

3.4.1 Measurement Conditions

executed from RAM, unless otherwise noted.

3.5 Static Electrical Characteristics

5 . 5 V  VSUP  18 V
- 4 0 ° C  TA  125 °C (MM912x634xMxxx)
- 4 0 ° C  TA  105 °C (MM912x634xVxxx) Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. Operating Ambient Temperature MM912x634xMxxx MM912x634xVxxx TA -40 to 125 -40 to 105 Operating Junction Temperature - Analog Die T J_A -40 to 150 C Operating Junction Temperature - MCU Die T J_M -40 to 150 C

Table 10. Supply Currents

Typical values noted reflect the approximate parameter mean at TA = 25 °C
f BUSMAX frequency ratings differ by device and is specified in Table 1
I RUN_M denotes the sum of the currents flowing into VDD and VDDX.
I STOP_M denotes the sum of the currents flowing into VDD and VDDX.

Electrical Characteristics

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 16

3.5.1 Static Electrical Characteristics Analog Die

Table 11. Static Electrical Characteristics - Power Supply Table 12. Static Electrical Characteristics - Resets Table 13. Static Electrical Characteristics - Window Watchdog Table 14. Static Electrical Characteristics - Voltage Regulator 5.0 V (VDDX)

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 17 Load Regulation Normal Mode, 1.0 mA < IVDDX < 80 mA Normal Mode, VSUP = 3.6 V, 1.0 mA < I VDDX < 40 mA Stop Mode, 0.1 mA < IVDDX < 500 µA LDXRUN LDXCRK LDXSTOP 200 250 mV External Capacitor C VDDX 1.0 - 10 µF External Capacitor ESR C VDDX_R -- 1 0 O h m Table 15. Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD) Table 16. Static Electrical Characteristics - Hall Sensor Supply Output - HSUP

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 18 Table 17. Static Electrical Characteristics - High Side Drivers - HS Table 18. Static Electrical Characteristics - Low Side Drivers - LS Table 19. Static Electrical Characteristics - LIN Physical Layer Interface - LIN

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 19 Table 20. Static Electrical Characteristics - High Voltage Inputs - Lx

The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity are guaranteed without the optional capacitor.

Table 21. Static Electrical Characteristics - General Purpose I/O - PTB[0…2]

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 20 Table 22. Static Electrical Characteristics - Analog Digital Converter - ADC(19)

5.5 V < VSUP < 27 V

No external load allowed on the ADC2p5 pin.
Reduced ADC frequency will lower measurement error.

Table 23. Static Electrical Characteristics - Current Sense Module - ISENSE

RES = 2.44 mV/(GAIN*R SHUNT)

Table 24. Static Electrical Characteristics - Temperature Sensor - TSENSE

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 21

3.5.2 Static Electrical Characteristics MCU Die

3.5.2.1 I/O Characteristics

This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Temperature represented by a ADCIN Voltage of 1.984 V(22) T1.984V 145 150 155 °C Note: 22. Guaranteed by design and characterization. Table 25. Static Electrical Characteristics - Supply Voltage Sense - VSENSE and VS1SENSE

The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity is guaranteed without the optional capacitor.

Table 26. 5.0 V I/O Characteristics for PTA, PTE, RESET and BKGD Pins

Refer to Section 3.8, “ESD Protection and Latch-up Immunity” for more details.

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 22

3.5.2.2 Electrical Specification for MCU internal Voltage Regulator

The LVR monitors the voltages VDD_CORE, VDDFLASH and VDDRX. As soon as voltage drops on these supplies which would prohibit the correct function of the microcontroller, the LVR is triggering a reset.

3.5.2.3 Chip Power-up and Voltage Drops

LVI (low voltage interrupt), POR (power-on reset) and LVRs (low voltage reset) handle chip power-up or drops of the supply voltage. Figure 4. MC9S12I32 - Chip Power-up and Voltage Drops (not scaled) Table 27. IVREG Characteristics

Device functionality is guaranteed on power down to the LVR assert level.
Monitors VDDRX, active only in Full Performanc e mode. MCU is monitored by the POR in RPM (see Figure ).
Monitors VDDRX, active only in Full Performance mode. V LVRA and VPORD.
Monitors MCU_CORE_VDD . Active in all modes.

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 23

3.6 Dynamic Electrical Characteristics

Dynamic characteristics noted under conditions 5.5 V  VSUP  18 V, -40 °C  TA 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

3.6.1 Dynamic Electrical Characteristics Analog Die

Table 28. Dynamic Electrical Characteristics - Modes of Operation Table 29. Dynamic Electrical Characteristics - Power Supply(29) Table 30. Dynamic Electrical Characteristics - Die to Die Interface - D2D

f BUSMAX frequency ratings differ by device and is specified in Table 1

Table 31. Dynamic Electrical Characteristics - Resets Table 32. Dynamic Electrical Characteristics - Wake-up / Cyclic Sense

No trimming possible in Sleep mode.

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 24 Table 33. Dynamic Electrical Characteristics - Window Watchdog Table 34. Dynamic Electrical Characteristics - High Side Drivers - HS Table 35. Dynamic Electrical Characteristics - Low Side Drivers - LS Table 36. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 6.

7.0 V VSUP18 V; tBit = 50 µs;

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 8.

7.6 V VSUP18 V; tBIT = 50 µs

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 7.

7.0 V VSUP18 V; tBIT = 96 µs

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 25 Figure 5. Test Circuit for Timing Measurements Figure 6. LIN Timing Measurements for Normal Baud Rate

7.6 V VSUP18 V; tBIT = 96 µs

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 27

3.6.2 Dynamic Electrical Characteristics MCU Die

3.6.2.1 NVM

3.6.2.1.1 Timing Parameters

The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this derived clock must be set within the limits specified as fNVMOP. The NVM module does not have any means to monitor the frequency and will not prevent program or erase operations at frequencies above or below the specified minimum. When attempting to program or erase the NVM module at a lower frequency, a full program or erase transition is not assured. The following sections provide equations which can be used to determine the time required to execute specific flash commands. All timing parameters are a function of the bus clock frequency, fNVMBUS. All program and erase times are also a function of the NVM operating frequency, fNVMOP. A summary of key timing parameters can be found in Table . The time required to perform a blank check on all blocks is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify all blocks is given by: The time required to perform a blank check is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by: Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by: Table 37. Dynamic Electrical Characteristics - General Purpose I/O - PTB[0…2] (34) Table 38. Dynamic Electrical Characteristics - Analog Digital Converter - ADC(36)

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 28 The maximum time to erase verify a section of P-Flash depends on the number of phrases being verified (NVP) and is given by: The maximum read once time is given by: The programming time for a single phrase of four P-Flash words and the two seven-bit ECC fields is dependent on the bus frequency, fNVMBUS, as well as on the NVM operating frequency, fNVMOP. The typical phrase programming time is given by: The maximum phrase programming time is given by: The maximum time required to program a P-Flash Program Once field is given by: The time required to erase all blocks is given by: The time required to erase the P-Flash block is given by: tdcheck 2800 1 fNVMBUS t 450 NVP+ 1 fNVMBUS t 400 1 fNVMBUS tppgm 164 1 fNVMOP fNVMBUS tppgm 164 1 fNVMOP fNVMBUS t 164 1 fNVMOP fNVMBUS tmass 100100 1 fNVMOP fNVMBUS tpmass 100100 1 fNVMOP fNVMBUS

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 29 The typical time to erase a 512-byte P-Flash sector is given by: The maximum time to erase a 512-byte P-Flash sector is given by: The maximum time required to erase and unsecure the Flash is given by: The maximum verify back door access key time is given by: The maximum set user margin level time is given by: The maximum set field margin level time is given by: The time required to Erase Verify D-Flash for a given number of words NW is given by: D-Flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, since programming across a row boundary requires extra steps. The D-Flash programming time is specified for different cases: 1,2,3,4 words and 4 words across a row boundary. The typical D-Flash programming time is given by the following equation, where NW denotes the number of words; BC=0 if no row boundary is crossed and BC=1 if a row boundary is crossed: tpera 20020 1 fNVMOP fNVMBUS tpera 20020 1 fNVMOP fNVMBUS tuns 100100 1 fNVMOP fNVMBUS t 400 1 fNVMBUS t 350 1 fNVMBUS t 350 1 fNVMBUS tdcheck 450 NW+ 1 fNVMBUS fNVMOP fNVMBUS +

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 30 The maximum D-Flash programming time is given by: Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given by: Maximum D-Flash sector erase times is given by: The D-Flash sector erase time is ~5.0 ms on a new device and can extend to ~20 ms as the flash is cycled.

3.6.2.1.2 NVM Reli ability Parameters

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors, and burn-in to screen early life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE All values shown in Table 40 are preliminary and subject to further characterization. Table 39. NVM Timing Characteristics (FTMRC)

Typical program and erase times are based on typical f NVMOP and maximum fNVMBUS.
Maximum program and erase times are based on minimum f NVMOP and maximum fNVMBUS.
The maximum device bus clo ck is specified as fBUS.
Typical value for a new device.

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 31

3.6.2.2 Phase Locked Loop

3.6.2.2.1 Jitte r Definitions

With each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency. Noise, voltage, temperature, and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods, as illustrated in Figure 10. Figure 10. Jitter Definitions Table 40. NVM Reliability Characteristics

T JAVG does not exceed 85 C in a typical temperature profile over the lifetime of a consumer, industrial or automotive application.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 C
Spec table quotes typical endurance evaluated at 25 C for this product family. For additional information on how Freescale defines

Typical Endurance, please refer to Engineering Bulletin EB619.

23 N - 1 N1

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 32 For N < 100, the following equation is a good fit for the maximum jitter: Figure 11. Maximum Bus Clock Jitter Approximation On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent.

3.6.2.2.2 Electri cal Characteristics for the PLL(45)

3.6.2.3 Electrical Characteristics for the IRC1M

Table 41. PLL Characteristics

the maximum device bus cloc k is specified as fBUS.
% deviation from target frequency.
f REF = 1.0 MHz, fBUS = 32 MHz equivalent fPLL = 64 MHz, REFRQ=00, SYNDIV=$1F, VCOFRQ=01, POSTDIV=$00.

Table 42. IRC1M Characteristics

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 33

3.6.2.4 Electrical Characteristics for the Oscillator (OSCLCP)

3.6.2.5 Reset Characteristics

3.6.2.6 SPI Timing

This section provides electrical parametrics and ratings for the SPI. In Table 45 the measurement conditions are listed.

3.6.2.6.1 Master Mode

In Figure 12 the timing diagram for master mode with transmission format CPHA = 0 is depicted. Table 43. OSCLCP Characteristics

These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements.
Only applies if EXTAL is externally driven.

Table 44. Reset and Stop Characteristics Table 45. Measurement Conditions

Timing specified for equal load on all SP I output pins. Avoid asymmetric load.

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 35

3.6.2.6.2 Slave Mode

In Figure 14 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. Figure 14. SPI Slave Timing (CPHA = 0) In Figure 15 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. Table 46. SPI Master Mode Timing Characteristics

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 36 Figure 15. SPI Slave Timing (CPHA = 1) In Table 47 the timing characteristics for slave mode are listed.

3.7 Thermal Protection Characteristics

reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. Table 47. SPI Slave Mode Timing Characteristics

0.5 t BUS added due to internal synchronization delay

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 37

3.8 ESD Protection a nd Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification, ESD stresses were performed for the Human Body Model (HBM), Machine Model (MM), Charge Device Model (CDM), as well as LIN transceiver specific specifications. A device will be defined as a failure if after exposure to ESD pulses, the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature, followed by hot temperature, unless specified otherwise in the device specification. Table 48. Thermal Characteristics - Voltage Regulators VDD (2.5 V) & VDDX (5.0 V)(52)

Guaranteed by characteriza tion. Functionality tested.

Table 49. ESD and Latch-up Protection Characteristics discharge, CZAP= 150 pF, RZAP = 330 .

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 38 ESD GUN - following IEC 61000-4-2 Test Specification(56), unpowered, contact discharge, CZAP= 150 pF, RZAP = 330  - LIN (with or without bus filter CBUS=220 pF) - VSENSE with serial RVSENSE (54) - VS1, VS2 with CVS - Lx with serial RLX ±8000 ±8000 ±8000 ±8000 V ESD GUN - following ISO10605 Test Specification(56), unpowered, contact discharge, CZAP= 150 pF, RZAP =2 . 0k - LIN (with or without bus filter CBUS=220pF) - VSENSE with serial RVSENSE (54) - VS1, VS2 with CVS - Lx with serial RLX ±6000 ±6000 ±6000 ±6000 V ESD GUN - following ISO10605 Test Specification (56), powered, contact discharge, CZAP= 330 pF, RZAP =2 . 0k - LIN (with or without bus filter CBUS=220 pF) - VSENSE with serial RVSENSE (54) - VS1, VS2 with CVS - Lx with serial RLX ±8000 ±8000 ±8000 ±8000 V Note: 53. Input Voltage Limit = -2.5 to 7.5 V. 54. With C VBAT (10…100 nF) as part of the battery path. 55. Certification available on request 56. Tested internally only; certification pending Table 49. ESD and Latch-up Protection Characteristics (continued)

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 39

3.9 Additional Test In formation ISO7637-2

Immunity against transients for the LIN, Lx, and VBAT, is specified according to the LIN Conformance Test Specification - Section LIN EMC Test Specification refer to the LIN Conformance Test Certification Report - available as separate document.

4 Functional Description and Application Information

4.1 Introduction

Die Overview through Section 4.26, “MM912_634 - Analog Die Trimming.

MCU Die Overview through Section 4.39, “Serial Peripheral Interface (S12SPIV5).

Sections concerning both dies or the complete device will not have a specific indication.

4.2 Device Register Maps

Table 50 shows the device register memory map overview for the 64 kByte MCU die (MC9S12I64). Table 50. Device Register Memory Map Overview

4.2.1 Detailed Module Register Maps

Table 51 to Table 73 show the detailed module maps of the MC9S12I64 MCU die. Table 51. 0x0000–0x0007 Port Integration Module (PIM) Map 1 of 3 Table 52. 0x000A–0x000B Memory Map Control (MMC) Map 1 of 2 Table 53. 0x000C–0x000D Port Integration Module (PIM) Map 2 of 3 Table 54. 0x000E–0x000F Reserved Table 55. 0x0010–0x001B Memory Map Control (MMC) Map 2 of 2

Table 56. 0x0016–0x0019 Reserved Table 57. 0x001A–0x001B Device ID Register (PARTIDH/PARTIDL) Table 58. 0x001C–0x001E Reserved Table 59. 0x001F Interrupt Module (INT) Table 60. 0x0020–0x002F Debug Module (DBG)

Table 61. 0x0030–0x033 Reserved Table 62. 0x0034–0x003F Clock and Power Management (CPMU) Map 1 of 2

Table 63. 0x0040–0x0D7 Reserved Table 64. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) Map 1 of 3

Table 65. 0x00E0–0x0E7 Reserved Table 66. 0x00E8–0x00EF Serial Peripheral Interface (SPI) Table 67. 0x00F0–0x0FF Reserved

Table 68. 0x0100–0x011F Flash Module (FTMRC)

Table 69. 0x0120 Port Integration Module (PIM) Map 3 of 3 Table 70. 0x0180–0x1EF Reserved Table 71. 0x01F0–0x01FF Clock and Power Management (CPMU) Map 2 of 2 Table 72. 0x01FD–0x1FF Reserved Table 73. 0x0200–0x03FF Die-To-Die Initiator Blocking and Non-Blocking Access Window

Table 74 shows the detailed module maps of the MM912_634 analog die. Table 74. Analog die Registers(57) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/

0 CTR3_E CTR3_2 CTR3_1 CTR3_0

Registers not shown are reserved and must not be accessed.

4.3 MM912_634 - Analog Die Overview

4.3.1 Introduction

and delivers application specific actuator control as well as input capturing.

4.3.2 System Registers

4.3.2.1 Silicon Revision Register (SRR)

4.3.3 Analog Die Options

The following section describes the differences between analog die options 1 and 2.

4.3.3.1 Current Sense Module

For device options with the current sense module not available, the following considerations are to be made. Table 75. Silicon Revision Register (SRR)

Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 76. SRR - Register Field Descriptions mask change. Read only, writing will have no effect. The first Full Mask will have the count 00. tweaks applied to the full mask.Read only, writing will have no effect. The first Full Mask will have the count 00. Table 77. Analog Die Options

4.3.3.1.1 Pinout considerations

4.3.3.1.2 Register Considerations

The Current Sense Register must remain in default (0x00) state. The Conversion Control Register - Bit 9 must always be written 0. The Conversion Complete Register - Bit 9 must be ignored. The ADC Data Result Reg 9 must be ignored.

4.3.3.1.3 Functional Considerations

The complete Current Sense Module is not available.
The ADC Channel 9 is not available.

4.3.3.2 Wake-up Inputs (Lx)

For device options with reduced number of wake up inputs (Lx), the following considerations are to be made.

4.3.3.2.1 Pinout considerations

4.3.3.2.2 Register Considerations

The Lx - Bit for the not available Lx input in the Lx Status Register must be ignored. Table 78. ISENSE - Pin Considerations Table 79. Lx - Pin Considerations

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 56 The Lx Control register for the not available Lx input must be written 0. A not available Lx input can not be selected as Wake-up Source and must have its LxWE bit set to 0. The Wake-up Source Register for not available Lx inputs must be ignored. The Conversion Control Register for the not available Lx analog input (3…8) must always be written 0. The Conversion Complete Register for the not available Lx analog input (3.8) must be ignored. The ADC Data Result Register for the not available Lx analog input (3.8) must be ignored.

4.3.3.2.3 Functional Considerations

For the not available Lx inputs, the following functions are limited:

No Wake-up feature / Cyclic Sense
No Digital Input
No Analog Input and conversion via ADC O f f s e t N a m e 76543210 0x08 LXR R 0 0 L5 L4 L3 L2 L1 L0 Lx Status Register W 0x09 LXCR R 0 0 L5DS L4DS L3DS L2DS L1DS L0DS Lx Control Register W 0x12 WCR R CSSEL L5WE L4WE L3WE L2WE L1WE L0WE Wake Up Control Register W 0x14 WSR R FWU LINWU L5WU L4WU L3WU L2WU L1WU L0WU Wake Up Source Register W 0x82 ACCR (hi) R CH15 CH14 CH12 CH11 CH10 CH9 CH8 ADC Conversion Ctrl Reg W 0x83 ACCR (lo) R CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 ADC Conversion Ctrl Reg W 0x84 ACCSR (hi) R CC15 CC14 0 CC12 CC11 CC10 CC9 CC8 ADC Conv Complete Reg W 0x85 ACCSR (lo) R CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 ADC Conv Complete Reg W 0x8C-0 x97 ADRx (hi) R adrx 9 adrx 8 adrx 7 adrx 6 adrx 5 adrx 4 adrx 3 adrx 2 ADC Data Result Register x W ADRx (lo) R adrx 1 adrx 0 0 0 0 0 0 0 ADC Data Result Register x W

4.4 Modes of Operation

mode both voltage regulators are turned off (VDD =V DDX =0V ) . into reset mode while the voltage regulator is turned back on. The selection of the different modes is controlled by the Mode Control Register (MCR). Figure 16 describes how transitions are done between the different operating modes. Figure 16. Modes of Operation and Transitions

4.4.1 Power Down Mode

MM912_634 analog die will enter Reset mode with the condition “Power On Reset - POR”.

4.4.2 Reset Mode

Low Voltage VDDX Reset - LVRX, WDR - Watchdog Reset, EXR - External Reset, and WUR - Wake-up Sleep Reset). VLVRX with VS1 > (VLVI + VLVI_H) for more than tVTO, the MM912_634 analog die will transit directly to Sleep mode.

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 58 The Reset Status Register (RSR) will indicate the source of the reset by individual flags.

POR - Power On Reset
LVR - Low Voltage Reset VDD
LVRX - Low Voltage Reset VDDX
WDR - Watchdog Reset
EXR - External Reset
WUR - Wake-up Sleep Reset See also Section 4.8, “Resets.

4.4.3 Normal Mode

In Normal mode, all MM912_634 analog die user functions are active and can be controlled by the D2D Interface. Both regulators (VDD and VDDX) are active and operate with full current capability. Once entered in Normal mode, the Watchdog will operate as a simple non-window watchdog with an initial timeout (tIWDTO) to be reset via the D2D Interface. After the initial reset, the watchdog will operate in standard window mode. See Section 4.10, “Window Watchdog for details.

4.4.4 Stop Mode

The Stop mode will allow reduced current consumption with fast startup time. In this mode, both voltage regulators (VDD and VDDX) are active, with limited current drive capability. In this condition, the MCU is supposed to operate in Low Power mode (STOP). NOTE To avoid any pending analog die interrupts prevent the MCU from entering MCU stop resulting in unexpected system behavior, the analog die IRQ sources should be disabled and the corresponding flags be cleared before entering stop. The device can enter in Stop mode by configuring the Mode Control Register (MCR) via the D2D Interface. The MCU has to enter a Low Power mode immediately afterwards executing the STOP instruction. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. While in Stop mode, the MM912_634 analog die will wake up on the following sources:

Lx - Wake-up (maskable with selectable cyclic sense)
Forced Wake-up (configurable timeout)
LIN Wake-up
D2D Wake-up (special command) After Wake-up from the sources listed above, the device will transit to Normal mode. Reset will wake up the device directly to Reset mode. See Section 4.9, “Wake-up / Cyclic Sense for details.

4.4.5 Sleep Mode

The Sleep mode will allow very low current consumption. In this mode, both voltage regulators (VDD and VDDX) are inactive. The device can enter into Sleep mode by configuring the Mode Control Register (MCR) via the D2D- Interface. During Sleep mode, all unused internal blocks are deactivated to allow the lowest possible consumption. Power consumption will decrease further if the Cyclic Sense or Forced Wake-up feature are disabled. While in Sleep mode, the MM912_634 analog die will wake up on the following sources:

Lx - Wake-up (maskable with selectable cyclic sense)
Forced Wake-up (configurable timeout)
LIN Wake-up After Wake-up from the sources listed above or a reset condition, the device will transit to Reset mode. See Section 4.9, “Wake-up / Cyclic Sense for details.

4.4.6 Analog Die Functionality by Operation Mode

4.4.7 Register Definition

4.4.7.1 Mode Control Register (MCR)

Table 80. Operation Mode Overview

Special init through non window watchdog.

Table 81. Mode Control Register (MCR)

Offset related to 0x0200 for blocking access and 0x3 00 for non blocking access within the global address space.

Table 82. MCR - Register Field Descriptions Mode Select - These bits will issue a transition from to the selected Operating Mode. 00 - Normal Mode. Only with effect in Stop Mode. Will issue Wake Up and transition to Normal Mode. 10 - Sleep Mode. Will initiate transition to Sleep Mode.

The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two

base clock cycles (fBASE) delay are required between WSR read and MCR write.

4.5 Power Supply

regulated supply. See Section 4.11, “Hall Sensor Supply Output - HSUP. ADC (VS1SENSE) to measure the VS1 pin voltage directly. See Section 4.24, “Internal Supply Voltage Sense - VS1SENSE. reference. See Section 4.25, “Internal Bandgap Reference Voltage Sense - BANDGAP. Section 4.20, “Analog Digital Converter - ADC.

LBI - Low Battery Interrupt, internally measured at VSENSE
LVI - Low Voltage Interrupt, internally measured at VS1
HVI - High Voltage Interrupt, internally measured at VS2
VROVI - Voltage Regulator Over-voltage Interrupt internally measured at VDD and VDDX
LVR - Low Voltage Reset, internally measured at VDD
LVRX - Low Voltage Reset, internally measured at VDDX
HTI - High Temperature Interrupt measured between the VDD and VDDX regulators
Over-temperature Shutdown measured between the VDD and VDDX regulators

Figure 17. MM912_634 Power Supply

VDD (2.5 V). External capacitors (CVDD) and (CVDDX) are required for proper regulation.

4.5.2 Power Up Behavior / Power Down Behavior - I64

To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 18 shows a standard power up and power down sequence. Figure 18. Power Up / Down Sequence VDDX is to low to guarantee RESET_A active (3;6). This is achieved with the following implementation.

The VDD regulator is enabled after VDDX has reached the V LVRX threshold (1).
Once VDD reaches V LRV, the RESET_A is released (2).
The MCU is also protected by the MCU_LVR. Power Down:
Once VDDX has reached the V LVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well.
The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. NOTE The behavior explained previously is essential for the MC9S12I64 MCU die used, as this MCU does have an internal regulator stage, but the LVR function only active in normal modeMC9S12I64. The shutdown behavior should be considered when sizing the external capacitors CVDD and CVDDX for extended low voltage operation. MCU_POR VLBI / VLVI Normal Operating Range (not to scale) VLVRX VLVR VPOR_A RESET_A VDDX VDDVSUP VPOR_MCU VROVX VROX 1 4 / VLVR_MCU MCU_LVR MCU_LVR MCU_POR

4.5.3 Register Definition

4.5.3.1 Voltage Control Register (VCR)

4.5.3.2 Voltage Status Register (VSR)

Table 83. Voltage Control Register (VCR)

Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 84. VCR - Register Field Descriptions Voltage Regulator Over-voltage Interrupt Enable — Enables the interrupt for the Regulator Over-voltage Condition. High Temperature Interrupt Enable — Enables the interrupt for the Voltage Regulator (VDD/VDDX) Temperature Warning. High Voltage Interrupt Enable — Enables the interrupt for the VS2 - High Voltage Warning. Low Voltage Interrupt Enable — Enables the interrupt for the VS1 - Low Voltage Warning. Low Battery Interrupt Enable — Enables the interrupt for the VSENSE - Low Battery Voltage Warning. Table 85. Voltage Status Register (VSR)

Offset related to 0x0200 for blocking access and 0x300 fo r non blocking access within the global address space.

Table 86. VSR - Register Field Descriptions 0 - No Voltage Regulator Over-voltage Condition present. 1 - Voltage Regulator Over-voltage Condition present. (VDD/VDDX). Reading the register will clear the HTI flag if present. See Section 4.7, “Interrupts for details. 0 - No High Temperature Condition present. 1 - High Temperature Condition present. HVI flag if present. See Section 4.7, “Interrupts for details. 0 - No High Voltage Condition present. 1 - High Voltage Condition present. LVI flag if present. See Section 4.7, “Interrupts for details. 0 - No Low Voltage Condition present. 1 - Low Voltage Condition present. the LBI flag if present. See Section 4.7, “Interrupts for details. 0 - No Low Battery Condition present. 1 - Low Battery Condition present.

Die to Die Interface - Target MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 64

4.6 Die to Die Interface - Target

The D2D Interface is the bus interface to the Microcontroller. Access to the MM912_634 analog die is controlled by the D2D Interface module. This section describes the functionality of the die-to-die target block (D2D).

4.6.1 Overview

The D2D is the target for a data transfer from the target to the initiator (MCU). The initiator provides a set of configuration registers and two memory mapped 256 Byte address windows. When writing to a window, a transaction is initiated sending a write command, followed by an 8-bit address, and the data byte or word is received from the initiator. When reading from a window, a transaction is received with the read command, followed by an 8-bit address. The target then responds with the data. The basic idea is that a peripheral located on the MM912_634 analog die, can be addressed like an on-chip peripheral. Features:

software transparent register access to peripherals on the MM912_634 analog die
256 Byte address window
supports blocking read or write, as well as non-blocking write transactions
4-bit physical bus width
automatic synchronization of the target when initiator starts driving the interface clock
generates transaction and error status as well as EOT acknowledge
providing single interrupt interface to D2D Initiator

4.6.2 Low Power Mode Operation

The D2D module is disabled in SLEEP mode. In Stop mode, the D2DINT signal is used to wake-up a powered down MCU. As the MCU could wake-up without the MM912_634 analog die, a special command will be recognized as a wake-up event during Stop mode. See Section 4.4, “Modes of Operation.

4.6.2.1 Normal Mode / Stop Mode

While in Normal or Stop mode, D2DCLK acts as input only with pull present. D2D[3:0] operates as an input/output with pull-down always present. D2DINT acts as output only. NOTE The maximum allowed clock speed of the interface is limited to fD2D.

4.6.2.2 Sleep Mode

While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption. ANALOGMCU

4.7 Interrupts

4.7.1 Interrupt Source Identification

Once an Interrupt is signalized, there are two options to identify the corresponding source(s).

4.7.1.1 Interrupt Source Mirror

access is necessary to serve the specific module. identified by reading the Voltage Status Register - VSR.

4.7.1.1.1 Interrupt Source Register (ISR)

Table 87. Interrupt Source Register (ISR)

Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 88. ISR - Register Field Descriptions

Low Battery Interrupt
Low Voltage Interrupt
High Voltage Interrupt
Voltage Regulator Over-voltage Interrupt
Voltage Regulator High Temperature Interrupt 1 - CH0 CH0 - TIM Channel 0 Interrupt 2 - CH1 CH1 - TIM Channel 1 Interrupt 3 - CH2 CH2 - TIM Channel 2 Interrupt 4 - CH3 CH3 - TIM Channel 3 Interrupt 5 - TOV TOV - Timer Overflow Interrupt 6 - ERR ERR - SCI Error Interrupt 7 - TX TX - SCI Transmit Interrupt 8 - RX RX - SCI Receive Interrupt 9 - SCI SCI - ADC Sequence Complete Interrupt 10 - LINOT LINOT - LIN Driver Over-temperature Interrupt 11 - HSOT HSOT - High Side Over-temperature Interrupt 12 - LSOT LSOT - Low Side Over-temperature Interrupt 13 - HOT HOT - HSUP Over-temperature Interrupt ANALOGMCU

4.7.1.2 Interrupt Vector Emulation by Priority

not acknowledge an interrupt. An additional D2D access is necessary to serve the specific module.

4.7.1.2.1 Interrupt Vector Register (IVR)

The following table is listing all MM912_634 analog die interrupt sources with the corresponding priority.

4.7.2 Interrupt Sources

4.7.2.1 Voltage Status Interrupt (VSI)

Table 89. Interrupt Vector Register (IVR)

Offset related to 0x0200 for bloc king access and 0x300 for non blocking access within the global address space.

Table 90. IVR - Register Field Descriptions Represents the highest prioritized interrupt pending. See Table 91 In case no interrupt is pending, the result will be 0. Table 91. Interrupt Source Priority

MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 67 interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information.

4.7.2.2 Low Voltage Interrupt (LVI)

Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information.