MM912F634

MM912F634 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 335

Technical content

Features

• 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM
• Background Debug (BDM) & Debug Module (DBG)
• Die to Die bus interface for transparent memory mapping
• On-chip oscillator & two independent watchdogs
• LIN 2.1 Physical Layer Interface with integrated SCI
• Six digital MCU GPIOs shared with SPI (PA5…0)
• 10-Bit, 15 Channel - Analog to Digital Converter (ADC)
• 16-Bit, 4 Channel - Timer Module (TIM16B4C)
• 8-Bit, 2 Channel - Pulse width modulation module (PWM)
• Six high voltage / Wake-up inputs (L5.0)
• Three low voltage GPIOs (PB2.0)
• Low Power Modes with cycl ic sense & forced wake-up
• Current Sense Module with selectable gain
• Reverse Battery protected Voltage Sense Module
• Two protected low side outputs to drive inductive loads
• Two protected high side outputs
• Chip temperature sensor
• Hall sensor supply
• Integrated voltage regulator(s)

Figure 1. Simplified Application Diagram

ORDERING INFORMATION

M PA0/MISO RESET_A RESET VDD EVDD EVSS LIN LS1 LS2 ISENSEH1 VS1Power Supply LIN interface 5V digital I/O LGND ISENSEL1 HSUP Analog/Digital Inputs (High Voltage- and Wake Up capable) DGND L31 L21 PTB1/AD1/TX/TIM0CH1 PTB2/AD2/PWM/TIM0CH2 Hall Sensor supply 5V GPI/O with optional pull-up (shared with ADC, PWM, Timer, SCI) Low-Side Drivers Current Sense Module PTB0/AD0/RX/TIM0CH0 L0PA1/MOSI PA2/SCK PA3/SS PA4 BKGD/MODC EXTAL XTAL VDDX EVDDX EVSSX 5V Supply Reset HS1 HS21 12V Light/LED and switch supply Debug and external Oscillator VSENSE1 TEST L41 L51 VS2 TEST_A TCLK Hall Sensor Hall Sensor 2.5V Supply Digital Ground ADC2p5 AGND ADC Supply PGND MCU Test Analog Test Battery Sense PA5 1) Feature not available in all Analog Options MM912F634

1 Ordering Information

The device part number is following the standard scheme below: Figure 2. Part Number Scheme Table 1. Ordering Information Table 2. Analog Options(2)

1. This table only highlight s the analog die differences between the derivatives. See

Section 4.2.3, “Analog Die Options" for detailed information.

Figure 3. Device Block Diagram

4 Channel Timer

2 Channel

2 Pin Assignment

Figure 4. MM912F634 Pin Out

2.1 MM912F634 Pin Description

Table 3. MM912F634 Pin Description Section 4.33, “External Oscillator (S12SS12SCRGV1)". Section 4.33, “External Oscillator (S12SS12SCRGV1)". pin must be tied to EVSS in user mode.

7 PA3 MCU PA3 / SS Pin General purpose port A input or output pin 3, shared with the SS signal of the

11 EVSSX MCU 5.0 V Ground Pin Ground for the MCU 5.0 V power supply. 13 EVSS MCU 2.5 V Ground Pin Ground for the MCU 2.5 V power supply.

15 VDD Voltage Regulator

Section 4.4, “Power Supply".

16 VDDX Voltage Regulator Output

Section 4.4, “Power Supply". LGND, and AGND are internally connected to PGND via a back to back diode.

20 VS2 Power Supply Pin 2 This pin is the device power s upply pin 2. VS2 supplies the High Side Drivers (HSx). Section 4.10, “Hall Sensor Supply Output - HSUP". “LIN Physical Layer Interface - LIN". internally connected to PGND via a back to back diode.

• PTB0 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor.
• AD0 - Analog Input Channel 0, 0…2.5 V (ADC2p5) analog input
• TIM0CH0 - Timer Channel 0 Input/Output
• Rx - Selectable connection to LIN / SCI See Section 4.17, “General Purpose I/O - PTB[0…2]" . 27 PTB1 General Purpose I/O 1 This is the General Purpos e I/O pin 1 based on VDDX with the following shared functions:
• PTB1 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor.
• AD1 - Analog Input Channel 1, 0…2.5 V (ADC2p5) analog input
• TIM0CH1 - Timer Channel 1 Input/Output
• Tx - Selectable connection to LIN / SCI See Section 4.17, “General Purpose I/O - PTB[0…2]" . 28 PTB2 General Purpose I/O 2 This is the General Purpos e I/O pin 2 based on VDDX with the following shared functions:
• PTB2 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor.
• AD2 - Analog Input Channel 2, 0…2.5 V (ADC2p5) analog input
• TIM0CH2 - Timer Channel 2 Input/Output
• PWM - Selectable connection to PWM Channel 0 or 1 See Section 4.17, “General Purpose I/O - PTB[0…2]" . 29 ADC2p5 ADC Reference Voltage This pin represents the AD C reference voltage and has to be connected to a filter capacitor. See Section 4.19, “Analog Digital Converter - ADC" 30 AGND Analog Ground Pin This pin is t he device Analog to Digital Converter ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode.

Table 3. MM912F634 Pin Description (continued)

31 L0 High Voltage Input 0 This pins is the High Volt age Input 0 with the following shared functions:

• L0 - Digital High Voltage Input 0. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4)
• AD3 - Analog Input 3 with selectable divider for 0…5.0 V and 0…18 V measurement range.
• WU0 - Selectable Wake-up input 0 fo r wake up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx"

32 L1 High Voltage Input 1 This pins is the High Volt age Input 1 with the following shared functions:

• L1 - Digital High Voltage Input 1. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4)
• AD4 - Analog Input 4 with selectable divider for 0…5.0 V and 0…18 V measurement range.
• WU1 - Selectable Wake-up input 1 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx"

33 L2 High Voltage Input 2 This pins is the High Volt age Input 2 with the following shared functions:

• L2 - Digital High Voltage Input 2. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4)
• AD5 - Analog Input 5 with selectable divider for 0…5.0 V and 0…18 V measurement range.
• WU2 - Selectable Wake-up input 2 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx".

34 L3 High Voltage Input 3 This pins is the High Volt age Input 3 with the following shared functions:

• L3 - Digital High Voltage Input 3. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4)
• AD6 - Analog Input 6 with selectable divider for 0…5.0 V and 0…18 V measurement range.
• WU3 - Selectable Wake-up input 3 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx".

35 L4 High Voltage Input 4 This pins is the High Volt age Input 4 with the following shared functions:

• L4 - Digital High Voltage Input 4. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4)
• AD7 - Analog Input 7 with selectable divider for 0…5.0 V and 0…18 V measurement range.
• WU4 - Selectable Wake-up input 4 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available on all device configurations.

36 L5 High Voltage Input 5 This pins is the High Volt age Input 5 with the following shared functions:

• L5 - Digital High Voltage Input 5. When used as digital input, a series resistor (RLx) must be used to protect against automotive transients.(4)
• AD8 - Analog Input 8 with selectable divider for 0…5.0 V and 0…18 V measurement range.
• WU5 - Selectable Wake-up input 5 for wake-up and cyclic sense during low power mode. See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available on all device configurations. 37 LS1 Low Side Output 1 Low Side output 1 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.12, “Low Side Drivers - LSx" 38 PGND Power Ground Pin This pin is the device Lo w Side Ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode.

42 NC Not connected Pin This pin is reserved for alte rnative function and should be left floating. “Window Watchdog". The pin is recommended to be grounded in user mode. based. See Section 4.7, “Resets". To be externally connected to the RESET pin. pin has an internal pull-up device to EVDDX.

47 BKGD MCU Background Debug

debug communication. It is used as MCU operating mode select pin during reset. BKGD pin has a pull-up device.

1. An optional filter capacitor C VSENSE is recommended to be placed between the board connector and RVSENSE to GND for increased ESD
2. An optional filter capacitor C Lx is recommended to be placed between the board connector and RLx to GND for increased ESD

Pin Assignment MCU Die Signal Properties MM912F634 Freescale Semiconductor 10

2.2 MCU Die Signal Properties

This section describes the external MCU signals. It includes a table of signal properties. Table 4. Signal Properties Summary

Description

EXTAL — V DD NA NA Oscillator pins XTAL — V DD NA NA RESET —V DDX Pull-up External reset TEST — N.A. RESET pin Down Test input BKGD MODC V DDX Always on UP Background debug PA5 — V DDX NA NA Port A I/O PA4 — V DDX NA NA Port A I/O PA3 SS V DDX NA NA Port A I/O, SPI PA2 SCK V DDX NA NA Port A I/O, SPI PA1 MOSI V DDX NA NA Port A I/O, SPI PA0 MISO V DDX NA NA Port A I/O, SPI

3 Electrical Characteristics

3.1 General

3.2 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. to ground unless otherwise noted. Table 5. Absolute Maximum Electrical Ratings - Analog Die

3.3 Operating Conditions

Table 6. Maximum Electrical Ratings - MCU Die Table 7. Maximum Thermal Ratings

1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requi rements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC34xxxD enter 34xxx), and review parametrics. Table 8. Operating Conditions

1. During power up and power down sequence always V DD < VDDX
2. f BUSMAX frequency ratings differ by device and is specified in Table 1

3.4 Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for the measurements.

3.4.1 Measurement Conditions

and the CPU code is executed from RAM. Table 9. Supply Currents

1. Typical values noted reflect the approximate parameter mean at T A =2 5° C
2. I RUN_M denotes the sum of the currents flowing into VDD and VDDX.
3. I STOP_M denotes the sum of the currents flowing into VDD and VDDX.
4. I WAIT_M denotes the sum of the currents flowing into VDD and VDDX.
5. f BUSMAX frequency ratings differ by device and is specified in Table 1.

3.5 Static Electrical Characteristics

values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted.

3.5.1 Static Electrical Characteristics Analog Die

Table 10. Static Electrical Characteristics - Power Supply Table 11. Static Electrical Characteristics - Resets Table 12. Static Electrical Characteristics - Window Watchdog Table 13. Static Electrical Characteristics - Voltage Regulator 5V (VDDX)

Table 14. Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD) Table 15. Static Electrical Characteristics - Hall Sensor Supply Output - HSUP Table 13. Static Electrical Characteristics - Voltage Regulator 5V (VDDX) (continued)

Table 16. Static Electrical Characteristics - High Side Drivers - HS Table 17. Static Electrical Characteristics - Low Side Drivers - LS Table 18. Static Electrical Characteristics - LIN Physical Layer Interface - LIN

1. Considering drop from VBAT to LIN, at very low VBAT level, t he internal logic will detect a dominant as the threshold will not decrease

Table 19. Static Electrical Characteristics - High Voltage Inputs - Lx

7.0 V ≤ VSUP ≤ 27 V

5.5 V ≤ VSUP ≤ 7V

5.5 V ≤ VSUP ≤ 27 V

1. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" are guaranteed without the optional capacitor.

Table 20. Static Electrical Characteristics - General Purpose I/O - PTB[0…2]

Table 21. Static Electrical Characteristics - Analog Digital Converter - ADC(16)

5.5 V < VSUP < 27 V

1. No external load allowed on the ADC2p5 pin.
2. Reduced ADC frequency will lower measurement error.

Table 22. Static Electrical Characteristics - Current Sense Module - ISENSE

1. RES = 2.44 mV/(GAIN*R SHUNT)

Table 23. Static Electrical Characteristics - Temperature Sensor - TSENSE

1. Guaranteed by design and characterization.

Table 24. Static Electrical Characteristics - Supply Voltage Sense - VSENSE and VS1SENSE

1. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" is guaranteed without the optional capacitor.

3.5.2 Static Electrical Characteristics MCU Die

3.5.2.1 I/O Characteristics

This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Table 25. 5.0 V I/O Characteristics for PTA, RESET and BKGD Pins

1. Refer to Section 3.8, “ESD Protection and Latch-up Immunity"” for more details.

3.6 Dynamic Electrical Characteristics

Dynamic electrical characteristics noted under conditions 5.5V ≤ VSUP ≤ 18 V, -40 °C ≤ TA ≤ 105 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted.

3.6.1 Dynamic Electrical Characteristics Analog Die

Table 26. Dynamic Electrical Characteristics - Modes of Operation Table 27. Dynamic Electrical Characteristics - Power Supply Table 28. Dynamic Electrical Characteristics - Die to Die Interface - D2D

1. f BUSMAX frequency ratings differ by device and is specified in Table 1

Table 29. Dynamic Electrical Characteristics - Resets Table 30. Dynamic Electrical Characteristics - Wake-up / Cyclic Sense

1. Trimming parameters are not available in Sleep mode.

Table 31. Dynamic Electrical Characteristics - Window Watchdog Table 32. Dynamic Electrical Characteristics - High Side Drivers - HS Table 33. Dynamic Electrical Characteristics - Low Side Drivers - LS Table 34. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 6.

7.0 V ≤ VSUP ≤ 18 V; tBit = 50 µs;

7.6 V ≤ VSUP ≤ 18 V; tBIT = 50 µs

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 7.

7.0 V ≤ VSUP ≤ 18 V; tBIT = 96 µs

7.6 V ≤ VSUP ≤ 18 V; tBIT = 96 µs

3.6.2 Dynamic Electrical Characteristics MCU Die

3.6.2.1 NVM Timing

the NVM modules at a lower frequency, a full program, or erase transition is not assured. The Flash program and erase operations are timed using a clock derived from the bus clock using the FCLKDIV and register. The frequency of this clock must be set within the limits specified as fNVMOP. maximum times are calculated for minimum fNVMOP and a fBUS of 2.0 MHz.

3.6.2.1.1 Single Word Programming

and can be calculated according to the following formula. Table 35. Dynamic Electrical Characteristics - General Purpose I/O - PTB[0…2] Table 36. Dynamic Electrical Characteristics - Analog Digital Converter - ADC

Electrical Characteristics Dyna mic Electrical Characteristics MM912F634 Freescale Semiconductor 26

3.6.2.1.2 Burst Programming

This applies only to the Flash, where up to 64 words in a row can be programmed consecutively, using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: The time to program a whole row is: Burst programming is more than 2 times faster than single word programming.

3.6.2.1.3 Sector Erase

The sector erase cycle is divided into 16 individual erase pulses to achieve faster system response during the erase flow. The given erase time (tERA) specifies the time considering consecutive pulses. Erasing a 512-byte Flash sector takes: The setup time can be ignored for this operation.

3.6.2.1.4 Mass Erase

Erasing a NVM block takes: The setup time can be ignored for this operation. tbwpgm 4 1 fNVMOP fbus tbrpgm tswpgm 63 t bwpgm⋅+= tera 4000 1 fNVMOP tmass 20000 1 fNVMOP

3.6.2.1.5 Blank Check

address zero. It takes one bus cycle per word to verify plus a setup of the command. Table 37. NVM Timing Characteristics

1. Minimum programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fBUS.
2. The sector erase cycle is divided into 16 individual erase pulses to achieve faster system response during the erase flow. The given

erase time (tERA) specifies the time considering consecutive pulses.

1. Minimum erase times are achieved under maximum NVM operating frequency, fNVMOP.
2. Minimum time, if first word in the array is not blank.
3. Maximum time to complete check on an erased block.

3.6.2.2 NVM Reliability

Figure 10. Typical Flash Cycling Endurance vs. Temperature Table 38. NVM Reliability Characteristics

1. T JAVG is the Average Junction Temperature
2. T JAVG will not exceed 85 °C considering a typical temperature profile over the lifetime of a consumer, industrial, or automotive application.
3. Typical data retention values are based on intrinsic capabili ty of the technology measured at high temperature and de-rated to 25 °C, using

the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, refer to Engineering Bulletin EB618.

1. Spec table quotes typical endur ance evaluated at 25 °C for this product family, typical endurance at various temperature can be estimated

using the graph in Figure 10. For additional information on how Freescale defines Typical Endurance, refer to Engineering Bulletin EB619.

3.6.2.3 Reset, Oscillator and Internal Clock Generation

3.6.2.3.1 Startup & FLL Characteristics

found in the Clock and Reset Generator (CRG) block description. Table 39. Startup & FLL Characteristics

1. Reference Frequency is factory trimmed
2. % deviation from target frequency, target frequency is f IREF_TRIM * (1000 + 2*MULT[6:0])
3. f DCO = 40 MHz, fIREF_TRIM = 32 kHz, MULT = $7D

3.6.2.3.2 Power On Reset

Figure 11. Power on Reset Table 40. Power On Reset Characteristics

3.6.2.3.3 Oscillator

monitor failure is asserted if the frequency is below the assert frequency fCMFA.

3.6.2.4 SPI Timing

This section provides electrical parameters and ratings for the SPI. Table 42 lists the measurement conditions. Table 41. Oscillator Characteristics Table 42. Measurement Conditions

1. Timing specified for equal load on all SP I output pins. Avoid asymmetric load.

3.6.2.4.1 Master Mode

Figure 12 depicts the timing diagram for master mode with transmission format CPHA = 0. Figure 12. SPI Master Timing (CPHA = 0) In Figure 13 depicts the timing diagram for master mode with transmission format CPHA=1. Figure 13. SPI Master Timing (CPHA = 1)

1. If configured as an output.

Table 43 lists the timing characteristics for master mode. Table 43. SPI Master Mode Timing Characteristics

3.6.2.4.2 Slave Mode

Figure 14 depicts the timing diagram for slave mode with transmission format CPHA = 0. Figure 14. SPI Slave Timing (CPHA = 0) Figure 15 depicts the timing diagram for slave mode with transmission format CPHA = 1. Figure 15. SPI Slave Timing (CPHA = 1)

Table 44 lists the timing characteristics for slave mode. Table 44. SPI Slave Mode Timing Characteristics

1. 0.5 t BUS added due to internal synchronization delay

3.7 Thermal Protection Characteristics

reflect the approximate parameter mean at TA = 25 °C under nominal conditions unless otherwise noted. Table 45. Thermal Characteristics - Voltage Regulators VDD (2.5 V) & VDDX (5.0 V)

1. Guaranteed by characterization. Functionality tested.

3.8 ESD Protection a nd Latch-up Immunity

Model (CDM), as well as LIN transceiver specific specifications. A device will be defined as a failure if after exposure to ESD pulses, the device no longer meets the device specification. followed by hot temperature, unless specified otherwise in the device specification. Table 46. ESD and Latch-up Protection Characteristics discharge, CZAP= 150 pF, RZAP = 330 Ω.

1. Input Voltage Limit = -2.5 to 7.5 V.
2. With C VBAT (10…100 nF) as part of the battery path.
3. Certification available on request
4. Tested internally only; certification pending

Freescale Semiconductor 38

3.9 Additional Test In formation ISO7637-2

For immunity against transients for the LIN, Lx, and VBAT is specified according to the LIN Conformance Test Specification - Section LIN EMC Test Specification refer to the LIN Conformance Test Certification Report - available as a separate document from ISO.

4 Functional Description and Application Information

4.1 Introduction

Die Overview" through Section 4.25, “MM912F634 - Analog Die Trimming".

• MCU Die Overview" through Section 4.38, “Serial Peripheral Interface (S12SPIV4)".

Sections concerning both dies or the complete device will not have a specific indication.

4.1.1 Device Register Maps

Table 47 shows the device register memory map overview for the 32 kByte MCU die (MC9S12I32). Table 47. Device Register Memory Map Overview

4.1.2 Detailed Module Register Maps

Table 48 to Table 65 show the detailed module maps of the MM912F634 MCU die. Table 48. 0x0000–0x0017 Port Integration Module (PIM) 1of 2 Table 49. 0x0018–0x001E Miscellaneous Peripheral Table 50. 0x001F Interrupt Module (S12SINT)

Table 51. 0x0020–0x002F Debug Module (S12XDBG)

1. This bit is visible at DBGCNT[7] and DBGSR[7]
2. This represents the contents if the Comparator A control register is blended into this address.
3. This represents the contents if the Comparator B control register is blended into this address.
4. This represents the contents if the Comparator C control register is blended into this address.

Table 52. 0x0030–0x0033 Module Mapping Control (S12SMMC) Table 53. 0x0034–0x003B Clock and Reset Generator (CRG) Table 54. 0x003C–0x003D Real Time Interrupt (RTI) Table 55. 0x003E–0x003F Computer Operating Properly (COP)

Table 56. 0x0040–0x00D7 Reserved Register Space Table 57. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) 1 of 3 Table 58. 0x00E0–0x00E7 Reserved Register Space Table 59. 0x00E8–0x00EF Serial Peripheral Interface (SPI)

Table 60. 0x00F0–0x00FF Reserved Register Space Table 61. 0x0100–0x0113 Flash Control & Status Register FTSR Table 59. 0x00E8–0x00EF Serial Peripheral Interface (SPI) (continued)

Table 65 shows the detailed module maps of the MM912F634 analog die. Table 62. 0x0114–0x011F Reserved Register Space Table 63. 0x0120–0x0123 Port Integration Module (PIM) 2 of 2 Table 64. 0x0124–0x01FF Reserved Register Space Table 65. Analog die Registers(55) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/ Table 61. 0x0100–0x0113 Flash Control & Status Register FTSR (continued)

1. Registers not shown are reserved and must not be accessed.

4.2 MM912F634 - Analog Die Overview

4.2.1 Introduction

delivers application specific actuator control as well as input capturing.

4.2.2 System Registers

4.2.2.1 Silicon Revision Register (SRR)

4.2.3 Analog Die Options

The following section describes the differences between analog die options 1 and 2. Table 66. Silicon Revision Register (SRR)

1. Offset related to 0x0200 for blocking access and 0x300 fo r non blocking access within the global address space.

Table 67. SRR - Register Field Descriptions mask change. Read only, writing will have no effect. The first Full Mask will have the count 00. tweaks applied to the full mask.Read only, writing will have no effect. The first Full Mask will have the count 00. Table 68. Analog Die Options (continued)

4.2.3.1 Current Sense Module

For device options with the current sense module not available, the following considerations are to be made.

4.2.3.1.1 Pinout considerations

4.2.3.1.2 Register Considerations

The Current Sense Register must remain in default (0x00) state. The Conversion Control Register - Bit 9 must always be written 0. The Conversion Complete Register - Bit 9 must be ignored. The ADC Data Result Reg 9 must be ignored. Table 69. ISENSE - Pin Considerations

4.2.3.1.3 Functional Considerations

• The complete Current Sense Module is not available.
• The ADC Channel 9 is not available.

4.2.3.2 Wake-up Inputs (Lx)

For device options with reduced number of wake up inputs (Lx), the following considerations are to be made.

4.2.3.2.1 Pinout Considerations

4.2.3.2.2 Register Considerations

The Lx - Bit for the not available Lx input in the Lx Status Register must be ignored. The Lx Control register for the not available Lx input must be written 0. A not available Lx input can not be selected as Wake-up Source and must have its LxWE bit set to 0. The Wake-up Source Register for not available Lx inputs must be ignored. The Conversion Control Register for the not available Lx analog input (3…8) must always be written 0. Table 70. Lx - Pin Considerations

Functional Description and Application Information MM912F634 - Analog Die Overview MM912F634 Freescale Semiconductor 54 The Conversion Complete Register for the not available Lx analog input (3.8) must be ignored. The ADC Data Result Register for the not available Lx analog input (3.8) must be ignored.

4.2.3.2.3 Functional Considerations

For the not available Lx inputs, the following functions are limited:

• No Wake-up feature / Cyclic Sense
• No Digital Input
• No Analog Input and conversion via ADC 0x84 ACCSR (hi) R CC15 CC14 0 CC12 CC11 CC10 CC9 CC8 ADC Conv Complete Reg W 0x85 ACCSR (lo) R CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 ADC Conv Complete Reg W 0x8C-0 x97 ADRx (hi) R adrx 9 adrx 8 adrx 7 adrx 6 adrx 5 adrx 4 adrx 3 adrx 2 ADC Data Result Register x W ADRx (lo) R adrx 1 adrx 0 0 0 0 0 0 0 ADC Data Result Register x W

4.3 Modes of Operation

into reset mode while the voltage regulator is turned back on. The selection of the different modes is controlled by the Mode Control Register (MCR). Figure 16 describes how transitions are done between the different operating modes. Figure 16. Modes of Operation and Transitions

4.3.1 Power Down Mode

MM912F634 analog die will enter Reset mode with the condition “Power On Reset - POR”.

4.3.2 Reset Mode

Low Voltage VDDX Reset - LVRX, WDR - Watchdog Reset, EXR - External Reset, and WUR - Wake-up Sleep Reset).

Functional Description and Application Information Modes of Operation MM912F634 Freescale Semiconductor 56 For internal reset sources, the RESET_A pin is driven low for tRST after the reset condition is gone. After this delay, the RESET_A pin is released. With a high detected on the RESET_A pin, VDD>VLVR and VDDX>VLVRX the MM912F634 analog die enters in Normal mode. To avoid short-circuit conditions being present for a long time, a tVTO timeout is implemented. Once VDD < VLVR or VDDX < VLVRX with VS1 > (VLVRI+ VLVR _H) for more than tVTO, the MM912F634 analog die will transit directly to Sleep mode. The Reset Status Register (RSR) will indicate the source of the reset by individual flags.

• POR - Power On Reset
• LVR - Low Voltage Reset VDD
• LVRX - Low Voltage Reset VDDX
• WDR - Watchdog Reset
• EXR - External Reset
• WUR - Wake-up Sleep Reset See also Section 4.7, “Resets".

4.3.3 Normal Mode

In Normal mode, all MM912F634 analog die user functions are active and can be controlled by the D2D Interface. Both regulators (VDD and VDDX) are active and operate with full current capability. Once entered in Normal mode, the Watchdog will operate as a simple non-window watchdog with an initial timeout (tIWDTO) to be reset via the D2D Interface. After the initial reset, the watchdog will operate in standard window mode. See Section 4.9, “Window Watchdog" for details.

4.3.4 Stop Mode

To avoid any pending analog die interrupts prevent the MCU from entering MCU stop resulting in unexpected system behavior, the analog die IRQ sources should be disabled and the corresponding flags be cleared before entering stop. The Stop mode will allow reduced current consumption with fast startup time. In this mode, both voltage regulators (VDD and VDDX) are active, with limited current drive capability. In this condition, the MCU is supposed to operate in Low Power mode (STOP or WAIT). The device can enter in Stop mode by configuring the Mode Control Register (MCR) via the D2D Interface. The MCU has to enter a Low Power mode immediately afterwards executing the STOP or WAIT instruction. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. While in Stop mode, the MM912F634 analog die will wake up on the following sources:

• Lx - Wake-up (maskable with selectable cyclic sense)
• Forced Wake-up (configurable timeout)
• LIN Wake-up
• D2D Wake-up (special command) After Wake-up from the sources listed above, the device will transit to Normal mode. Reset will wake up the device directly to Reset mode. See Section 4.8, “Wake-up / Cyclic Sense" for details.

4.3.5 Sleep Mode

The Sleep mode will allow very low current consumption. In this mode, both voltage regulators (VDD and VDDX) are inactive.

• Lx - Wake-up (maskable with selectable cyclic sense)
• Forced Wake-up (configurable timeout)
• LIN Wake-up After Wake-up from the sources listed above or a reset condition, the device will transit to Reset mode. See Section 4.8, “Wake-up / Cyclic Sense" for details.

4.3.6 Analog Die Functionality by Operation Mode

Table 71. Operation Mode Overview

1. Special init through non window watchdog.

4.3.7 Register Definition

4.3.7.1 Mode Control Register (MCR)

Table 72. Mode Control Register (MCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 73. MCR - Register Field Descriptions Mode Select - These bits will issue a transition from to the selected Operating Mode. 00 - Normal Mode. Only with effect in Stop Mode. Will issue Wake Up and transition to Normal Mode. 10 - Sleep Mode. Will initiate transition to Sleep Mode.

1. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two

base clock cycles (fBASE) delay are required between WSR read and MCR write.

Functional Description and Application Information Power Supply MM912F634 Freescale Semiconductor 59

4.4 Power Supply

The MM912F634 analog die supplies VDD (2.5 V), VDDX (5.0 V), and HSUP, based on the supply voltage applied to the VS1 pin. VDD is cascaded of the VDDX regulator. To separate the High Side outputs from the main power supply, the VS2 pin does only power the High Side drivers. Both supply pins have to be externally protected against reverse battery conditions. To supply external Hall Effect Sensors, the HSUP pin will supply a switchable regulated supply. See Section 4.10, “Hall Sensor Supply Output - HSUP". A reverse battery protected input (VSENSE) is implemented to measure the Battery Voltage directly. A serial resistor (RVSENSE) is required on this pin. See Section 4.22, “Supply Voltage Sense - VSENSE". In addition, the VS1 supply can be routed to the ADC (VS1SENSE) to measure the VS1 pin voltage directly. See Section 4.23, “Internal Supply Voltage Sense - VS1SENSE". To have an independent ADC verification, the internal sleep mode bandgap voltage can be routed to the ADC (BANDGAP). As this node is independent from the ADC reference, any out of range result would indicate malfunctioning ADC or Bandgap reference. See Section 4.24, “Internal Bandgap Reference Voltage Sense - BANDGAP". To stabilize the internal ADC reference voltage for higher precision measurements, the current limited ADC2p5 pin needs to be connected to an external filter capacitor (CADC2p5). It is not recommended to connect additional loads to this pin. See Section 4.19, “Analog Digital Converter - ADC". The following safety features are implemented:

• LBI - Low Battery Interrupt, internally measured at VSENSE
• LVI - Low Voltage Interrupt, internally measured at VS1
• HVI - High Voltage Interrupt, internally measured at VS2
• VROVI - Voltage Regulator Over-voltage Interrupt internally measured at VDD and VDDX
• LVR - Low Voltage Reset, internally measured at VDD
• LVRX - Low Voltage Reset, internally measured at VDDX
• HTI - High Temperature Interrupt measured between the VDD and VDDX regulators
• Over-temperature Shutdown measured between the VDD and VDDX regulators

Figure 17. MM912F634 Power Supply VDD (2.5 V). External capacitors (CVDD) and (CVDDX) are required for proper regulation.

4.4.2 Power Up Behavior / Power Down Behavior

To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 18 shows a standard power up and power down sequence.

Figure 18. Power Up / Down Sequence VDDX is to low to guarantee RESET_A active (3;6). This is achieved with the following implementation.

• The VDD regulator is enabled after VDDX has reached the V LVRX threshold (1).
• Once VDD reaches V LRV, the RESET_A is released (2). Power Down:
• Once VDDX has reached the V LVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well.
• The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. VLBI / VLVI Normal Operating Range (not to scale) VLVRX VLVR VPOR_A RESET_A VDDX VDDVSUP VPOR_MCU VROVX VROX MCU_POR 1 4 MCU_POR

4.4.3 Power Up Behavior / Power Down Behavior - I64

CVDDX for extended low voltage operation. To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 19 shows a standard power up and power down sequence. Figure 19. Power Up / Down Sequence VDDX is to low to guarantee RESET_A active (3;6). This is achieved with the following implementation.

• The VDD regulator is enabled after VDDX has reached the V LVRX threshold (1).
• Once VDD reaches V LRV, the RESET_A is released (2).
• The MCU is also protected by the MCU_LVR. Power Down:
• Once VDDX has reached the V LVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well.
• The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. MCU_POR VLBI / VLVI Normal Operating Range (not to scale) VLVRX VLVR VPOR_A RESET_A VDDX VDDVSUP VPOR_MCU VROVX VROX 1 4 / VLVR_MCU MCU_LVR MCU_LVR MCU_POR

4.4.4 Register Definition

4.4.4.1 Voltage Control Register (VCR)

Table 74. Voltage Control Register (VCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 75. VCR - Register Field Descriptions Voltage Regulator Over-voltage Interrupt Enable — Enables the interrupt for the Regulator Over-voltage Condition. High Temperature Interrupt Enable — Enables the interrupt for the Voltage Regulator (VDD/VDDX) Temperature Warning. High Voltage Interrupt Enable — Enables the interrupt for the VS2 - High Voltage Warning. Low Voltage Interrupt Enable — Enables the interrupt for the VS1 - Low Voltage Warning. Low Battery Interrupt Enable — Enables the interrupt for the VSENSE - Low Battery Voltage Warning.

4.4.4.2 Voltage Status Register (VSR)

Table 76. Voltage Status Register (VSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 77. VSR - Register Field Descriptions 0 - No Voltage Regulator Over-voltage Condition present. 1 - Voltage Regulator Over-voltage Condition present. (VDD/VDDX). Reading the register will clear the HTI flag if present. See Section 4.6, “Interrupts" for details. 0 - No High Temperature Condition present. 1 - High Temperature Condition present. HVI flag if present. See Section 4.6, “Interrupts" for details. 0 - No High Voltage Condition present. 1 - High Voltage Condition present. LVI flag if present. See Section 4.6, “Interrupts" for details. 0 - No Low Voltage Condition present. 1 - Low Voltage Condition present. the LBI flag if present. See Section 4.6, “Interrupts" for details. 0 - No Low Battery Condition present. 1 - Low Battery Condition present.

Functional Description and Application Information Die to Die Interface - Target MM912F634 Freescale Semiconductor 65

4.5 Die to Die Interface - Target

The D2D Interface is the bus interface to the Microcontroller. Access to the MM912F634 analog die is controlled by the D2D Interface module. This section describes the functionality of the die-to-die target block (D2D).

4.5.1 Overview

The D2D is the target for a data transfer from the target to the initiator (MCU). The initiator provides a set of configuration registers and two memory mapped 256 Byte address windows. When writing to a window, a transaction is initiated sending a write command, followed by an 8-bit address, and the data byte or word is received from the initiator. When reading from a window, a transaction is received with the read command, followed by an 8-bit address. The target then responds with the data. The basic idea is that a peripheral located on the MM912F634 analog die, can be addressed like an on-chip peripheral. Features:

• software transparent register access to peripherals on the MM912F634 analog die
• 256 Byte address window
• supports blocking read or write, as well as non-blocking write transactions
• 4 bit physical bus width
• automatic synchronization of the target when initiator starts driving the interface clock
• generates transaction and error status as well as EOT acknowledge
• providing single interrupt interface to D2D Initiator

4.5.2 Low Power Mode Operation

The D2D module is disabled in SLEEP mode. In Stop mode, the D2DINT signal is used to wake-up a powered down MCU. As the MCU could wake up without the MM912F634 analog die, a special command will be recognized as a wake-up event during Stop mode. See Section 4.3, “Modes of Operation".

4.5.2.1 Normal Mode / Stop Mode

The maximum allowed clock speed of the interface is limited to fD2D. While in Normal or Stop mode, D2DCLK acts as input only with pull present. D2D[3:0] operates as an input/output with pull-down always present. D2DINT acts as output only.

4.5.2.2 Sleep Mode

While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption.

4.6 Interrupts

the interrupt is acknowledged via the D2D-Interface. Interrupts are only asserted while in Normal mode.

4.6.1 Interrupt Source Identification

Once an Interrupt is signalized, there are two options to identify the corresponding source(s).

4.6.1.1 Interrupt Source Mirror

identified by reading the Voltage Status Register - VSR. access is necessary to serve the specific module.

4.6.1.1.1 Interrupt Source Register (ISR)

Table 78. Interrupt Source Register (ISR)

1. Offset related to 0x0200 for blocki ng access and 0x300 for non blocking access within the global address space.

4.6.1.2 Interrupt Vector Emulation by Priority

not acknowledge an interrupt. An additional D2D access is necessary to serve the specific module.

4.6.1.2.1 Interrupt Vector Register (IVR)

The following table is listing all MM912F634 analog die interrupt sources with the corresponding priority. Table 79. ISR - Register Field Descriptions

• Low Battery Interrupt
• Low Voltage Interrupt
• High Voltage Interrupt
• Voltage Regulator Over-voltage Interrupt
• Voltage Regulator High Temperature Interrupt 1 - CH0 CH0 - TIM Channel 0 Interrupt 2 - CH1 CH1 - TIM Channel 1 Interrupt 3 - CH2 CH2 - TIM Channel 2 Interrupt 4 - CH3 CH3 - TIM Channel 3 Interrupt 5 - TOV TOV - Timer Overflow Interrupt 6 - ERR ERR - SCI Error Interrupt 7 - TX TX - SCI Transmit Interrupt 8 - RX RX - SCI Receive Interrupt 9 - SCI SCI - ADC Sequence Complete Interrupt 10 - LINOT LINOT - LIN Driver Over-temperature Interrupt 11 - HSOT HSOT - High Side Over-temperature Interrupt 12 - LSOT LSOT - Low Side Over-temperature Interrupt 13 - HOT HOT - HSUP Over-temperature Interrupt

Table 80. Interrupt Vector Register (IVR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 81. IVR - Register Field Descriptions Represents the highest prioritized interrupt pending. See Table 82 In case no interrupt is pending, the result will be 0.

4.6.2 Interrupt Sources

4.6.2.1 Voltage Status Interrupt (VSI)

including masking information.

4.6.2.2 Low Voltage Interrupt (LVI)

and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information.

4.6.2.3 Voltage Regulator High Temperature Interrupt (HTI)

and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information.

4.6.2.4 Low Battery Interrupt (LBI)

and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information.

4.6.2.5 TIM Channel 0 Interrupt (CH0)

See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)". Table 82. Interrupt Source Priority

Functional Description and Application Information Interrupts MM912F634 Freescale Semiconductor 69

4.6.2.6 TIM Channel 1 Interrupt (CH1)

See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)".

4.6.2.7 TIM Channel 2 Interrupt (CH2)

See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)".

4.6.2.8 TIM Channel 3 Interrupt (CH3)

See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)".

4.6.2.9 TIM Timer Over flow Interrupt (TOV)

See Section 4.18, “Basic Timer Module - TIM (TIM16B4C)".

4.6.2.10 SCI Error Interrupt (ERR)

See Section 4.15, “Serial Communication Interface (S08SCIV4)".

4.6.2.11 SCI Transmit Interrupt (TX)

See Section 4.15, “Serial Communication Interface (S08SCIV4)".

4.6.2.12 SCI Receive Interrupt (RX)

See Section 4.15, “Serial Communication Interface (S08SCIV4)".

4.6.2.13 LIN Driver Over-temperature Interrupt (LINOT)

Acknowledge the interrupt by reading the LIN Register - LINR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.14, “LIN Physical Layer Interface - LIN" for details on the LIN Register including masking information.

4.6.2.14 High Side Over-temperature Interrupt (HSOT)

Acknowledge the interrupt by reading the High Side Status Register - HSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.11, “High Side Drivers - HS" for details on the High Side Status Register including masking information.

4.6.2.15 Low Side Over-temperature Interrupt (LSOT)

Acknowledge the interrupt by reading the Low Side Status Register - LSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.12, “Low Side Drivers - LSx" for details on the Low Side Status Register including masking information.

4.6.2.16 HSUP Over-temperature Interrupt (HOT)

Acknowledge the interrupt by reading the Hall Supply Register - HSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.10, “Hall Sensor Supply Output - HSUP" for details on the Hall Supply Register including masking information.

4.6.2.17 High Voltage Interrupt (HVI)

Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information.

Functional Description and Application Information Resets MM912F634 Freescale Semiconductor 70

4.6.2.18 Voltage Regulator Over-voltage Interrupt (VROVI)

Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.4, “Power Supply" for details on the Voltage Status Register including masking information.

4.7 Resets

To protect the system during critical events, the MM912F634 analog die will drive the RESET_A pin low during the presence of the reset condition. In addition, the RESET_A pin is monitored for external reset events. To match the MCU, the RESET_A pin is based on the VDDX voltage level. After an internal reset condition has gone, the RESET_A will stay low for an additional time tRST before being released. Entering reset mode will cause all MM912F634 analog die registers to be initialized to their RESET default. The only registers with valid information are the Reset Status Register (RSR) and the Wake-up Source Register (WUS).

4.7.1 Reset Sources

In the MM912F634 six reset sources exist.

4.7.1.1 POR - Analog Die Power On Reset

To indicate the device power supply (VS1) was below VPOR or the MM912F634 analog die was powered up, the POR condition is set. See Section 4.3, “Modes of Operation".

4.7.1.2 LVR - Low Voltage Reset - VDD

With the VDD voltage regulator output voltage falling below VLVR, the Low Voltage Reset condition becomes present. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. See Section 4.4, “Power Supply".

4.7.1.3 LVRX - Low Voltage Reset - VDDX

With the VDDX voltage regulator output voltage falling below VLVRX, the Low Voltage Reset condition becomes present. See Section 4.4, “Power Supply".

4.7.1.4 WUR - Wake-up Reset

While in Sleep mode, any active wake-up event will cause a MM912F634 analog die transition from Sleep to Reset Mode. To determine the wake-up source, refer to Section 4.8, “Wake-up / Cyclic Sense".

4.7.1.5 EXR - External Reset

Any low level voltage at the RESET_A pin with a duration > tRSTDF will issue an External Reset event. This reset source is also active in Stop mode.

4.7.1.6 WDR - Watchdog Reset

Any incorrect serving if the MM912F634 analog die Watchdog will result in a Watchdog Reset. Please refer to the Section 4.9, “Window Watchdog" for details.

4.7.2 Register Definition

4.7.2.1 Reset Status Register (RSR)

Table 83. Reset Status Register (RSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 84. RSR - Register Field Descriptions 5 - WDR Watchdog Reset - Reset caused by an incorrect serving of the watchdog. 2 - LVRX Low Voltage Reset VDDX - Reset caused by a low voltage condition monitored at the VDDX output. 0 - POR Power On Reset - Supply Voltage was below V POR.

1. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the

4.8 Wake-up / Cyclic Sense

between the WSR read and MCR write.

• Wake-up by a state change of one of the Lx inputs
• Wake-up by a state change of one of the Lx inputs during a cyclic sense
• Wake-up due to a forced wake-up
• Wake-up by the LIN module
• Wake-up by D2D interface (Stop mode only)
• Wake-up due to internal / external Reset (Stop mode only)
• Wake-up due to loss of supply voltage (Sleep mode only)

Figure 20. Wake-up Sources

4.8.1 Wake-up Sources

4.8.1.1 Lx - Wake-up (Cyclic Sense Disabled)

low power mode. The Lx - Wake-up may be combined with the Forced Wake-up. Note: Selecting a Lx Input for wake-up will disable a selected analog input once entering low power mode.

Functional Description and Application Information Wake-up / Cyclic Sense MM912F634 Freescale Semiconductor 73

4.8.1.2 Lx - Cyclic Sense Wake-up

Once Cyclic Sense is configured (CSSEL!=0), the state change is only recognized from one cyclic sense event to the next. The additional accuracy of the cyclic sense cycle by the WD clock trimming is only active during STOP mode. There is no trimmed clock available during SLEEP mode. To reduce external power consumption during low power mode a cyclic wake-up has been implemented. Configuring the Timing Control Register (TCR) a specific cycle time can be selected to implement a periodic switching of the HS1 or HS2 output with the corresponding detection of an Lx state change. Any configuration of the HSx in the High Side Control Register (HSCR) will be ignored when entering low power mode. The Lx - Cyclic Sense Wake-up may be combined with the Forced Wake-up. In case both (forced and Lx change) events are present at the same time, the Forced Wake-up will be indicated as Wake-up source.

4.8.1.3 Forced Wake-up

Configuring the Forced Wake-up Multiplier (FWM) in the Timing Control Register (TCR) will enable the forced wake-up based on the selected Cyclic Sense Timing (CST). Forced Wake-up can be combined with all other wake-up sources considering the timing dependencies.

4.8.1.4 LIN - Wake-up

While in Low-Power mode the MM912F634 analog die monitors the activity on the LIN bus. A dominant pulse longer than tPROPWL followed by a dominant to recessive transition will cause a LIN Wake-up. This behavior protects the system from a short-to-ground bus condition.

4.8.1.5 D2D - Wake-up (Stop Mode only)

Receiving a Normal mode request via the D2D interface (MODE=0, Mode Control Register (MCR)) will result in a wake-up from stop mode. As this condition is controlled by the MCU, no wake-up status bit does indicate this wake-up source.

4.8.1.6 Wake-up Due to Internal / External Reset (STOP Mode Only)

While in Stop mode, a Reset due to a VDD low voltage condition or an external Reset applied on the RESET_A pin will result in a Wake-up with immediate transition to Reset mode. In this case, the LVR or EXR bits in the Reset Status Register will indicate the source of the event.

4.8.1.7 Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only)

While in Sleep mode, a supply voltage VS1 < VPOR will result in a transition to Power On mode.

4.8.2 Register Definition

4.8.2.1 Wake-up Control Register (WCR)

Table 85. Wake-up Control Register (WCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 86. WCR - Register Field Descriptions 11 - Cyclic Sense with periodic HS1 and HS2 on. 5 - L5WE Wake-up Input 5 Enabled - L5 Wake-up Select Bit. 4 - L4WE Wake-up Input 4 Enabled - L4 Wake-up Select Bit. 3 - L3WE Wake-up Input 3 Enabled - L3 Wake-up Select Bit. 2- L2WE Wake-up Input 2 Enabled - L2 Wake-up Select Bit. 1 - L1WE Wake-up Input 1 Enabled - L1 Wake-up Select Bit. 0 - L0WE Wake-up Input 0 Enabled - L0 Wake-up Select Bit.

4.8.2.2 Timing Control Register (TCR)

Table 87. Timing Control Register (TCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 88. TCR - Register Field Descriptions with the cyclic sense period <= the forced wake-up period.

1. Cyclic Sense Timing with Accuracy CS

4.8.2.3 Wake-up Source Register (WSR)

required between the WSR read and the MCR write. Table 89. Wake-up Source Register (WSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 90. WSR - Register Field Descriptions

4.9 Window Watchdog

(tWDTO) can be configured between 10 ms and 1280 ms (typ.) using the Watchdog Register (WDR). During Low Power mode, the watchdog feature is not active, a D2D read during Stop mode will have the WDOFF bit set. after the RESET_A has been released has to be 0xAA. The next one must be 0x55. After the RESET_A has been released, there will be a standard (non-window) watchdog active with a fixed timeout of tIWDTO. “MM912F634 - Analog Die Trimming". Figure 21. MM912F634 Analog Die Watchdog Operation (WDSR) before tIWDTO is reached. indicate the current status of the window. A timeout or wrong value written to the WDSR will force a watchdog reset. is re-enabled, the initial watchdog sequence has to be performed. During Low Power mode, the Watchdog clock is halted and the Watchdog Service Register (WDSR) is reset to the default state.

4.9.1 Register Definition

4.9.1.1 Watchdog Register (WDR)

4.9.1.2 Watchdog Service Register (WDSR)

Table 91. Watchdog Register (WDR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 92. WDR - Register Field Descriptions 7 - WDOFF watchdog Off - Indicating the Wa tchdog module is being disabled externally. 6 - WDWO Watchdog Window Open - Indicating the Watc hdog Window is currently open for counter reset. Watchdog Timeout Configuration - configuring the Watchdog timeout duration tWDTO. Table 93. Watchdog Service Register (WDSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 94. WDSR - Register Field Descriptions will reset the watchdog counter. Writing the register while the watchdog is disabled will have no effect.

4.10 Hall Sensor S upply Output - HSUP

over-temperature condition is gone, will re-enable the Hall Supply Output. The HSUP output is active only during Normal mode. A capacitor CHSUP is recommended for operation.

4.10.1 Register Definition

4.10.1.1 Hall Supply Register (HSR)

Table 95. Hall Supply Register (HSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 96. HSR - Register Field Descriptions clear the HOT flag if present. See Section 4.6, “Interrupts" for details.

Functional Description and Application Information High Side Drivers - HS MM912F634 Freescale Semiconductor 80

4.11 High Side Drivers - HS

These outputs are two High Side drivers, intended to drive small resistive loads or LEDs incorporating the following features:

• PWM capability via the PWM Module
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• High voltage shutdown - HVI (software maskable)
• Cyclic-Sense, See Section 4.8, “Wake-up / Cyclic Sense"

4.11.1 Open Load Detection

Each high side driver signals an open load condition if the current through the high side is below the open load current threshold. The open load condition is indicated with the bits HS1OL and HS2OL in the High Side Status Register (HSSR).

4.11.2 Current Limitation

Each high side driver has an output current limitation. In combination with the over-temperature shutdown the high side drivers are protected against over-current and short-circuit failures. That the driver operates in the current limitation area is indicated with the bits HS1CL and HS2CL in the High Side Status Register (HSSR).

4.11.3 Over-temperature Protection (HS Interrupt)

Both high side drivers are protected against over-temperature. In over-temperature conditions, both high side drivers are shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source Register (ISR). A thermal shutdown of the high side drivers is indicated by setting the HSOT bit in the High Side Status Register (HSSR). A write to the High Side Control Register (HSCR), when the over-temperature condition is gone, will re- enable the high side drivers.

4.11.4 High Voltage Shutdown

In case of a high voltage condition (HVI), and if the high voltage shutdown is enabled (bit HVSDE in the High Side Control Register (HSCR) is set), both high side drivers are shut down. A write to the High Side Control Register (HSCR), when the high voltage condition is gone, will re-enable the high side drivers.

4.11.5 Sleep And Stop Mode

The high side drivers can be enabled to operate in Sleep and Stop mode for cyclic sensing. See Section 4.8, “Wake-up / Cyclic Sense"

4.11.6 PWM Capability

Section 4.13, “PWM Control Module (PWM8B2C)"

4.11.7 Register Definition

4.11.7.1 High Side Control Register (HSCR)

Table 97. High Side Control Register (HSCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 98. HSCR - Register Field Descriptions present. See Section 4.4, “Power Supply" for the Voltage Status Register.

4.11.7.2 High Side Status Register (HSSR)

Table 99. High Side Status Register (HSSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 100. HSSR - Register Field Descriptions interrupt flag if present. See Section 4.6, “Interrupts" for details.

4.12 Low Side Drivers - LSx

4.12.1 Introduction / Features

• PWM capability
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• Active clamp
• Independent VREG - High Voltage Shutdown

4.12.1.1 Block Diagram

The following Figure shows the basic structure of the LS drivers. Figure 22. Low Side Drivers - Block Diagram

4.12.1.2 Modes of Operation

The Low Side module is active only in Normal mode; the Low Side drivers are disabled in Sleep and Stop mode.

4.12.2 External Signal Description

controlled by the Low Side module. Table 101. Pin Functions and Priorities

4.12.3 Memory Map and Registers

4.12.3.1 Module Memory Map

4.12.3.2 Register Descriptions

4.12.3.2.1 Low Side Control Register (LSCR)

Table 102. Low-Side Module - Memory Map Table 103. Low Side Control Register (LSCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 104. LSCR - Register Field Descriptions

4.12.3.2.2 Low Side Status Register (LSSR)

4.12.3.2.3 Low Side Control Enable Register (LSCEN)

Table 105. Low Side Status Register (LSSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 106. LSSR - Register Field Descriptions flag if present. See Section 4.6, “Interrupts" for details. Table 107. Low Side Enable Register (LSEN)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 108. LSEN - Register Field Descriptions Low Side Control Enable - To allow the LS Control via LSx, the correct value has to be written into the LSCEN Register.

Functional Description and Application Information Low Side Drivers - LSx MM912F634 Freescale Semiconductor 86

4.12.4 Functional Description

The Low Side switches are controlled by the bits LS1:2 in the Low Side Control Register (LSCR). In order to control the Low Sides, the LSCEN register has to be correctly written once after RESET or VROV. To protect the device against over-voltage when an inductive load (relay) is turned off an active clamp circuit is implemented.

4.12.4.1 Voltage Regulator Over-voltage Protection

The over-voltage threshold has to be trimmed at system power up. Please refer to and may have disabled the LS function already. An initial LS enable would be needed. To protect the application for an unintentional activation of the drivers in case of a voltage regulator over-voltage failure, the Low Side Drivers will automatically shut down in case of an over-voltage on one of the two regulators. The shutdown is fully handled in the analog section of the driver. This will secure the feature in case the digital logic is damaged due to the over-voltage condition. Once an over-voltage condition on one of the voltage regulators occurs, the LSx control bits in the Low Side Control Register (LSCR) will be reset to 0. The Voltage Regulator Over-voltage Condition Bit (VROVC) in the Voltage Status Register (VSR) will stay set as long as the condition is present. If the Voltage Regulator Over-voltage Interrupt was enabled (VROVIE=1), the VROV- Interrupt will be issued. Reading the Voltage Regulator Over-voltage Condition Bit (VROVC) in the Voltage Status Register (VSR) will clear the interrupt. To issue another VROV - Interrupt, the condition has to vanish and be present again. To re-enable the Low Side Drivers after a Voltage Regulator Over-voltage condition occurred, first the LSCEN register has to be written with “0x05” - this information is processed through the main digital blocks, and would secure a minimum functionality before enabling the LS drivers again. In a second step, the LSx Control Bits in the Low Side Control Register (LSCR) must be enabled again after the over-voltage condition has vanished (VROVC=0).

4.12.4.2 Open Load Detection

Each Low Side driver signals an open load condition if the current through the Low Side is below the open load current threshold. The open load condition is indicated with the bit LS1OP and LS2OP in the Low Side Status Register (LSSR).

4.12.4.3 Current Limitation

Each Low Side driver has a current limitation. In combination with the over-temperature shutdown, the Low Side drivers are protected against over-current and short-circuit failures. The driver operates in current limitation, and is indicated with the bits LS1CL and LS2CL in the Low Side Status Register (LSSR). Note: If the drivers is operating in current limitation mode excessive power might be dissipated.

4.12.4.4 Over-temperature Protection (LS Interrupt)

Both Low Side drivers are protected against over-temperature. In case of an over-temperature condition, both Low Side drivers are shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as LS Interrupt in the Interrupt Source Register (ISR). If the bit LSM is set in the Interrupt Mask Register (IMR) than an Interrupt (IRQ) is generated. A write to the Low Side Control Register (LSCR) will re-enable the Low Side drivers when the over-temperature condition is gone.

4.12.5 PWM Capability

See Section 4.13, “PWM Control Module (PWM8B2C)".

Functional Description and Application Information PWM Control Module (PWM8B2C) MM912F634 Freescale Semiconductor 87

4.13 PWM Control Module (PWM8B2C)

4.13.1 Introduction

To control the High Side (HS1, HS2) and the Low Side (LS1, LS2) duty cycle as well as the PTB2 output, the PWM module is implemented. Refer to the individual driver section for details on the use of the internal PWM1 and PWM0 signal (Section 4.11, “High Side Drivers - HS", Section 4.12, “Low Side Drivers - LSx" and Section 4.17, “General Purpose I/O - PTB[0…2]" ) The PWM definition is based on the HC12 PWM definitions with some of the simplifications incorporated. The PWM module has two channels with independent controls of left and center aligned outputs on each channel. Each of the two channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%.

4.13.1.1 Features

The PWM block includes these distinctive features:

• Two independent PWM channels with programmable periods and duty cycles
• Dedicated counter for each PWM channel
• Programmable PWM enable/disable for each channel
• Software selection of PWM duty pulse polarity for each channel
• Period and duty cycle are double buffer ed. Change takes effect when the end of the effective period is reached (PWM counter reaches zero), or when the channel is disabled
• Programmable center or left ali gned outputs on individual channels
• Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
• Programmable clock select logic

4.13.1.2 Modes of Operation

The PWM8B2C module does operate in Normal mode only.

4.13.1.3 Block Diagram

Figure 23 shows the block diagram for the 8-bit 2-channel PWM block. Figure 23. PWM Block Diagram

4.13.2 Signal Description

frequencies higher than the maximum output frequency of the connected driver (HS, LS). Please refer to Section 3.6, “Dynamic Electrical Characteristics" for details. Section 4.17, “General Purpose I/O - PTB[0…2]" for configuration details.

4.13.2.1 D2DCLK

4.13.2.2 PWM1 — Pulse Wi dth Modulator Channel 1

This signal serves as waveform output of PWM channel 1.

4.13.2.3 PWM0 — Pulse Wi dth Modulator Channel 0

This signal serves as waveform output of PWM channel 0.

4.13.3 Register Descriptions

read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit.

4.13.3.1 PWM Control Register (PWMCTL)

Table 109. PWM Register Summary

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 110. PWM Control Register (PWMCTL)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.13.3.1.1 PWM Enable (PWMEx)

disabled (PWME1–0 = 0), the prescaler counter shuts off for power savings. output until its clock source begins its next cycle, due to the synchronization of PWMEx and the clock source.

4.13.3.1.2 PWM Polarity (PPOLx)

polarity bit is zero, the output starts low and then goes high when the duty count is reached.

4.13.3.1.3 PWM Clock Select (PCLKx)

Each PWM channel has a choice of two clocks to use as the clock source for that channel as described by the following. Table 111. PWMCTL - Register Field Descriptions 0 Channels 1–0 operate in left aligned output mode. 1 Channels 1–0 operate in center aligned output mode. 0 Clock B is the clock source for PWM channel 1. 1 Clock SB is the clock source for PWM channel 1. 0 Clock A is the clock source for PWM channel 0. 1 Clock SA is the clock source for PWM channel 0. 0 PWM channel 1–0 outputs are low at the beginning of the period, then go high when the duty count is reached. 1 PWM channel 1–0 outputs are high at the beginning of the period, then go low when the duty count is reached. 0 Pulse width channel 1–0 is disabled. source begins its next cycle.

4.13.3.1.4 PWM Center Align Enable (CAEx)

Write these bits only when the corresponding channel is disabled. description of the PWM output modes.

4.13.3.2 PWM Prescale Clock Select Register (PWMPRCLK)

This register selects the prescale clock source for clocks A and B independently. Table 112. PWM Prescale Clock Select Register (PWMPRCLK)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 113. PWMPRCLK - Register Field Descriptions determine the rate of clock B, as shown in Table 114. determine the rate of clock A, as shown in Table 115. Table 114. Clock B Prescaler Selects

4.13.3.3 PWM Scale A Register (PWMSCLA)

A, dividing it by the value in the PWMSCLA register and dividing that by two.

4.13.3.4 PWM Scale B Register (PWMSCLB)

B, dividing it by the value in the PWMSCLB register and dividing that by two. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Table 115. Clock A Prescaler Selects Table 116. PWM Scale A Register (PWMSCLA)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.13.3.5 PWM Channel Counter Registers (PWMCNTx)

register and then back down to 0. Table 117. PWM Scale B Register (PWMSCLB)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 118. PWM Channel Counter Registers (PWMCNTx)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.13.3.6 PWM Channel Period Registers (PWMPERx)

the value of the currently active period due to the double buffering scheme.

• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel:
• Left aligned output (CAEx = 0)
• PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1)
• PWMx Period = Channel Clock Period * (2 * PWMPERx)

Table 119. PWM Channel Period Registers (PWMPERx)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.13.3.7 PWM Channel Duty Registers (PWMDTYx)

the value of the currently active duty due to the double buffering scheme.

• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. If the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a% of period) for a particular channel:
• Polarity = 0 (PPOL x =0) – Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
• Polarity = 1 (PPOLx = 1) – Duty Cycle = [PWMDTYx / PWMPERx] * 100%

Figure 24. PWM Channel Duty Registers (PWMDTYx)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Functional Description and Application Information PWM Control Module (PWM8B2C) MM912F634 Freescale Semiconductor 96

4.13.4 Functional Description

4.13.4.1 PWM Clock Select

There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the D2D clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the D2D clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 25 shows the four different clocks and how the scaled clocks are created.

4.13.4.1.1 Prescale

The input clock to the PWM prescaler is the D2D clock. The input clock can also be disabled when both PWM channels are disabled (PWME1-0 = 0). This is useful for reducing power by disabling the prescale counter. Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the D2D clock. The value selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK register.

4.13.4.1.2 Clock Scale

The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB.

Figure 25. PWM Clock Select Block Diagram

Functional Description and Application Information PWM Control Module (PWM8B2C) MM912F634 Freescale Semiconductor 98 NOTE Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. NOTE Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register. As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by 8 rate. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this.

4.13.4.1.3 Clock Select

Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. Each PWM channel has the capability of selecting one of two clocks. For channels 0 the clock choice is clock A or clock SA. For channels 1 the choice is clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCTL register.

4.13.4.2 PWM Channel Timers

The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register, and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value, and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown in Figure 26 is the block diagram for the PWM timer.

Figure 26. PWM Timer Channel Block Diagram

4.13.4.2.1 PWM Enable

The first PWM cycle after enabling the channel can be irregular. PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. (PWMEx = 0), the counter for the channel does not count.

4.13.4.2.2 PWM Polarity

reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.

Functional Description and Application Information PWM Control Module (PWM8B2C) MM912F634 Freescale Semiconductor 100

4.13.4.2.3 PWM Period and Duty

When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. Dedicated period and duty registers exist for each channel and are double buffered, so if they change while the channel is enabled, the change will NOT take effect until one of the following occurs:

• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers, and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be used to make adjustments

4.13.4.2.4 PWM Timer Counters

To start a new “clean” PWM waveform without any “history” from the old waveform, writing the channel counter (PWMCNTx) must happen prior to enabling the PWM channel (PWMEx = 1). Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see Section 4.13.4.1, “PWM Clock Select"” for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 26. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 26 and described in Section 4.13.4.2.5, “Left Aligned Outputs"” Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next selected clock. Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. “Center Aligned Outputs"” for more details).

4.13.4.2.5 Left Aligned Outputs

to program the output mode before enabling the PWM channel. in the PWMCTL register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. 0 to the value in the period register – 1. Figure 27. PWM Left Aligned Output Waveform for the channel (A, B, SA, or SB), and divide it by the value in the period register for that channel.

• PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
• PWMx Duty Cycle (high time as a % of period): — Polarity = 0 (PPOLx = 0)
• Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock Source = E, where E = 10 kHz (100 µs period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 kHz/4 = 2.5 kHz PWMx Period = 400 µs PWMx Duty Cycle = 3/4 *100% = 75%

Table 120. PWM Timer Counter Conditions When PWMCNTx register written to any value When PWM channel is enabled (PWMEx = 1). Counts from last value in PWMCNTx.

The output waveform generated is shown in Figure 28. Figure 28. PWM Left Aligned Output Example Waveform

4.13.4.2.6 Center Aligned Outputs

to program the output mode before enabling the PWM channel. output will be center aligned. down to 0. Thus the effective period is PWMPERx*2. Figure 29. PWM Center Aligned Output Waveform for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.

• PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)
• PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% Period = 400 µs E = 100 µs Duty Cycle = 75% PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx Period = PWMPERx*2 PWMPERxPWMPERx

Figure 30 shows the output waveform generated. Figure 30. PWM Center Aligned Output Example Waveform

4.13.4.2.7 PWM Boundary Cases

Table 121 summarizes the boundary conditions for the PWM, regardless of the output mode (left aligned or center aligned).

4.13.5 Resets

their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section.

• The 8-bit up/down counter is configur ed as an up counter out of reset.
• All the channels are disabled and all the counters do not count.

4.13.6 Interrupts

The PWM module has no Interrupts. Table 121. PWM Boundary Cases

1 Always high

0 Always low

1. Counter = $00 and does not count.

Functional Description and Application Information LIN Physical Layer Interface - LIN MM912F634 Freescale Semiconductor 104

4.14 LIN Physical La yer Interface - LIN

The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer version 2.1 specification, and has the following features:

• LIN physical la yer 2.1 compliant
• Slew rate selection 20 kBit, 10 kBit, and fast Mode (100 kBit)
• Over-temperature Shutdown - HTI
• Permanent Pull-up in Normal mode 30 k Ω, 1.0 MΩ in low power
• Current limitation
• External Rx / Tx access. See Section 4.17, “General Purpose I/O - PTB[0…2]"
• Slew Rate Trim Bit. See Section 4.25, “MM912F634 - Analog Die Trimming" The LIN driver is a Low Side MOSFET with current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed.

4.14.1 LIN Pin

The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. See Section 3.8, “ESD Protection and Latch-up Immunity".

4.14.2 Slew Ra te Selection

The slew rate can be selected for optimized operation at 10 kBit/s and 20 kBit/s as well as a fast baud rate (100 kBit) for test and programming. The slew rate can be adapted with the bits LINSR[1:0] in the LIN Register (LINR). The initial slew rate is 20 kBit/s.

4.14.3 Over-temperature Shutdown (LIN Interrupt)

The output Low Side FET (transmitter) is protected against over-temperature conditions. In case of an over-temperature condition, the transmitter will be shut down and the bit LINOTC in the LIN Register (LINR) is set as long as the condition is present. If the LINOTIE bit is set in the LIN Register (LINR), an Interrupt IRQ will be generated. Acknowledge the interrupt by reading the LIN Register (LINR). To issue a new interrupt, the condition has to vanish and occur again. The transmitter is automatically re-enabled once the over-temperature condition is gone and TxD is High.

4.14.4 Low Power Mode and Wake-up Feature

During Low Power mode operation the transmitter of the physical layer is disabled. The receiver is still active and able to detect Wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge, will generate a wake-up event and be reported in the Wake-up Source Register (WSR).

4.14.5 J2602 Compliance

A Low Voltage Shutdown feature was implemented to allow controlled J2602 compliant LIN driver behavior under Low Voltage conditions (LVSD=0). When an under-voltage occurs on VS1 (LVI), the LIN stays in recessive mode if it was in recessive state. If it was in a dominant state, it waits until the next dominant to recessive transition, then it stays in the recessive state.

4.14.6 Register Definition

4.14.6.1 LIN Register (LINR)

Table 122. LIN Register (LINR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 123. LINR - Register Field Descriptions 6 - LINOTC LIN - Over-temperature condition pr esent. LIN driver is shut down. Reading this bit will clear the LINOT interrupt flag. 5 - RX LIN - Receiver (Rx) Status.

Functional Description and Application Information Serial Communication Interface (S08SCIV4) MM912F634 Freescale Semiconductor 106

4.15 Serial Communicati on Interface (S08SCIV4)

4.15.1 Introduction

4.15.1.1 Features

Features of the SCI module include:

• Full-duplex, standard non-return-to-zero (NRZ) format
• Double-buffered transmitter and receiver with separate enables
• Programmable baud rates (13-bit modulo divider)
• Interrupt-driven or polled operation: — Transmit data register em pty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect — Active edge on receive pin — Break detect supporting LIN
• Hardware parity generation and checking
• Programmable 8-bit or 9-bit character length
• Receiver wake-up by idle-line or address-mark
• Optional 13-bit break character generat ion / 11-bit break character detection
• Selectable transmitter output polarity

4.15.1.2 Modes of Operation

See Section 4.15.3, “Functional Description",” For details concerning SCI operation in these modes:

• 8- and 9-bit data modes
• Loop mode
• Single-wire mode

4.15.1.3 Block Diagram

Figure 31 shows the transmitter portion of the SCI. Figure 31. SCI Transmitter Block Diagram

4.15.2 Register Definition

The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to Section 4.5, “Die to Die Interface - Target" of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.

4.15.2.1 SCI Baud Rate Regist ers (SCIBD (hi), SCIBD (lo))

in SCIBD (hi) does not change until SCIBD (lo) is written. transmitter is enabled (RE or TE bits in SCIC2 are written to 1). Table 124. SCI Baud Rate Register (SCIBD (hi))

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 125. SCIBD (hi) Field Descriptions 0 Hardware interrupts from LBKDIF disabled (use polling). 1 Hardware interrupt requested when LBKDIF flag is 1. 0 Hardware interrupts from RXEDGIF disabled (use polling). 1 Hardware interrupt requested when RXEDGIF flag is 1. to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 127. Table 126. SCI Baud Rate Register (SCIBDL)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 127. SCIBDL Field Descriptions BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 125.

4.15.2.2 SCI Control Register 1 (SCIC1)

This read/write register is used to control various optional features of the SCI system. Table 128. SCI Control Register 1 (SCIC1)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 129. SCIC1 Field Descriptions transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connec ted to the transmitter output and receiver input. 0 Normal — start + 8 data bits (LSB first) + stop.

1 Receiver and transmitter use 9-bit data characters

start + 8 data bits (LSB first) + 9th data bit + stop. Wake-up"” for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking.

4.15.2.3 SCI Control Register 2 (SCIC2)

This register can be read or written at any time. Table 130. SCI Control Register 2 (SCIC2)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 131. SCIC2 Field Descriptions 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1. 0 Hardware interrupts from TC disabled (use polling). 1 Hardware interrupt requested when TC flag is 1. 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF flag is 1. 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. SCI communication line (TxD pin). finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. (WAKE = 0, idle-line wake-up), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wake-up). 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wake-up condition. 0 Normal transmitter operation. 1 Queue break character(s) to be sent.

4.15.2.4 SCI Status Register 1 (SCIS1)

this register) are used to clear these status flags. Table 132. SCI Status Register 1 (SCIS1)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 133. SCIS1 Field Descriptions and then write to the SCI data register (SCID). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmi ssion activity complete).

• Write to the SCI data register (SCID) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCIC2 RDRF Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID). 0 Receive data register empty. 1 Receive data register full. IDLE Idle Line Flag — IDLE is set when the SCI receive line becomes idle fo r a full character time after a period of activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. OR Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from SCID yet. In this case, the new character (and all associated error information) is lost because there is no room to move it into SCID. To clear OR, read SCIS1 with OR = 1 and then read the SCI data register (SCID). 0 No overrun. 1 Receive overrun (new SCI data lost). NF Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and then read the SCI data register (SCID). 0 No noise detected. 1 Noise detected in the received character in SCID.

4.15.2.5 SCI Status Register 2 (SCIS2)

This register has one read-only status flag. then read the SCI data register (SCID). 0 No framing error detected. This does not guarantee the framing is correct. character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the SCI data register (SCID). Table 134. SCI Status Register 2 (SCIS2)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 135. SCIS2 Field Descriptions detected. LBKDIF is cleared by writing a “1” to it. 0 No LIN break character has been detected. 1 LIN break character has been detected. RxD pin occurs. RXEDGIF is cleared by writing a “1” to it. 0 No active edge on the receive pin has occurred. 1 An active edge on the receive pin has occurred. Receive Data Inversion — Setting this bit reverses the polarity of the received data input.

0 Receive data not inverted

1 Receive data inverted

Receive Wake Up Idle Detect— RWUID controls whether the idle character t hat wakes up the receiver sets the IDLE bit. 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. framing error is not affected by the state of this bit.

0 Break character is transmitted with length of 10 bit times (11 if M = 1)

1 Break character is transmitted with length of 13 bit times (14 if M = 1)

error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character detection enabled. 1 Break character detection disabled.

1. Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.

Table 133. SCIS1 Field Descriptions (continued)

from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.

4.15.2.6 SCI Control Register 3 (SCIC3)

Table 136. SCI Control Register 3 (SCIC3)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 137. SCIC3 Field Descriptions be written each time SCID is written. (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. Transmit Data Inversion — Setting this bit reverses the pol arity of the transmitted data output.

0 Transmit data not inverted

1 Transmit data inverted

Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1. Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF = 1. Framing Error Interrupt Enable — This bit enables the framing error flag (F E) to generate hardware interrupt requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE = 1. Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF = 1.

1. Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.

4.15.2.7 SCI Data Register (SCID)

4.15.3 Functional Description

SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI.

4.15.3.1 Baud Ra te Generation

As shown in Figure 33, the clock source for the SCI baud rate generator is the D2D clock. Figure 33. SCI Baud Rate Generation the leading edge of the start bit and how bit sampling is performed. acceptable for reliable communications. Table 138. SCI Data Register (SCID)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.15.3.2 Transmitter Functional Description

idle characters. The transmitter block diagram is shown in Figure 31. store data into the transmit data buffer by writing to the SCI data register (SCID). complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. must first be completed. This includes data characters in progress, queued idle characters, and queued break characters.

4.15.3.2.1 Send Break and Queued Idle

Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE = 1) occurs. control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below. Table 139. Break Character Length

Functional Description and Application Information Serial Communication Interface (S08SCIV4) MM912F634 Freescale Semiconductor 117

4.15.3.3 Receiver F unctional Description

In this section, the receiver block diagram (Figure 32) is used as a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wake-up function are explained. The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to Section •, “8- and 9-bit data modes".” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s

4.15.3.3.1 Data Sampling Technique

The SCI receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set.

4.15.3.3.2 Receiver Wake-up Operation

Receiver wake-up is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU bit is set, the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message.

Functional Description and Application Information Serial Communication Interface (S08SCIV4) MM912F634 Freescale Semiconductor 118 When WAKE = 0, the receiver is configured for idle-line wake-up. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE flag. The receiver wakes up and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether RWU is zero or one. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. When WAKE = 1, the receiver is configured for address-mark wake-up. In this mode, RWU is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wake-up allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is received and sets the RDRF flag. In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time.

4.15.3.4 Interrupts and Status Flags

The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCID. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID. The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then reading SCID. When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains idle for an extended period of time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading SCID. After IDLE has been cleared, it cannot become set again until the receiver has received at least one new character and has set RDRF. If the associated error was detected in the received character that caused RDRF to be set, the error flags — noise flag (NF), framing error (FE), and parity error flag (PF) — get set at th e same time as RDRF. These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE, or PF condition is lost.

Functional Description and Application Information Serial Communication Interface (S08SCIV4) MM912F634 Freescale Semiconductor 119 At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled (RE = 1).

4.15.3.5 Additional SCI Functions

The following sections describe additional SCI functions. 4.15.3.5.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIC3. For the receiver, the ninth bit is held in R8 in SCIC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID. If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with address-mark wake-up so the ninth data bit can serve as the wake-up bit. In custom protocols, the ninth bit can also serve as a software-controlled marker.

4.15.3.5.2 Stop Mode Operation

During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. An active edge on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1). Note that because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module.

4.15.3.5.3 Loop Mode

When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general purpose port I/O pin.

4.15.3.5.4 Single- wire Operation

When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used and reverts to a general purpose port I/O pin. In single-wire mode, the TXDIR bit in SCIC3 controls the direction of serial data on the TxD pin. When TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.

4.16 High Voltage Inputs - Lx

• Digital Input Capable
• Analog Input Capable with selectable voltage divider.
• Wake-up Capable during Low Power mode. See Section 4.8, “Wake-up / Cyclic Sense". When used as analog inputs to sense voltages outside the module a series resistor must be used on the used input. When a Lx input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. When a Lx input is selected in the analog multiplexer, it will be disconnected in low power mode if configured as Wake-up input. Unused Lx pins are recommended to be connected to GND to improve EMC behavior.

4.16.1 Register Definition

4.16.1.1 Lx Status Register (LXR)

4.16.1.2 Lx Control Register (LXCR)

Table 140. Lx Status Register (LXR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 141. LXR - Register Field Descriptions Table 142. Lx Control Register (LXCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 143. LXCR - Register Field Descriptions

4.17 General Purpose I/O - PTB[0…2]

The three multipurpose I/O pins can be configured to operate as documented in the table below. The alternate function of PTB2, PTB1 and PTB0 can be configured by selecting the function in the corresponding module (e.g. TIMER). The selection with the highest priority will take effect when more than one function is selected.

4.17.1 Digital I/O Functionality

All three pins act as standard digital Inputs / Outputs with selectable pull-up resistor.

4.17.2 Alternative SCI / LIN Functionality

internal LIN and / or SCI signals (RxD and TxD). Figure 34 shows the 4 available configurations. Figure 34. Alternative SCI / LIN Functionality

4.17.3 Alternative PWM Functionality

configured in the Port B Configuration Register 2 (PTBC2). Table 144. General purpose I/O - Operating modes

4.17.4 Register definition

4.17.4.1 Port B Configuration Register 1 (PTBC1)

The pull-up resistor is not active once the port is configured as an output.

4.17.4.2 Port B Configuration Register 2 (PTBC2)

Table 145. Port B Configuration Register 1 (PTBC1)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 146. PTBC1 - Register Field Descriptions 0 - Pull-up disabled on PTBx pin. 1- Pull-up enabled on PTBx pin. 0 - PTBx configured as input. 1 - PTBx configured as output. Table 147. Port B Configuration Register 2 (PTBC2)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 148. PTBC2 - Register Field Descriptions PWM Channel Select PTB2. See Section 4.13, “PWM Control Module (PWM8B2C)". PWM Enable for PTB2. See Section 4.13, “PWM Control Module (PWM8B2C)". Serial Mode Select for PTB0 and PTB1. See Figure 34 for details.

4.17.4.3 Port B Data Register (PTB)

Table 149. Port B Data Register (PTB)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 150. PTB - Register Field Descriptions and synchronized pin input state is read.

4.18 Basic Timer Modul e - TIM (TIM16B4C)

4.18.1 Introduction

4.18.1.1 Overview

The basic timer consists of a 16-bit, software-programmable counter driven by a seven-stage programmable prescaler. waveform. Pulse widths can vary from microseconds to many seconds. A full access for the counter registers or the input capture/output compare registers should take place in 16bit word access.

4.18.1.2 Features

• Four input capture/output compare channels.
• Clock prescaler
• 16-bit counter

4.18.1.3 Modes of Operation

The TIM16B4C is only active during Normal mode.

4.18.1.4 Block Diagram

Figure 35. Timer Block Diagram For more information see the respective functional descriptions see Section 4.18.4, “Functional Description" of this chapter.

4.18.2 Signal Description

4.18.2.1 Overview

“General Purpose I/O - PTB[0…2]" (IOC3).

4.18.2.2 Detailed Signal Descriptions

4.18.2.2.1 IOC3 – Input Capture and Output Compare Channel 3

channel would have no effect. Section 4.17.2, “Alternative SCI / LIN Functionality".

4.18.2.2.2 IOC2 – Input Capture and Output Compare Channel 2

This pin serves as an input capture or output compare for channel 2 and can be routed to the PTB2 general purpose I/O.

4.18.2.2.3 IOC1 – Input Capture and Output Compare Channel 1

This pin serves as an input capture or output compare for channel 1 and can be routed to the PTB1 general purpose I/O.

4.18.2.2.4 IOC0 – Input Capture and Output Compare Channel 0

For the description of interrupts see Section 4.18.6, “Interrupts". This pin serves as an input capture or output compare for channel 0 and can be routed to the PTB0 general purpose I/O.

4.18.3 Memory Map and Registers

4.18.3.1 Overview

This section provides a detailed description of all memory and registers.

4.18.3.2 Module Memory Map

The memory map for the TIM16B4C module is given below in Table 151. Table 151. Module Memory Map

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
2. Only writable in special modes. (Ref er to SOC Guide for different modes).
3. Write to these registers have no meaning or effect during input capture.

Table 151. Module Memory Map (continued)

4.18.3.3 Register Descriptions

associated figure number. Details of register bit and field function follow the register diagrams, in bit order.

4.18.3.3.1 Timer Input Capture /Output Compare Select (TIOS)

4.18.3.3.2 Timer Compare Force Register (CFORC)

Table 152. Timer Input Capture/Output Compare Select (TIOS)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 153. TIOS - Register Field Descriptions 0 - The corresponding channel acts as an input capture. 1 - The corresponding channel acts as an output compare. Table 154. Timer Compare Force Register (CFORC)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 155. CFORC - Register Field Descriptions

then forced output compare action will take precedence and interrupt flag will not get set. register except the interrupt flag does not get set.

4.18.3.3.3 Output Compare 3 Mask Register (OC3M)

ranges from 0 to 2) bit is set to be an output compare.

4.18.3.3.4 Output Compare 3 Data Register (OC3D)

Table 156. Output Compare 3 Mask Register (OC3M)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 157. OC3M - Register Field Descriptions Table 158. Output Compare 3 Data Register (OC3D)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.18.3.3.5 Timer Count Register (TCNT)

4.18.3.3.6 Timer System Control Register 1 (TSCR1)

Table 159. OC3D - Register Field Descriptions Table 160. Timer Count Register (TCNT)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 161. TCNT - Register Field Descriptions

16 Bit Timer Count Register

Table 162. Timer System Control Register 1 (TSCR1)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.18.3.3.7 Timer Toggle On Overflow Register 1 (TTOV)

toggle on the output compare pin takes precedence over forced output compare events. Table 163. TSCR1 - Register Field Descriptions 0 = Disables the timer. (Used for reducing power consumption). corresponding channel flag, CnF, to be cleared.For TFLG2 register, any access to the TCNT register clears the TOF flag. 0 = Allows the timer flag clearing. Table 164. Timer Toggle On Overflow Register 1 (TTOV)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 165. TTOV - Register Field Descriptions 1 = Toggle output compare pin on overflow feature enabled. 0 = Toggle output compare pin on overflow feature disabled.

4.18.3.3.8 Timer Contro l Register 1 (TCTL1)

4.18.3.3.9 Timer Contro l Register 2 (TCTL2)

These four pairs of control bits configure the input capture edge detector circuits. Table 166. Timer Control Register 1 (TCTL1)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 167. TCTL1 - Register Field Descriptions Table 168. Compare Result Output Action Table 169. Timer Control Register 2 (TCTL2)

1. (116)Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 170. TCTL2 - Register Field Descriptions

4.18.3.3.10 Timer Interrupt Enable Register (TIE)

4.18.3.3.11 Timer System Control Register 2 (TSCR2)

This mode of operation is similar to an up-counting modulus counter. counter register (TCNT) is reset from $FFFF to $0000. where all prescale counter stages equal zero. Table 171. Edge Detector Circuit Configuration Table 172. Timer Interrupt Enable Register (TIE)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 173. TIE - Register Field Descriptions Input Capture/Output Compare Interrupt Enable. Table 174. Timer System Control Register 2 (TSCR2)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 175. TIE - Register Field Descriptions 1 = Hardware interrupt requested when TOF flag set in TFLG2 register. 0 = Hardware Interrupt request inhibited.

4.18.3.3.12 Main Timer In terrupt Flag 1 (TFLG1)

channel flag CnF to be cleared. 0 = Inhibits Timer Counter reset and counter continues to run. These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 176. Table 176. Timer Clock Selection Table 177. Main Timer Interrupt Flag 1 (TFLG1)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 178. TFLG1 - Register Field Descriptions Input Capture/Output Compare Channel Flag. 0 = No event (Input Capture or Output Compare event) occurred. Table 175. TIE - Register Field Descriptions (continued)

4.18.3.3.13 Main Timer In terrupt Flag 2 (TFLG2)

4.18.3.3.14 Timer Input Capture/Outp ut Compare Registers (TC3 - TC0)

no effect during input capture. corresponding input capture edge detector or to trigger an output action for output compare. it will give a different result. Table 179. Main Timer Interrupt Flag 2 (TFLG2)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 180. TFLG2 - Register Field Descriptions 0 = Flag indicates an Interrupt has not occurred. Table 181. Timer Input Capture/Output Compare Register 0 (TC0)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 182. Timer Input Capture/Output Compare Register 1(TC1)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 183. Timer Input Capture/Output Compare Register 2(TC2)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 184. Timer Input Capture/Output Compare Register 3(TC3)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 185. TCn - Register Field Descriptions

16 Timer Input Capture/Output Compare Registers

4.18.4 Functional Description

4.18.4.1 General

Figure 36. Detailed Timer Block Diagram

4.18.4.2 Prescaler

The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64, or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in the timer system control register 2 (TSCR2).

4.18.4.3 Input Capture

timer transfers the value in the timer counter into the timer channel registers, TCn. The minimum pulse width for the input capture input is greater than two bus clocks. An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests.

4.18.4.4 Output Compare

the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests. disconnects the pin from the output logic. being used as the pulse accumulator input. Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.

4.18.5 Resets

4.18.5.1 General

details the registers and their bit-fields.

4.18.6 Interrupts

4.18.6.1 General

Table 186. TIM16B4C Interrupts

Functional Description and Application Information Basic Timer Module - TIM (TIM16B4C) MM912F634 Freescale Semiconductor 138

4.18.6.2 Description of Interrupt Operation

The TIM16B4C uses a total of 5 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. More information on interrupt vector offsets and interrupt numbers can be found in the Section 4.6, “Interrupts"

4.18.6.2.1 Channel [3:0] Interrupt

These active high outputs are asserted by the module to request a timer channel 3–0 interrupt, following an input capture or output compare event on these channels [3-0]. For the interrupt to be asserted on a specific channel, the enable, CnI bit of TIE register should be set. These interrupts are serviced by the system controller.

4.18.6.2.2 Timer Overfl ow Interrupt (TOF)

This active high output will be asserted by the module to request a timer overflow interrupt, following the timer counter overflow when the overflow enable bit (TOI) bit of TFLG2 register is set. This interrupt is serviced by the system controller.

4.19 Analog Digital Converter - ADC

4.19.1 Introduction

4.19.1.1 Overview

and high precision conversions. Figure 37. Analog Digital Converter Block Diagram

4.19.1.2 Features

• 10-bit resolution
• 13 µs (typ.), 10-bit Single Sample + Conversion Time
• External ADC2p5 pin with over-current protection to filter the analog reference voltage
• Total Error (TE) of ± 5 LSB without offset calibration active
• Integrated selectable offset compensation
• 14 + 1 analog channels (AD0…8; ISENSE, TSENSE and VSENSE, VS1SENSE, BANDGAP, plus calibration channel)
• Sequence- and Continuous Conversion Mode with IRQ for Sequence Complete indication
• Dedicated Result register for each channel

4.19.2 Modes of Operation

The Analog Digital Converter Module is active only in normal mode; it is disabled in Sleep and Stop mode.

4.19.3 External Signal Description

controlled by the Analog Digital Converter Module.

4.19.4 Memory Map and Register Definition

4.19.4.1 Module Memory Map

Table 187. ADC - Pin Functions and Priorities Table 188. Analog Digital Converter Module - Memory Map

Table 188. Analog Digital Converter Module - Memory Map (continued)

4.19.4.2 Register Definition

4.19.4.2.1 ADC Config Register (ACR)

ADCRST is strongly recommended to be set during D2D clock frequency changes.

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 189. ADC Config Register (ACR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 190. ACR - Register Field Descriptions

4.19.4.2.2 ADC Status Register (ASR)

4.19.4.2.3 ADC Conversion Control Register (ACCR)

Table 191. ADC Status Register (ASR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 192. ACR - Register Field Descriptions 7 - SCF Sequence Complete Flag. Reading the ADC Status Register (ASR) will clear the Flag. Table 193. ADC Conversion Control Register (ACCR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 190. ACR - Register Field Descriptions (continued)

4.19.4.2.4 ADC Conversion Comple te Status Register (ACCSR)

4.19.4.2.5 ADC Data Resu lt Register x (ADRx)

Table 194. ACCR - Register Field Descriptions Channel 15, if selected. Write to the Low Byte will not start a conversion. offset compensation functional. Table 195. ADC Conversion Complete Status Register (ACCSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 196. ACCSR - Register Field Descriptions recommended. 8-Bit read will return the current status, no latching will be performed. Table 197. ADC Data Result Register x (ADRx)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 198. ADRx - Register Field Descriptions high byte will clear the cc flag.

4.19.5 Functional Description

4.19.5.1 Analog Channel Definitions

4.19.5.2 Automatic Of fset Compensation

content. See Section 4.25, “MM912F634 - Analog Die Trimming". The reference is factory trimmed to 8 LSB. work with single and sequence conversion. Table 199. Analog Channels

0 AD0 - PTB0 Analog Input AD0

1 AD1 - PTB1 Analog Input AD1

2 AD2 - PTB2 Analog Input AD2

3 AD3 - L0 Analog Input AD3

4 AD4 - L1 Analog Input AD4

5 AD5 - L2 Analog Input AD5

6 AD6 - L3 Analog Input AD6

7 AD7 - L4 Analog Input AD7

8 AD8 - L5 Analog Input AD8

9 Current Sense ISENSE

10 Voltage Sense VSENSE

11 Temperature Sense TSENSE

12 VS1 Sense VS1SENSE

14 Bandgap (131) BANDGAP

15 Calibration Reference CAL

1. Internal “bg1p25sleep” reference.

Figure 38. Automatic Offset Compensation

4.19.5.3 Conversion Timing

needs to be configured to have the ADCCLK match the specified fADC clock limits.

• 9 cycle sampling time
• 18 cycle remaining conversion time
• A worst case (only channel 14) of 15 clock cycles to count up to the selected channel (15, 0, 1,....14)
• 4 cycles between two channels Example 1. Single Conversion Channel 10 (VSENSE) 12c (count up to Ch10) + 9c (sample) + 18c (conversion) = 39 cycles from start to end of conversion. Example 2. Sequence of Channel 10 (VSENSE) + Channel 15 (Offset Compensation) 1c (count) + 9c (sample Ch15) + 18c (conversion Ch15) + 4c (in between) + 0c (count further to Ch10 is performed while converting ch15) + 9c (sample) + 18c (conversion) = 59 cycles from start to end of both conversions. OCE – Offset Compensation Enable = 1 MCU – IFR (4C..4F) => CTR0..3 ACCR – ADC Conversion Control Register CH15=1 + CHx = 1 Read ADRx after SCF is set Sample CH15 Offset is calculated as difference between result and 8 LSB Sample CHx Adjust CHx Result by calculated offset CH15 is a trimmed reference of 8 LSB (requires CTRx) internal all x

4.20 Current Sense Module - ISENSE

Figure 39. Current Sense Module with External Filter Option eight different GAIN setting are implemented.

4.20.1 Register Definition

4.20.1.1 Current Sense Register (CSR)

Table 200. Current Sense Register (CSR)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 201. CSR - Register Field Descriptions

1. This feature should be used when implementing an external filt er to the current sense ISENSEx inputs. In principal an internal charge

compensation is activated in synch with the conversion to avoid the sample capacitors to be discharged by the external filter.

4.21 Temperature Sensor - TSENSE

temperature related gain of TSG can be routed to the internal Analog Digital Converter (Channel 11). Figure 40. TSENSE - Graph Refer to the Section 4.19, “Analog Digital Converter - ADC" for details on the channel selection and analog measurement.

4.22 Supply Voltage Sense - VSENSE

system power up and wake-up. The reverse battery protected VSENSE pin has been implemented to allow a direct measurement of the Battery level voltage. series resistor is required to protect the MM912F634 analog die from fast transients. Figure 41. VSENSE Module interrupt (LBI) to alert the MCU. Section 4.19, “Analog Digital Converter - ADC".

4.23 Internal Supply Voltage Sense - VS1SENSE

Section 4.19, “Analog Digital Converter - ADC" for details on the acquisition. Figure 42. VS1Sense Module

4.24 Internal Bandgap Refere nce Voltage Sense - BANDGAP

the 2p5sleep Bandgap circuity.

1. The maximum allowed sample frequency for Channel 14 is limit ed to fCH14. Increasing the sample frequency above can result in

unwanted turn off of the LS drivers due to a false VREG over-voltage.

4.25 MM912F634 - Analog Die Trimming

analog die trimming registers. The trimming registers will maintain their content during Low Power mode, Reset will set the default value.

4.25.1 Memory Map and Register Definition

4.25.1.1 Module Memory Map

SLPBG_LOCK bit has to stay at 0. is locked, no other trim on the parameter is possible. analog die trimming registers. The following table shows the register correlation. Table 202. MM912F634 Analog Die Trimming Registers

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 203. MM912F634 - MCU vs. Analog Die Trimming Register Correlation

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

4.25.1.2 Register Descriptions

4.25.1.2.1 Trimming Register 0 (CTR0)

4.25.1.2.2 Trimming Register 1 (CTR1)

Table 204. Trimming Register 0 (CTR0)

1. Offset related to 0x0200 for blocki ng access and 0x300 for non blocking access within the global address space.

Table 205. CTR0 - Register Field Descriptions Table 206. Trimming Register 1 (CTR1)

1. Offset related to 0x0200 for blocki ng access and 0x300 for non blocking access within the global address space.

4.25.1.2.3 Trimming Register 2 (CTR2)

Table 207. CTR1 - Register Field Descriptions Table 208. Trimming Register 2 (CTR2)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 209. CTR2 - Register Field Descriptions

4.25.1.2.4 Trimming Register 3 (CTR3)

VDDx over-voltage detection. Table 210. Trimming Register 3 (CTR3)

1. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 211. CTR3 - Register Field Descriptions Table 209. CTR2 - Register Field Descriptions (continued)

Functional Description and Application Information MM912F634 - MCU Die Overview MM912F634 Freescale Semiconductor 155

4.26 MM912F634 - MCU Die Overview

4.26.1 Introduction

The MC9S12I32 micro controller implemented in the MM912F634 is the first member of the newly introduced S12S platform, mainly targeted for Intelligent Distributed Control (IDC) applications. The MC9S12I32 device is designed as counter part to an analog die, and is not being offered as a standalone MCU. The MC9S12I32 die contains a HCS12 Central Processing Unit (CPU), offering 32 kB of Flash memory and 2.0 kB of system SRAM, up to six general purpose I/Os, an on-chip oscillator and clock multiplier, one Serial Peripheral Interface (SPI), an interrupt module, and debug capabilities via the on-chip debug module (DBG) in combination with the Background Debug Mode (BDM) interface. The MC9S12I32 die has no external bus interface, and thus no emulation capability as well as no internal voltage regulator. Additionally there is a die-to-die initiator (D2DI) which represents the communication interface to the companion (analog) die.

4.26.1.1 Features

• 16-Bit S12S CPU — Upward compatible with the CPU12 instruction set
• Note: Five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) are not supported on this device.
• INT (interrupt module) — Supporting nested interrupts
• MMC (memory mapping control and crossbar switch)
• DBG (debug module) — Monitoring of the CPU bus with tag- type or force-type breakpoint requests — 64 x 20-bit circular trace buffer captures c hange-of-flow or memory access information
• BDM (background debug mode)
• OSC (oscillator) — Full-swing Pierce oscillator option utilizi ng a 4.0 MHz to 16 MHz crystal or resonator
• CRG (clock and reset generation) — 32 kHz trimmable internal reference clock — Oscillator clock monitor — Internal Digital Controlled Oscillator ( DCO), Frequency Locked Loop (FLL) based
• COP module (Computer Operating Properly watchdog)
• RTI module (Real Time Interrupt)
• Memory Options — 32 k byte Flash — 2.0 k byte RAM
• Flash General Features — Erase sector size 512 bytes — Automated program and erase algorithm
• Serial Peripheral Interface Module (SPI) — Configurable for 8 or 16-bit data size
• Input/Output — Up to 6 general-purpose input/output (I/O) pins — Hysteresis on all input pins — Configurable drive strength on all output pins
• Die 2 Die Initiator (D2DI) — Up to 2.0 Mbyte/s data rate — Configurable 4-bit or 8-bit wide data path
• 20 MHz maximum CPU bus frequency (16 MHz for MM912F634CV2AP) ANALOGMCU

4.26.1.2 Modes of Operation

• Normal operating mode — Normal single-chip mode
• Special Operating mode — Special single-chip mode with active background debug mode Low-power modes:
• System stop mode
• System wait mode

4.26.2 Block Diagrams

Figure 43. MC9S12I32 Block Diagram

4.26.3 Device Memory Map

4.26.3.1 Address Mapping

internal resources in the memory map.

64 Byte Trace Buffer

Table 212. Device Internal Resources

1. Write access to Reserved has no effec t. Read access will return always 0x0000.
2. RAMSIZE is the hexadecimal va lue of RAM SIZE in bytes.
3. Accessing unimplemented FLASH pages causes an illegal address reset.
4. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes.

Figure 44. MC9S12I32 Global Address Mapping

4.26.4 Part ID Assignments

unique part ID for each revision of the chip. Table 213 shows the assigned part ID number and Mask Set number.

4.26.5 System Clock Description

shows the clock connections from the CRG to all modules. Consult the CRG specification for details on clock generation. Figure 45. Clock Connections Table 213. Assigned Part ID Numbers

1. The coding is as follows:

• The on-chip frequency locked loop (FLL).
• The oscillator. The clock generated by the FLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure 45, these system clocks are used throughout the MCU to drive the core, the memories, and the peripherals. The Flash memory is supplied by the bus clock which is also being used as a time base to derive the program and erase times for the NVM. In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the output of the oscillator. The clock monitor can be configured to generate a system reset if it is allowed to time out as a result of no oscillator clock being present.

4.26.6 Modes of Operation

are described in 4.26.6.2 Power Modes.

4.26.6.1 Chip Conf iguration Summary

The different modes and the security state of the MCU affect the debug features (enabled or disabled). MODC signal is registered into this bit on the rising edge of RESET.

4.26.6.1.1 Normal Single-chip Mode

the reset vector to be programmed correctly).The processor program is executed from internal memory.

4.26.6.1.2 Special Single-chip Mode

additional serial commands through the BKGD pin.

4.26.6.2 Power Modes

Table 214. Chip Modes

4.26.6.2.1 System Stop Mode

4.26.6.2.2 Wait Mode

individually turn off their local clocks. Asserting RESET, D2DINT, or any other interrupt that is not masked ends system wait mode.

4.26.6.2.3 Run Mode

Although this is not a low-power mode, unused peripheral modules should be disabled in order to save power.

4.26.6.2.4 Freeze Mode

RTI when the background debug module is active consult the corresponding module descriptions.

4.26.7 Security

4.26.7.1 MC9S12I32

the 4.36.6, “Flash Module Security“ description.

4.26.8 Resets and Interrupts

4.26.8.1 Resets

Resets are explained in detail in the 4.27, “Port Integration Module (9S12I32PIMV1)“ description.

4.26.8.2 Vectors

(9S12I32PIMV1)“) provides an interrupt vector base register (IVBR) to relocate the vectors. Table 215. Interrupt Vector Locations

4.26.8.3 Effects of Reset

descriptions for register reset states.

4.26.8.3.1 I/O Pins

Refer to the 4.27, “Port Integration Module (9S12I32PIMV1)“ description for reset configurations of all peripheral module ports.

4.26.8.3.2 Memory

The RAM array is not initialized out of reset.

1. 16 bits vector address based

Table 215. Interrupt Vector Locations (continued)

4.27 Port Integration Module (9S12I32PIMV1)

4.27.1 Introduction

available externally; if used in a dual-die package this interface is internal. and multiplexing on the shared pins and the pull-down functionality on specific pins.

4.27.2 Features

• 6-pin port A associated with the SPI module
• 2-pin port C used as D2DI clock output and D2DI interrupt input
• 8-pin port D used as 8 or 4-bit data I/O for the D2DI interface
• GPIO function shared on all pins
• Pull-down devices on PC1 and PD7-0 if used as D2DI inputs
• Reduced drive capability on port A on per pin basis The Port Integration Module includes these distinctive registers:
• Data registers for ports A, C, and D, when used as general-purpose I/O
• Data direction registers for ports A, C, and D, when used as general-purpose I/O
• Port input register on port A
• Reduced drive register on port A A standard port A pin has the following features:
• Input/output selection
• 5.0 V output drive
• 5.0 V digital input A standard port C and D pin has the following features:
• Input/output selection
• 2.5 V output drive
• 2.5 V digital input

4.27.3 Memory Map

Table 216. Memory Map

Table 216. Memory Map (continued)

4.27.3.1 Port A Data Register (PTA)

Table 217. Port A Data Register (PTA) Table 218. Port A Data Register Description synchronized pin input state is read. synchronized pin input state is read. Port A pin 3 is associated with the SS signal of the SPI module. When not used with the alternative function, this pin can be used as general purpose I/O. synchronized pin input state is read. Port A pin 2 is associated with the SCK signal of the SPI module. When not used with the alternative function, this pin can be used as general purpose I/O. synchronized pin input state is read. Port A pin 1 is associated with the MOSI signal of the SPI module. When not used with the alternative function, this pin can be used as general purpose I/O. synchronized pin input state is read. Port A pin 0 is associated with the MISO signal of the SPI module. When not used with the alternative function, this pin can be used as general purpose I/O. synchronized pin input state is read.

4.27.3.2 PIM Reserved Register

4.27.3.3 Port A Data Direction Register (DDRA)

4.27.3.4 PIM Reserved Register

Table 219. PIM Reserved Register Write: Unimplemented. Writing to this register has no effect. Table 220. Port A Data Direction Register (DDRA) Table 221. DDRA Register Field Descriptions This register controls the data direction of pins 5 through 0. The SPI function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input. Table 222. PIM Reserved Register Write: Unimplemented. Writing to this register has no effect.

4.27.3.5 Port C Data Register (PTC)

4.27.3.6 Port D Data Register (PTD)

Table 223. Port C Data Register (PTC) Table 224. PTC Register Field Descriptions Port C pin 1 is associated with the D2DINT signal of the D2DI module. When not used with the alternative function, this pin can be used as general purpose I/O. synchronized pin input state is read. Port C pin 0 is associated with the D2DCLK signal of the D2DI module. When not used with the alternative function, this pin can be used as general purpose I/O. synchronized pin input state is read. Table 225. Port D Data Register (PTD) Table 226. PTD Register Field Descriptions Port D pins 7 through 0 are associated with the D2DI data signals of the D2DI module if enabled in 8-bit mode. Port D pins 3 through 0 are associated with the D2DI data signals of the D2DI module if enabled in 4-bit mode. When not used with the alternative function, these pins can be used as general purpose I/O. synchronized pin input state is read.

4.27.3.7 Port C Data Direction Register (DDRC)

4.27.3.8 Port D Data Direction Register (DDRD)

Table 227. Port C Data Direction Register (DDRC) Table 228. DDRC Register Field Descriptions This register controls the data direction of pins 1 and 0. The D2DI function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input. Table 229. Port D Data Direction Register (DDRD) Table 230. DDRD Register Field Descriptions This register controls the data direction of pins 7 through 0. The D2DI function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.

4.27.3.9 PIM Reserved Registers

4.27.3.10 Port A Input Register (PTIA)

4.27.3.11 PIM Reserved Register

Table 231. PIM Reserved Registers Write: Unimplemented. Writing to these registers has no effect. Table 232. Port A Input Register (PTIA) Write: Unimplemented. Writing to this register has no effect.

1. u = Unaffected by reset

Table 233. PTIA Register Field Descriptions overload or short circuit conditions on output pins. Table 234. PIM Reserved Register Write: Unimplemented. Writing to this register has no effect.

4.27.3.12 Port A Reduced Drive Register (RDRA)

4.27.3.13 PIM Reserved Registers

Table 235. Port A Reduced Drive Register (RDRA)

1. Read: Anytime. Write: Anytime.

Table 236. RDRA Register Field Descriptions This register configures the drive strength of output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled. Table 237. PIM Reserved Register Write: Unimplemented. Writing to these registers has no effect.

4.27.4 Functional Description

4.27.4.1 General

4.27.4.2 Registers

4.27.4.2.1 Data register (PTx)

This register holds the value driven out to the pin, if the pin is used as a general purpose I/O. the buffered and synchronized state of the pin is returned, if the associated data direction register bit is set to “0”. other configuration (Figure 46).

4.27.4.2.2 Data direction register (DDRx)

This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 46).

4.27.4.2.3 Input register (PTIx)

This is a read-only register and always returns the buffered and synchronized state of the pin (Figure 46).

4.27.4.2.4 Reduced drive register (RDRx)

If the pin is used as an output this register allows the configuration of the drive strength. Figure 46. Illustration of I/O Pin Functionality

Functional Description and Application Information Port Integration Module (9S12I32PIMV1) MM912F634 Freescale Semiconductor 172

4.27.4.3 Ports

4.27.4.3.1 Port A

This port is associated with the SPI. Port A pins PA5-0 can be used for general-purpose I/O and PA3-0, also with the SPI subsystem.

4.27.4.3.2 Port C

This port is associated with the D2DI interface. Port C pins PC1-0 can be used either for general-purpose I/O, or as the D2DI interrupt input and D2DI clock output, respectively. A pull-down device is enabled on pin PC1 if used as D2DI input. The D2DI interrupt input is synchronized and has an asynchronous bypass in STOP mode to allow the generation of a wake-up interrupt.

4.27.4.3.3 Port D

This port is exclusively associated with the D2DI interface and not available externally. Port D pins PD7-0 can be used either for general-purpose I/O or with the D2DI data I/O. If the D2DI is enabled in 4-bit mode, pins PD7-4 can be used with general purpose pin functionality. Pull-down devices are enabled on all pins if used as D2DI inputs.

4.27.5 Initializat ion Information

4.27.5.1 Port Data and Data Direction Register writes

It is not recommended to write PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs.

4.28 Memory Mapping Control (S12SMMCV1)

4.28.1 Introduction

of the MMC is shown in Figure 47. to a global memory space using the PPAGE register.

4.28.1.1 Terminology

4.28.1.2 Features

• Paging capability to support a global 256 Kilobytes memory address space
• Bus arbitration between the masters CPU, BDM to different resources (internal and peripherals). Note: resources are also called targets.
• MCU operation mode control
• MCU security control
• Separate memory map schemes for each master CPU, BDM
• Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes

Table 238. Acronyms and Abbreviations Bus Clock System Clock. Refer to CRG Block Guide.

4.28.1.3 S12S Memory Mapping

• A (CPU or BDM) 64 kByte local map, defi ned using specific resource page (PPAGE) register and the default instruction set. The 64 Kilobytes visible at any instant can be considered as the local map accessed by the 16-bit (CPU or BDM) address.

4.28.1.4 Modes of Operation

This subsection lists and briefly describes all operating modes supported by the MMC.

4.28.1.4.1 Power Saving Modes

• R u n m o d e MMC is functional during normal run mode.
• Wait mode MMC is functional during wait mode.
• Stop mode MMC is inactive during stop mode.

4.28.1.4.2 Functional Modes

• Single chip modes In normal and special single chip mode the internal memory is used.

4.28.1.5 Block Diagram

Figure 47 shows a block diagram of the MMC. Figure 47. MMC Block Diagram External Signal Description

bonded out in all implementations. Table 239 outlines the pin names and functions. It also provides a brief description of their operation.

4.28.2 Memory Map and Registers

4.28.2.1 Module Memory Map

are given in the subsections that follow.

4.28.2.2 Register Descriptions

4.28.2.2.1 Program Page Index Register (PPAGE)

complete before the end of the instruction execution. Table 239. External Input Signals Associated with the MMC Figure 48. MMC Register Summary Table 240. Program Page Index Register (PPAGE)

Figure 49. PPAGE Address Mapping space. See SoC Guide for details. The fixed 16 k page from 0x4000–0x7FFF is the page number 0xFD. The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x0000 and 0xFFFF out of reset. The fixed 16 k page from 0xC000-0xFFFF is the page number 0xFF.

4.28.2.2.2 Direct Page Register (DIRECT)

Write: anytime in special modes, one time only in other modes. Table 241. PPAGE Field Descriptions to be accessed in the Program Page Window. Table 242. Direct Register (DIRECT)

Figure 50. Direct Address Mapping MOVB #0x80,DIRECT ;Set DIRECT re gister to 0x80. Write once only. ;Global data accesses to the range 0xXX_80XX can be direct. ;Logical data accesses to the range 0x80XX are direct. LDY <00 ;Load the Y index register from 0x8000 (direct access). ;automatically select direct mode. Table 243. DIRECT Field Descriptions Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. The bits from this register form bits [15:8] of the address (see Figure 50).

4.28.2.2.3 Mode Register (MODE)

Write: Only if a transition is allowed (see Figure 51). The MODC bit of the MODE register is used to establish the MCU operating mode. Figure 51. Mode Transition Diagram when MCU is Unsecured Table 244. Mode Register (MODE)

1. External signal (see Table 239).

Table 245. MODE Field Descriptions after the RESET signal goes inactive (see Figure 51). Write restrictions exist to disallow transitions between certain modes. Figure 51 illustrates all allowed mode changes.

4.28.2.2.4 MMC Control Register (MMCCTL1)

The IFRON bit of the MMCCTL1 register is used to make program IFR sector visible in the memory map.

4.28.3 Functional Description

4.28.3.1 MCU Operating Mode

• Normal single-chip mode There is no external bus in this mode. The MCU program is executed from the internal memory and no external accesses are allowed.
• Special single-chip mode This mode is generally used for debugging single-chip operation, boot-strapping or security related operations. The active background debug mode is in control of the CPU code execution and the BDM firmware is waiting for serial commands sent through the BKGD pin. There is no external bus in this mode.

4.28.3.2 Memory Map Scheme

4.28.3.2.1 CPU and BDM Memory Map Scheme

and WRITE_BD access cycles to distinguish between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block Guide for further details). module will not be visible in the memory map during active BDM mode. Figure 52. MMC Control Register (MMCCTL1) Table 246. MODE Field Descriptions This bit is used to make the IFR sector of the Program Flash visible in the global memory map. 0 Not visible in the global memory map.

1 Visible in the global memory map in the range (See Figure 44):

Functional Description and Application Information Memory Mappin g Control (S12SMMCV1) MM912F634 Freescale Semiconductor 180 Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value of 0xFF.

4.28.3.2.2 Expansion of the Local Address Map

The program page index register in MMC allows accessing up to 256 kbyte of FLASH or ROM in the global memory map by using the four page index bits to page 16x16 kbyte blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map. The page value for the program page window is stored in the PPAGE register. The value of the PPAGE register can be read or written by normal memory accesses as well as by the CALL and RTC instructions (see Section 4.28.4.1, “CALL and RTC Instructions"). Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64 kilobyte local CPU address space. The starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the PPAGE register will be set to the appropriate value when the service routine is called. However an interrupt service routine can call other routines that are in paged memory. The upper 16 kilobyte block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU memory map. PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. The four BDMPPR Program Page index bits allow access to the full 256 kbyte address map that can be accessed with 17 address bits. The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing a firmware command which uses CPU instructions, or by a BDM hardware commands. See the BDM Block Guide for further details. (see Figure 53).

Figure 53. BDMPPR Address Mapping

4.28.3.2.3 Implemen ted Memory Map

that the memory spaces have fixed top addresses.

Table 247. Global Implemented Memory Space

1. RAMSIZE is the hexadecimal va lue of RAM SIZE in bytes.
2. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes.

Figure 54. Local to Global Address Mapping

Figure 55. Implemented Global Address Mapping

4.28.3.3 Chip Bus Control

to specific target buses (see Figure 56). Figure 56. S12S Platform

4.28.3.3.1 Master Bus Prioritization Regarding Access Conflicts on Target Buses

• CPU always has priority over BDM.
• BDM has priority over CPU when its access is stalled for mo re than 128 cycles. In the later case the CPU will be stalled after finishing the current operation and the BDM will gain access to the bus.

4.28.3.4 Interrupts

Functional Description and Application Information Memory Mappin g Control (S12SMMCV1) MM912F634 Freescale Semiconductor 186

4.28.4 Initialization/A pplication Information

4.28.4.1 CALL and RTC Instructions

CALL and RTC instructions are not interruptable CPU instructions that automate page switching in the program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is called can be located anywhere in the local address space or in any Flash or ROM page visible through the program page window. The CALL instruction calculates and stacks a return address, stacks the current PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value controls which of the 256 possible pages is visible through the 16 kbyte program page window in the 64 kbyte local CPU memory map. Execution then begins at the address of the called subroutine. During the execution of the CALL instruction, the CPU performs the following steps: 1. Writes the current PPAGE value into an internal tempor ary register and writes the new instruction-supplied PPAGE value into the PPAGE register 2. Calculates the address of the next instruction after the CALL instruction (the return address) and pushes this 16-bit value onto the stack 3. Pushes the temporarily stor ed PPAGE value onto the stack 4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new address This sequence is not interruptable. There is no need to inhibit interrupts during the CALL instruction execution. A CALL instruction can be performed from any address to any other address in the local CPU memory space. The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction. In indexed-indirect variations of the CALL instruction a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Using indirect addressing for both the new page value and the address within the page allows usage of values calculated at run time rather than immediate values that must be known at the time of assembly. The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction after the CALL instruction. During the execution of an RTC instruction the CPU performs the following steps: 1. Pulls the previously stored PPAGE value from the stack 2. Pulls the 16-bit return address from the stack and loads it into the PC 3. Writes the PPAGE value into the PPAGE register 4. Refills the queue and resumes execution at the return address This sequence is uninterruptable. The RTC can be executed from anywhere in the local CPU memory space. The CALL and RTC instructions behave like JSR and RTS instruction, they however require more execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and CALL/RTC instructions should only be used when needed. The JSR and RTS instructions can be used to access subroutines that are already present in the local CPU memory map (i.e. in the same page in the program memory page window for example). However calling a function located in a different page requires usage of the CALL instruction. The function must be terminated by the RTC instruction. Because the RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the RTC instruction must be called using the CALL instruction even when the correct page is already present in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time of the RTC instruction execution.

Functional Description and Application Information Interrupt Module (S12SINTV1) MM912F634 Freescale Semiconductor 187

4.29 Interrupt Module (S12SINTV1)

4.29.1 Introduction

The 9S12I32PIMV1 module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to the CPU. The 9S12I32PIMV1 module supports:

• I bit and X bit maskable interrupt requests
• A non-maskable unimplemented opcode trap
• A non-maskable software interrupt (SWI) or background debug mode request
• Three system reset vector requests
• A spurious interrupt vector Each of the I bit maskable interrupt requests is assigned to a fixed priority level.

4.29.1.1 Glossary

CCR — Condition Code Register (in the CPU) ISR — Interrupt Service Routine MCU — Micro-controller Unit

4.29.1.2 Features

• Interrupt vector base register (IVBR)
• One spurious interrupt vector (at address vector base + 0x0080). The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte).
• 2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
• I bit maskable interrupts can be nested.
• One X bit maskable interrupt vector request (at address vector base + 0x00F4).
• One non-maskable software interrupt request (SWI) or ba ckground debug mode vector request (at address vector base + 0x00F6).
• One non-maskable unimplemented opcode trap (TRAP) vector (at address vector base + 0x00F8).
• Three system reset vectors (a t addresses 0xFFFA–0xFFFE).
• Determines the highest priority interrupt vector reques ts, drives the vector to the bus on CPU request
• Wakes up the system from stop or wait mode wh en an appropriate interrupt request occurs.

4.29.1.3 Modes of Operation

• R u n m o d e This is the basic mode of operation.
• Wait mode In wait mode, the clock to the 9S12I32PIMV1 module is disabled. The 9S12I32PIMV1 module is however capable of waking up the CPU from wait mode if an interrupt occurs. Please refer to Section 4.29.5.3, “Wake-up from Stop or Wait Mode"” for details.
• Stop mode In stop mode, the clock to the 9S12I32PIMV1 module is disabled. The 9S12I32PIMV1 module is however capable of waking up the CPU from stop mode if an interrupt occurs. Please refer to Section 4.29.5.3, “Wake-up from Stop or Wait Mode"” for details.
• Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to

4.29.1.4 Block Diagram

Figure 57 shows a block diagram of the 9S12I32PIMV1 module. Figure 57. 9S12I32PIMV1 Block Diagram

4.29.2 External Signal Description

The 9S12I32PIMV1 module has no external signals.

4.29.3 Memory Map and Register Definition

This section provides a detailed description of all registers accessible in the 9S12I32PIMV1 module.

4.29.3.1 Register Descriptions

This section describes in address order all the 9S12I32PIMV1 registers and their individual bits.

4.29.3.1.1 Interru pt Vector Base Register (IVBR)

Figure 58. Interrupt Vector Base Register (IVBR)

4.29.4 Functional Description

4.29.4.1 S12S Exception Requests

4.29.4.2 Interrupt Prioritization

interrupt requests, e.g., by nesting SWI or TRAP calls. more than one interrupt request is pending, the interrupt request with the higher vector address wins the prioritization. The following conditions must be met for an I bit maskable interrupt request to be processed.

1. The local interrupt enabled bit in the peripheral module must be set.
2. The I bit in the condition code regist er (CCR) of the CPU must be cleared.
3. There is no SWI, TRAP , or X bit maskable request pending.

highest priority vector and the system will process this interrupt request first, before the original interrupt request is processed.

4.29.4.3 Reset Exception Requests

1. Pin reset, power-on reset or illegal address reset

Table 248. IVBR Field Descriptions are set to 0xFF (i.e., vectors are located at 0xFF80–0xFFFE) to ensure compatibility to HCS12. non-maskable interrupts in the BDM firmware.

1. Clock monitor reset request
2. COP watchdog reset request

4.29.4.4 Exception Priority

the CPU is shown in Table 249.

4.29.5 Initialization/A pplication Information

4.29.5.1 Init ialization

1. Initialize the interrupt vector base register if the interrupt vector table is not located at the default location
2. Enable I bit maskable interrupts by clearing the I bit in the CCR.
3. Enable the X bit maskable interrupt by clearing the X bit in the CCR.

4.29.5.2 Interru pt Nesting

The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the CPU.

• I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority. I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests, per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the Ibit, other I bit maskable interrupt requests can interrupt the current ISR. An ISR of an interruptible I bit maskable interrupt request could basically look like this: 1. Service interrupt, e.g., clear interrupt flags, copy data, etc. 2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt requests) 3. Process data 4. Return from interrupt by executing the instruction RTI

Table 249. Exception Vector Map and Priority

1. 16 bits vector address based

Functional Description and Application Information Interrupt Module (S12SINTV1) MM912F634 Freescale Semiconductor 191

4.29.5.3 Wake-up from Stop or Wait Mode

4.29.5.3.1 CPU Wake-up from Stop or Wait Mode

Every I bit maskable interrupt request is capable of waking the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake-up the CPU or not, the same conditions as in normal run mode are applied during stop or wait mode:

• If the I bit in the CCR is set, all I bit maska ble interrupts are masked from wake-up the MCU. Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can wake-up the MCU from stop mode.

Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 192

4.30 Background Debug Module (S12SBDMV1)

4.30.1 Introduction

This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S core platform. The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. The BDM has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible to the BDM of the S12 family with the following exceptions:

• TAGGO command not su pported by S12SBDM
• External instruction tagging feat ure is part of the DBG module
• S12SBDM register map and register content modified
• Family ID readable from firmware ROM at global address 0x3_FF0F (value for devices with HCS12S core is 0xC2)
• Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)

4.30.1.1 Features

The BDM includes these distinctive features:

• Single-wire communication with host development system
• Enhanced capability for allowing more flexibility in clock rates
• SYNC command to determine communication rate
• GO_UNTIL (169) command
• Hardware handshake protocol to increase the performance of the serial communication
• Active out of reset in special single chip mode
• Nine hardware commands using free cycles, if available, for minimal CPU intervention
• Hardware commands not requiring active BDM
• 14 firmware commands execute from the standard BDM firmware lookup table
• Software control of BDM operation during wait mode
• When secured, hardware commands are allowed to access the r egister space in special single chip mode, if the Flash and EEPROM erase tests fail.
• Family ID readable from firmware ROM at global address 0x3_FF0F (value for devices with HCS12S core is 0xC2)
• BDM hardware commands are operational until system stop mode is entered

4.30.1.2 Modes of Operation

BDM is available in all operating modes but must be enabled before firmware commands are executed. Some systems may have a control bit that allows suspending the function during background debug mode.

4.30.1.2.1 Regular Run Modes

All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power during run mode.

• Normal modes General operation of the BDM is available and operates the same in all normal modes.
• Special single chip mode In special single chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory.

4.30.1.2.2 Secure Mode Operation

4.30.1.2.3 Low Power Modes

BDM is now ready to receive a new command.

4.30.1.3 Block Diagram

A block diagram of the BDM is shown in Figure 59. Figure 59. BDM Block Diagram

4.30.2 External Signal Description

A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. accordingly and a communication timeout (BDM soft reset) has occurred.

4.30.3 Memory Map and Register Definition

4.30.3.1 Module Memory Map

Table 250 shows the BDM memory map when BDM is active.

4.30.3.2 Register Descriptions

communications to the BDM hardware using READ_BD and WRITE_BD commands. Table 250. BDM Memory Map Figure 60. BDM Register Summary

4.30.3.2.1 BDM Status Register (BDMSTS)

4.30.3.2.2 BDM Status Register (BDMSTS)

modes, the BDMCCR register is read zero. not apply in special single chip mode). firmware lookup table upon exit from BDM active mode. by the BDM hardware or standard firmware lookup table as part of BDM command execution. Table 251. Register Global Address 0x3_FF01

1. ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased

(Flash). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed.

1. UNSEC is read as 1 by a debugging environment in special singl e chip mode when the device is secured and fully erased, else it is 0

and can only be read if not secure (see also bit description). Figure 60. BDM Register Summary (continued)

Table 252. BDMSTS Field Descriptions

0 BDM disabled

1 BDM enabled

secured, this bit will not be set by the firmware until after the Flash erase verify tests are complete. of the exit sequence to return to user code and remove the BDM memory from the map.

0 BDM not active

1 BDM active

control program flow execution.

0 Data phase of command not complete

1 Data phase of command is complete

0 TRACE1 command is not being executed

1 TRACE1 command is being executed

map overlapping the standard BDM firmware lookup table. turned off. If the erase test fails, the UNSEC bit will not be asserted. 0 System is in a secured mode. 1 System is in a unsecured mode. Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM. is configured for unsecure mode. Table 253. BDM CCR Holding Register (BDMCCR)

4.30.3.2.3 BDM Program Page Index Register (BDMPPR)

4.30.3.3 Family ID Assignment

ID which is 0xC2 for devices with HCS12S core.

4.30.4 Functional Description

hardware and firmware commands. register (X), Y index register (Y), stack pointer (SP), and program counter (PC). can only be executed when the system is not secure and is in active background debug mode (BDM). Table 254. BDM Program Page Register (BDMPPR) Table 255. BDMPPR Field Descriptions used for global accesses even if the BGAE bit is set.

0 BDM Program Paging disabled

1 BDM Program Paging enabled

the program page window scheme, refer to the S12S_MMC Block Guide.

Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 198

4.30.4.1 Security

If the user resets into special single-chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip EEPROM and Flash EEPROM are erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the EEPROM or Flash do not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the firmware commands. This allows the BDM hardware to be used to erase the EEPROM and Flash. BDM operation is not possible in any other mode than special single-chip mode when the device is secured. The device can only be unsecured via BDM serial interface in special single-chip mode. For more information regarding security, please see the S12S_9SEC Block Guide.

4.30.4.2 Enabling and Activating BDM

If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE. After being enabled, BDM is activated by one of the following (BDM is enabled and active immediately out of special single-chip reset):

• Hardware BACKGROUND command
• CPU BGND instruction
• Breakpoint force or tag mechanism (This me thod is provided by the S12S_DBG module) When BDM is activated, the CPU finishes executing the current instruction, and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0x3_FF00 to 0x3_FFFF. BDM registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs. When BDM is activated while CPU executes code overlapping with BDM firmware space the saved program counter (PC) will be auto incremented by one from the BDM firmware, no matter what caused the entry into BDM active mode (BGND instruction, BACKGROUND command or breakpoints). In such a case the PC must be set to the next valid address via a WRITE_PC command before executing the GO command.

4.30.4.3 BDM Hardware Commands

Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, Flash, I/O and control registers. requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. The BDM hardware commands are listed in Table 256. the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map. Table 256. Hardware Commands the part enters active background mode. ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse. Read from memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table in map. Read from memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table in map. Write to memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table out of map.

4.30.4.4 Standard BDM Firmware Commands

BACKGROUND is the usual way to activate BDM. watches for serial commands and executes them as they are received. The firmware commands are shown in Table 257. Table 257. Firmware Commands READ_NEXT(168) 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator. READ_X 65 16-bit data out Read X index register. READ_Y 66 16-bit data out Read Y index register. READ_SP 67 16-bit data out Read stack pointer. WRITE_NEXT 42 16-bit data in Increment X index register by 2 (X = X + 2), then write word to location pointed to by X. WRITE_PC 43 16-bit data in Write program counter. WRITE_D 44 16-bit data in Write D accumulator. WRITE_X 45 16-bit data in Write X index register. WRITE_Y 46 16-bit data in Write Y index register. WRITE_SP 47 16-bit data in Write stack pointer. GO 08 none Go to user program. If enabled, ACK wi ll occur when leaving active background mode. returning to active background mode.

1. If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete
2. When the firmware command READ_NEXT or WRITE_NEXT is us ed to access the BDM address space the BDM resources are

accessed rather than user code. Writing BDM firmware is not possible.

1. System stop disables the ACK function an d ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode). The

again) is reached (see Section 4.30.4.7, “Serial Interface Hardware Handshake Protocol"” last Note).

Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 201

4.30.4.5 BDM Command Structure

If the bus rate of the target processor is unknown or could be changing, it is recommended that the ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16-bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. Figure 61 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is

Figure 61. BDM Command Structure

4.30.4.6 BDM Serial Interface

times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. earlier. Synchronization between the host and target is established in this manner at the start of every bit time.

8 Bits

16 Bits

Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. Figure 62. BDM Host-to-Target Serial Bit Timing after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. Figure 63. BDM Target-to-Host Serial Bit Timing (Logic 1)

10 Cycles

cycles after starting the bit time. Figure 64. BDM Target-to-Host Serial Bit Timing (Logic 0)

4.30.4.7 Serial Interface Ha rdware Handshake Protocol

wait or stop mode, the BDM command is no longer pending. sub-section will describe the hardware handshake protocol. pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 65). accurate time measurement or short response time to any event in the serial communication.

Figure 65. Target Acknowledge Pulse (ACK) of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even. Figure 66. Handshake Protocol at Command Level potential conflict time becomes longer as well. electrical conflict in the BKGD pin.

16 Cycles

32 Cycles

Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 206 NOTE The ACK pulse does not provide a timeout. This means for the GO_UNTIL(169) command that it can not be distinguished if a stop or wait has been executed (command discarded and ACK not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command. See the handshake abort procedure described in Section 4.30.4.8, “Hardware Handshake Abort Procedure"”. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted.

4.30.4.8 Hardware Handshake Abort Procedure

The abort procedure is based on the SYNC command. In order to abort a command, which has not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 4.30.4.9, “SYNC — Request Timed Reference Pulse"”, and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it can not be guaranteed that the pending command is aborted when issuing a SYNC before the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware READ or WRITE command that is issued and on the selected bus clock rate. When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL(169) command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command. Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 4.30.4.9, “SYNC — Request Timed Reference Pulse"”.

Figure 67. ACK Abort Procedure at the Command Level along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conflict from happening. Figure 68. ACK Pulse and SYNC Request Conflict

Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 208 The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. The commands are described as follows:

• ACK_ENABLE — enables the hardware handshake protoc ol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response.
• ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed, and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin, and when the data bus cycle is complete. See Section 4.30.4.3, “BDM Hardware Commands"” and Section 4.30.4.4, “Standard BDM Firmware Commands"” for more information on the BDM commands. The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL(169) command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs, and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command.

4.30.4.9 SYNC — Request Timed Reference Pulse

The SYNC command is unlike other BDM commands, because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (the lowest serial communication frequency is determined by either DCO clock or external crystal oscillator depending on the configuration chosen in the CRG.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high-impedance. 4. Listen to the BKGD pin for the sync response pulse.

Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 209 Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic one. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the cu rrent BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high-impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed, and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a timeout in the serial communication. After the SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command not to be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued.

4.30.4.10 Instruction Tracing

When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware, and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist. Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address pointing to BDM firmware address space. When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving the low power mode. This is the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM hardware commands except the BACKGROUND command are operational after tracing a stop or wait instruction, and still in stop or wait mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational. As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the corresponding interrupt service routine. In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command.

Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 210

4.30.4.11 Serial Communication Timeout

The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any timeout limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. However, if a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft reset. If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft reset will occur causing the command to be disregarded. The data is not available for retrieval after the timeout has occurred. This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake protocol is enabled, the timeout between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the timeout feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the timeout period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the timeout in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges, and the command being issued or data being retrieved is not complete, a soft reset will occur causing the partially received command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.

Functional Description and Application Information S12S Debug (S12SDBGV1) Module MM912F634 Freescale Semiconductor 211

4.31 S12S Debug (S 12SDBGV1) Module

4.31.1 Introduction

The S12SDBGV1 module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The S12SDBGV1 module is optimized for S12SCPU debugging. Typically the S12SDBGV1 module is used in conjunction with the S12SBDM module, whereby the user configures the S12SDBGV1 module for a debugging session over the BDM interface. Once configured the S12SDBGV1 module is armed and the device leaves BDM returning control to the user program, which is then monitored by the S12SDBGV1 module. Alternatively, the S12SDBGV1 module can be configured over a serial interface using SWI routines.

4.31.1.1 Glossary Of Terms

COF — Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt. BDM — Background Debug mode S12SBDM — Background Debug module WORD — 16 bit data entity Data Line — 20 bit data entity CPU — S12SCPU module DBG — S12SDBG module Tag — Tags can be attached to CPU opcodes as they ent er the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs.

4.31.1.2 Overview

The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated. Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered immediately by writing to the TRIG control bit. The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured.

4.31.1.3 Features

• Three comparators (A, B, and C) — Comparators A compares the full address bus and full 16-bit data bus — Comparator A features a data bus mask register — Comparators B and C compare the full address bus only — Each comparator features selectio n of read or write access cycles — Comparator B allows selection of byte or word access cycles — Comparator matches can initiate state sequencer transitions
• Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin ≤ Address ≤ Addmax — Outside address range match mode, Address < Addmin or Address > Addmax
• Two types of matches — Tagged — This matches just before a specific instruction begins execution — Force — This is valid on the first in struction boundary after a match occurs
• Two types of breakpoints — CPU breakpoint entering BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI)
• Trigger mode independent of comparators — TRIG Immediate software trigger

• Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 4.31.4.5.3, “Normal Mode") for change of flow definition. — Loop1: same as Normal but inhibits co nsecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Pure PC: All program counter addresses are stored
• 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin and End alignment of tracing to trigger

4.31.1.4 Modes of Operation

The DBG module can be used in all MCU functional modes. BDM Mode through a BACKGROUND command, the DBG module, if already armed, remains armed.

4.31.1.5 Block Diagram

Figure 69. Debug Module Block Diagram Table 258. Mode Dependent Restriction Summary

4.31.2 External Signal Description

There are no external signals associated with this module.

4.31.3 Memory Map and Registers

4.31.3.1 Module Memory Map

bits are given in the subsections that follow. Table 259. Quick Reference to DBG Registers

4.31.3.2 Register Descriptions

4.31.3.2.1 Debug Control Register 1 (DBGC1)

being written. These bits must be cleared using a second write if required. Bit 6 can be written anytime but always reads back as 0. Bits 4:3 anytime DBG is not armed.

1. This bit is visible at DBGCNT[7] and DBGSR[7]
2. This represents the contents if the Comparator A control register is blended into this address.
3. This represents the contents if the Comparator B control register is blended into this address.
4. This represents the contents if the Comparator C control register is blended into this address.

Table 260. Debug Control Register (DBGC1) Table 261. DBGC1 Field Descriptions this bit the state sequencer enters State1.

0 Debugger disarmed

1 Debugger armed

Table 259. Quick Reference to DBG Registers (continued)

4.31.3.2.2 Debug Status Register (DBGSR)

Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of comparator status. 0 Do not trigger until the state sequencer enters the Final State.

1 Enter Final State immediately and issue fo rced breakpoint request on tracing completion

module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. tracing is not enabled, the breakpoint is generated immediately.

0 No Breakpoint generated

1 Breakpoint generated

is visible at the address 0x0027. See Table 262. Table 262. COMRV Encoding

00 Comparator A DBGSCR1

01 Comparator B DBGSCR2

10 Comparator C DBGSCR3

11 None DBGMFR

Table 263. Debug Status Register (DBGSR) Table 264. DBGSR Field Descriptions This bit is also visible at DBGCNT[7]. Table 261. DBGC1 Field Descriptions (continued)

4.31.3.2.3 Debug Trace Control Register (DBGTCR)

Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed. Table 265. SSF[2:0] — State Sequence Flag Bit Encoding

000 State0 (disarmed)

001 State1

010 State2

011 State3

100 Final State

Table 266. Debug Trace Control Register (DBGTCR) Table 267. DBGTCR Field Descriptions secured, this bit cannot be set and tracing is inhibited. This bit must be set to read the trace buffer.

0 Debug session without tracing requested

1 Debug session with tracing requested

counter value for each instruction executed is stored. See Table 268. Trigger Align Bit — This bit controls whether the trigger is al igned to the beginning or end of a tracing session.

0 Trigger at end of stored data

1 Trigger before storing data

Table 268. TRCMOD Trace Mode Bit Encoding

00 Normal

Table 264. DBGSR Field Descriptions (continued)

4.31.3.2.4 Debug Contro l Register2 (DBGC2)

Write: Anytime the module is disarmed. This register configures the comparators for range matching.

4.31.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)

Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set.

01 Loop1

10 Detail

11 Pure PC

Table 269. Debug Control Register2 (DBGC2) Table 270. DBGC2 Field Descriptions Table 271. ABCM Encoding 00 Match0 mapped to comparator A match: Match1 mapped to comparator B match. 01 Match 0 mapped to comparator A/B inside range: Match1 disabled. 10 Match 0 mapped to comparator A/B outside range: Match1 disabled.

11 Reserved (174)

1. Currently defaults to Comparator A, Comparator B disabled.

Table 272. Debug Trace Buffer Register (DBGTB) Table 268. TRCMOD Trace Mode Bit Encoding (continued)

Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents.

4.31.3.2.6 Debug Count Register (DBGCNT)

Table 273. DBGTB Field Descriptions and for reads with the TSOURCE bit clear. The POR state is undefined. Other resets do not affect the trace buffer contents. Table 274. Debug Count Register (DBGCNT) Table 275. DBGCNT Field Descriptions Table 276. CNT Decoding Table ARM bit will be cleared and the tracing session ends.

4.31.3.2.7 Debug Stat e Control Registers

allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. Write: If COMRV[1:0] = 00 and DBG is not armed. comparator enable bit in the associated DBGXCTL control register. Table 277. State Control Register Access Encoding

00 DBGSCR1

01 DBGSCR2

10 DBGSCR3

11 DBGMFR

Table 278. Debug State Control Register 1 (DBGSCR1) Table 279. DBGSCR1 Field Descriptions These bits select the targeted next state whilst in State1, based upon the match event. Table 276. CNT Decoding Table (continued)

(0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches. Write: If COMRV[1:0] = 01 and DBG is not armed. comparator enable bit in the associated DBGXCTL control register. Table 280. State1 Sequencer Next State Selection

000 Any match to Final State

001 Match1 to State3

010 Match2 to State2

011 Match1 to State2

Table 281. Debug State Control Register 2 (DBGSCR2) Table 282. DBGSCR2 Field Descriptions These bits select the targeted next state whilst in State2, based upon the match event. Table 283. State2 —Sequenc er Next State Selection

010 Match2 to State3

101 Match2 Final State

111 Match2 has no affect, all other matches (M0,M1) to Final State

Write: If COMRV[1:0] = 10 and DBG is not armed. comparator enable bit in the associated DBGXCTL control register. (0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches. Table 284. Debug State Control Register 3 (DBGSCR3) Table 285. DBGSCR3 Field Descriptions These bits select the targeted next state whilst in State3, based upon the match event. Table 286. State3 — Sequencer Next State Selection

000 Match0 to State1

100 Match1 to State2

101 Match1 to Final State

111 Match0 to Final State

flags. Once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag.

4.31.3.2.8 Comparator Register Descriptions

Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map. register). Comparator C consists of four register bytes (three address bus compare registers and a control register). Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g. from those of comparators A and C. Table 287. Debug Match Flag Register (DBGMFR) Table 288. Comparator Register Layout

DBG module register address map. Table 289. Debug Comparator Control Register DBGACTL (Comparator A) Table 290. Debug Comparator Control Register DBGBCTL (Comparator B) Table 291. Debug Comparator Control Register DBGCCTL (Comparator C) Table 292. DBGXCTL Field Descriptions comparator. This bit is ignored if the TAG bit in the same register is set.

0 Word/Byte access size is not used in comparison

1 Word/Byte access size is used in comparison

only available for comparator A.

0 Match on data bus equivalence to comparator register contents

1 Match on data bus difference to comparator register contents

0 Word access size will be compared

1 Byte access size will be compared

is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue. The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F.

0 Allow state sequencer transition immediately on match

0 The debug session termination is dependent upon t he state sequencer and trigger conditions. is terminated and the module disarmed. comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set.

0 Write cycle will be matched

1 Read cycle will be matched

0 Read/Write is not used in comparison

1 Read/Write is used in comparison

0 The comparator is not enabled

1 The comparator is enabled

Table 293. Read or Write Comparison Logic Table Table 294. Debug Comparator Address High Register (DBGXAH) Table 295. Comparator Address Register Visibility

00 DBGAAH, DBGAAM, DBGAAL

Table 292. DBGXCTL Field Descriptions (continued)

Read: Anytime. See Table 296 for visible register encoding. Write: If DBG not armed. See Table 296 for visible register encoding. Read: Anytime. See Table 297 for visible register encoding. Write: If DBG not armed. See Table 297 for visible register encoding.

01 DBGBAH, DBGBAM, DBGBAL

10 DBGCAH, DBGCAM, DBGCAL

11 None

Table 296. DBGXAH Field Descriptions comparator will compare the address bus bits [17:16] to a logic one or logic zero.

0 Compare corresponding address bit to a logic zero

1 Compare corresponding address bit to a logic one

Table 297. Debug Comparator Address Mid Register (DBGXAM) Table 298. DBGXAM Field Descriptions comparator will compare the address bus bits [15:8] to a logic one or logic zero. Table 295. Comparator Address Register Visibility (continued)

Read: Anytime. See Table 300 for visible register encoding. Write: If DBG not armed. See Table 300 for visible register encoding. Write: If COMRV[1:0] = 00 and DBG not armed. Table 299. Debug Comparator Address Low Register (DBGXAL) Table 300. DBGXAL Field Descriptions comparator will compare the address bus bits [7:0] to a logic one or logic zero. Table 301. Debug Comparator Data High Register (DBGADH) Table 302. DBGADH Field Descriptions performed if the TAG bit in DBGACTL is clear.

0 Compare corresponding data bit to a logic zero

1 Compare corresponding data bit to a logic one

Write: If COMRV[1:0] = 00 and DBG not armed. Write: If COMRV[1:0] = 00 and DBG not armed. Table 303. Debug Comparator Data Low Register (DBGADL) Table 304. DBGADL Field Descriptions Table 305. Debug Comparator Data High Mask Register (DBGADHM) Table 306. DBGADHM Field Descriptions 0 Do not compare corresponding data bit. Any value of corresponding data bit allows match.

1 Compare corresponding data bit

Write: If COMRV[1:0] = 00 and DBG not armed.

4.31.4 Functional Description

generate breakpoints, but tracing is not possible.

4.31.4.1 S12SDBGV1 Operation

sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity. Comparator A can also be configured to monitor databus activity and mask out individual data bus bits during a compare. tracing is triggered and/or a breakpoint can be generated. Table 307. Debug Comparator Data Low Mask Register (DBGADLM) Table 308. DBGADLM Field Descriptions

Figure 70. DBG Overview

4.31.4.2 Comparator Modes

and DBGADL, and allows masking of individual data bus bits. All comparators are disabled in BDM and during BDM accesses. configuration is controlled by the control register contents and the range control by the DBGC2 contents. to be considered in the compare. Only comparator B features SZE and SZ. the comparator address register must be loaded with the exact opcode address. of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). value when a subsequent match occurs.

4.31.4.2.1 Exact Address Comparator Match (Comparators A and C)

comparator address/data registers. Further qualification of the type of access (R/W, word/byte) is possible. contents, or when the data bus is equivalent to the comparator register contents.

4.31.4.2.2 Exact Address Comparator Match (Comparator B)

same as for comparators A and C. Table 309. Comparator A Data Bus Considerations Table 310. Comparator Access Size Considerations

1. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address

register must contain the exact address used in the code.

Functional Description and Application Information S12S Debug (S12SDBGV1) Module MM912F634 Freescale Semiconductor 231

4.31.4.2.3 Range Comparisons

Using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A TAG bit is used to tag range comparisons. The comparator B TAG bit is ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is ignored in range mode. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons. This configuration depends upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary is valid only if the aligned address is inside the range. In the outside range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid only if the aligned address is outside the range. Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an unexpected range. In forced match mode the outside range match would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or lower range limit to $00000 respectively.

4.31.4.3 Match Modes (Forced or Tagged)

Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register TAG bits select the match mode. The modes are described in the following sections.

4.31.4.3.1 Fo rced Match

When configured for forced matching, a comparator channel match can immediately initiate a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state. Forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent of comparator RWE/RW settings. Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an opcode address typically precedes a tagged match at the same address.

4.31.4.3.2 Tagged Match

If a CPU taghit occurs a transition to another state, sequencer state is initiated, and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition.

4.31.4.3.3 Immediate Trigger

Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint, by writing to the TRIG bit in DBGC1. This forces the state sequencer into the Final State and issues a forced breakpoint request to the CPU.

4.31.4.3.4 Channel Priorities

4.31.4.4 State Sequence Control

Figure 71. State Sequencer Diagram the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. sequencer enters state0 and the debug module is disarmed. Table 311. Channel Priorities

Functional Description and Application Information S12S Debug (S12SDBGV1) Module MM912F634 Freescale Semiconductor 233

4.31.4.4.1 Final State

On entering Final State, a trigger may be issued to the trace buffer according to the trace alignment control, as defined by the the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case, or upon completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed.

4.31.4.5 Trace Buffer Operation

The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next read will receive fresh information. Data is stored in the format shown in Table 312. After each store, the counter register DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer, whilst the DBG is armed, returns invalid data and the trace buffer pointer is not incremented.

4.31.4.5.1 Trace Trigger Alignment

Using the TALIGN bit (see Section 4.31.3.2.3, “Debug Trace Control Register (DBGTCR)"”) it is possible to align the trigger with the end or the beginning of a tracing session. If End tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State signals the end of the tracing session. Tracing with Begin Trigger starts at the opcode of the trigger. Using End Trigger, or when the tracing is initiated by writing to the TRIG bit whilst configured for Begin-Trigger, tracing starts at the second opcode after writing to DBGC1 Storing with Begin Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the DBG module will remain armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction, the change of flow associated with the trigger will be stored in the Trace Buffer. Using Begin Trigger together with tagging, if the tagged instruction is about to be executed, then the trace is started. Upon completion of the tracing session, the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. Storing with End Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module will become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.

4.31.4.5.2 Trace Modes

Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections. The trace buffer organization is shown in Table 312.

Functional Description and Application Information S12S Debug (S12SDBGV1) Module MM912F634 Freescale Semiconductor 234

4.31.4.5.3 Normal Mode

In Normal mode, change of flow (COF) program counter (PC) addresses will be stored. COF addresses are defined as follows:

• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
• Destination address of indexed JMP, JSR, and CALL instruction
• Destination address of RTI, RTS, and RTC instructions
• Vector address of interrupts, except for BDM vectors LBRA, BRA, BSR, BGND, as well as non-indexed JMP, JSR, and CALL instructions, are not classified as change of flow and are not stored in the trace buffer. Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. NOTE When a COF instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously, then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets executed after the interrupt service routine. In the following example, an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine, but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place. LDX #SUB_1 MARK1 JMP 0,X ; IRQ interrupt occurs during execution of this MARK2 NOP ; SUB_1 BRN * ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 NOP ; ADDR1 DBNE A,PART5 ; Source address TRACE BUFFER ENTRY 4 IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 STAB VAR_C1 RTI ; The execution flow taking into account the IRQ is as follows LDX #SUB_1 MARK1 JMP 0,X ; IRQ_ISR LDAB #$F0 ; STAB VAR_C1 RTI ; SUB_1 BRN * NOP ; ADDR1 DBNE A,PART5 ;

Functional Description and Application Information S12S Debug (S12SDBGV1) Module MM912F634 Freescale Semiconductor 235 NOTE In certain very tight loops, the source address will have already been fetched again before the background comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below: Loop1 mode, similarly to Normal mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches. Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. LOOP INX ; 1-byte instruction fe tched by 1st P-cycle of BRCLR BRCLR CMPTMP,#$0c,LOOP ; the BRCLR in struction also will be fetched by 1st ; P-cycle of BRCLR LOOP2 BRN * ; 2-byte instruction fetched by 1st P-cycle of DBNE NOP ; 1-byte instruction fe tched by 2nd P-cycle of DBNE DBNE A,LOOP2 ; this instruction al so fetched by 2nd P-cycle of DBNE In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes, where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information bit storage to the trace buffer, for each address byte storage. The information bits indicates the size of access (word or byte) and the type of access (read or write). When tracing in Detail mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle. NOTE: When tracing is terminated using forced breakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoint can be stored to the trace buffer. The number of opcodes is dependent on program flow. This should be avoided by using tagged breakpoints. In Pure PC mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal opcodes are stored.

4.31.4.5.4 Trace Buffer Organization

Single byte data accesses in Detail mode is always stored to the low byte of the trace buffer (DATAL) and the high byte is cleared. The format of the bits is dependent upon the active trace mode, as described by the following. In Detail mode, the CSZ and CRW bits indicate the type of access being made by the CPU. Table 312. Trace Buffer Organization(20-bit wide buffer)

0 DATAH1 DATAL1

0 DATAH2 DATAL2

Table 313. Field2 Information Bits in Detail Mode Table 314. Field Descriptions

0 Word Access

1 Byte Access

0 Write Access

1 Read Access

Address Bus bit 17— Corresponds to system address bus bit 17. Address Bus bit 16— Corresponds to system address bus bit 16.

4.31.4.5.5 Reading Data from Trace Buffer

can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. first-out. By reading CNT in DBGCNT, the number of valid lines can be determined. DBGCNT will not decrement as data is read. oldest data entry, thus if no overflow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. buffer read sequence to be easily restarted from the oldest data entry. field 2 in the least significant bits [3:0] and “0” for bits [15:4]. Reading the Trace Buffer while the DBG module is armed, will return invalid data and no shifting of the RAM pointer will occur.

4.31.4.5.6 Trace Buffer Reset State

no information would be stored in the trace buffer. Table 315. Information Bits PCH Table 316. PCH Field Descriptions or destination address. This bit has no meaning in Pure PC mode.

0 Source Address

1 Destination Address

0 Non-Vector Destination Address

1 Vector Destination Address

Program Counter bit 17— In Normal, Pure PC, and Loop1 mode this bit corresponds to program counter bit 17. Program Counter bit 16— In Normal, Pure PC, and Loop1 mode this bit corresponds to program counter bit 16.

4.31.4.6 Tagging

the queue, a tag hit occurs and can initiate a state sequencer transition. address stored in the comparator match address registers must be an opcode address. to Final State, then a breakpoint is generated immediately before the tagged instruction is carried out. since the tag is attached to the opcode at the matched address, and is not dependent on the data bus nor on the size of access. Thus these bits are ignored if tagging is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. Tagging is disabled when the BDM becomes active.

4.31.4.7 Breakpoints

4.31.4.7.1 Breakpoints From Comparator Channels

breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment. Table 317. Breakpoint Setup For CPU Breakpoints

4.31.4.7.2 Breakpoints Generated Via the TRIG Bit

4.31.4.7.3 Breakpoint Priorities

channel match, it has no effect, since tracing has already started. the breakpoint to SWI is suppressed. BDM/SWI service routine, care must be taken to avoid a repeated breakpoint at the same address. is the first instruction executed when normal program execution resumes. Table 318. Breakpoint Mapping Summary

0 X X X No Breakpoint

Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) MM912F634 Freescale Semiconductor 240

4.32 S12S Clocks and Reset Generator (S12SCRGV1)

4.32.1 Introduction

This specification describes the function of the Clocks and Reset Generator (S12SCRGV1).

4.32.1.1 Features

The main features of this block are:

• Internal 32 kHz reference clock generator: — Trimmable in frequency ± 2% deviation over voltage and temperature for a fixed trim value. — Factory trimmed value in Flash Memory
• Optional external crystal or resonator: — Full swing Pierce Oscillator for crystals or resonators from 4.0 MHz to 16 MHz — Oscillator Monitor to detect loss of clock
• Internal digitally controlled oscillator (DCO): — Allows to generate frequencies in the range from 32 MHz to 40 MHz — Stable frequency by using a reference clock in a Frequency Locked Loop (FLL). — FLL based on either Internal Reference Clock (32 kHz) or optional external crystal/resonator (for higher accuracy). — Interrupt request on entry or exit from FLL locked condition
• Bus Clock Generator — Clock switch for DCO or optional ex ternal crystal/resonator based Bus Clock — Bus Clock divider to choose system speed
• System Reset generation from the following possible sources: — Power-on detect — Illegal address access — COP timeout — Loss of external Oscillator Clock (Oscillator monitor fail) — External pin RESET

4.32.1.2 Modes of Operation

This subsection lists and briefly describes all operating modes supported by the 9S12I32PIMV1.

4.32.1.2.1 Run Mode

• FLL Engaged Internal (FEI) — This is the default mode after System Reset and Power-on Reset. — The FLL reference is the Internal Reference Clock. — The Bus Clock is based on the DCO Clock.
• FLL Engaged External (FEE) — This mode is entered by: – enabling the external Oscillator (OSCEN bit) – programming the reference divider (RDIV[2:0] bits) – selecting the divided down Oscillator Cl ock as FLL reference clock (REFS bit) — The FLL reference is the Oscillator Clock. — The Bus Clock is based on the DCO Clock.
• FLL Bypassed External (FBE) — This mode is entered by: – enabling the external Oscillator (OSCEN bit) – selecting the Oscillator Clock as basis for Bus Clock (BCLKS bit) — The DCO Clock is turned off. — The Bus Clock is based on the Oscillator Clock.

Functional Description and Application Information S12S Clocks and Reset Generator (S12SCRGV1) MM912F634 Freescale Semiconductor 241

4.32.1.2.2 Wait Mode

For 9S12I32PIMV1 Wait mode is same as Run mode.

4.32.1.2.3 Stop Mode

• This mode is entered by executing the CPU STOP instruction.
• The Bus Clock is turned off.
• The Oscillator Clock and the Oscillator Monitor is turned off.
• The DCO Clock is turned off.
• The Internal Reference Clock can be kept enabled by periphe rals like e.g. the Real Time Interrupt module (RTI). See device and other block descriptions for details.

4.32.1.3 Block Diagram

Figure 72 shows a block diagram of the 9S12I32PIMV1.

Figure 72. Block diagram of 9S12I32PIMV1

4.32.2 Signal Description

This section lists and describes the signals that connect off chip.

4.32.2.1 RESET

open-drain output it indicates that a System Reset or Power-on Reset (internal to MCU) has been triggered.

4.32.3 Memory Map and Registers

This section provides a detailed description of all registers accessible in the 9S12I32PIMV1.

4.32.3.1 Module Memory Map

Table 319 gives an overview on all 9S12I32PIMV1 registers.

4.32.3.2 Register Descriptions

This section describes in address order all the 9S12I32PIMV1 registers and their individual bits. Table 319. 9S12I32PIMV1 Register Summary

Write: See individual bit descriptions. Writing the CRGCTL0 register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register. Table 320. 9S12I32PIMV1 Control Register 0 (CRGCTL0) Table 321. CRGCTL0 Field Descriptions 0 Oscillator Clock and Oscill ator Monitor are disabled. 1 Oscillator Clock and Oscill ator Monitor are enabled. These bits divide the Oscillator Clock down in frequency. Divided down frequency must be in the allowed range for fFLLREF. See device electrical characteristics for details.

111 Reserved

Writing BCLKS = 1 is only possible if oscillator startup flag is set (UPOSC = 1). BCLKS is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop Mode. 0 DCO Clock is selected as basis for the Bus Clock. 1 Oscillator Clock is selected as basis for the Bus Clock. DCO is disabled. Writing REFS = 1 is only possible if oscillator startup flag is set (UPOSC = 1). REFS is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop Mode. 0 Internal Reference Clock is selected as FLL Reference Clock. 1 Divided down Oscillator Clock is selected as FLL Reference Clock.

4.0 MHz Oscillator low pass filter select Bit

frequency noise immunity. Writing OSC4MHZ is only possible if OSCEN was zero before. 0 Oscillator uses noise filter with high bandwid th. To be used with crystals/resonators > 4.0 Mhz. case of a 4.0 MHz crystal/resonator further improves noise immunity at lower frequencies.

This register determines the multiplication factor to generate the DCO Clock. Writing the CRGMULT register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register. Table 322. 9S12I32PIMV1 Control Register (CRGCTL1) Table 323. CRGCTL1 Field Descriptions the Core Clock. Bus frequency is Core frequency divided by 2. 0 FLL Lock Interrupt requests are disabled. 1 FLL Lock Interrupt will be requested whenever LOCKIF is set. Table 324. 9S12I32PIMV1 FLL Multiply Register (CRGMULT)

This register provides 9S12I32PIMV1 status bits and flags. Table 325. CRGMULT Field Descriptions Characteristics for frequency range of fDCO. Table 326. 9S12I32PIMV1 Flags Register (CRGFLG)

1. PORF is set to 1 when a Power-On Reset occurs. Unaffected by System Reset.
2. ILAF is set to 1 when an illegal address access occurs. Unaffected by System Reset. Cleared by Power-On Reset.

Table 327. CRGFLG Field Descriptions 0 Power-on Reset has not occurred. 1 Power-on Reset has occurred.

1. Writing a 0 has no effect. If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. Entering Stop mode or writing

registers CRGCTL0, CRGMULT, CRGTRIMH, or CRGTRIML clears the LOCKST bit. 0 DCO Clock is not within the desir ed tolerance of the target frequency. 1 DCO Clock is within the desired tolerance of the target frequency. Illegal Address Reset Flag — ILAF is set to 1 when an illegal address access occurs. Refer to MMC Block Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Illegal address access has not occurred. 1 Illegal address access has occurred. Oscillator Startup Status Bit — UPOSC is set when startup of the oscillator has finished successfully. Monitor becomes active after initial oscillator startup, that is only for UPOSC=1. UPOSC is cleared with disabling the Oscillator, that is either OSCEN = 0 or entering Stop mode. Writes have no effect. 0 Oscillator has not started up. Os cillator Monitor is inactive. 1 Oscillator has started up. Os cillator Monitor is active.

Writing the CRGTRIMH or CRGTRIML register clears the LOCKST bit, but does not set the LOCKIF bit in the CRGFLG register. This register is reserved for factory test. This register is not writable. Table 328. 9S12I32PIMV1 TRIM Register High Byte (CRGTRIMH) Internal Reference Frequency fIREF_TRIM. Table 329. 9S12I32PIMV1 Trim Register Low Byte (CRGTRIML) Internal Reference Frequency fIREF_TRIM. Table 330. CRGTRIMH and CRGTRIML Field Descriptions Reference Frequency fIREF_TRIM. See Electrical Characteristics for value of fIREF_TRIM. will increase the frequency, increasing the value will decrease the frequency. Trimmed frequency must be in the allowed range for fFLLREF. See device electrical characteristics for details. Table 331. 9S12I32PIMV1 Test Register 0 (CRGTEST0)

This register is reserved for factory test. This register is not writable.

4.32.4 Write: Not Possible Functional Description

4.32.4.1 Startup from Reset

An example of startup of clock system from Reset is given in Figure 73. Figure 73. Example for Startup of Clock System After Reset Table 332. 9S12I32PIMV1 Test Register 1(CRGTEST1) During startup from Reset DCO Clock is the Core Clock and, divided by 2, the Bus Clock.

4.32.4.2 Stop Mode Using DCO Clock as a Bus Clock

An example of what happens going into stop mode and exiting stop mode after an interrupt is shown in Figure 74. Figure 74. Example of STOP Mode Using DCO Clock as Bus Clock

4.32.4.3 Stop Mode Using Oscillator Clock as Bus Clock

An example of what happens going into stop mode and exiting stop mode after an interrupt is shown in Figure 75. Figure 75. Example of STOP Mode Using Oscillator Clock as a Bus Clock

4.32.4.4 Enabling the External Oscillator

An example of how to use the Oscillator as Bus Clock is shown in Figure 76. Figure 76. Example for Enabling the External Oscillator

4.32.5 Resets

4.32.5.1 General

All reset sources are listed in Table 333. Refer to MCU specification for related vector addresses and priorities. Table 333. Reset Summary enable external Oscillator by writing OSCEN bit to one.

4.32.5.2 Description of Reset Operation

cycles after the low drive is released.

• Low level is detected at the RESET pin (External Reset).
• Power-on is detected.
• Illegal Address Access is detected (see MMC Block Guide for details).
• COP watchdog times out.
• Oscillator monitor failure is detected. Upon detection of any reset event, an internal circuit drives the RESET pin low for 516 DCO Clock cycles. Depending on internal synchronization latency, it can also be 517 DCO Clock cycles (see Figure 77). Since entry into reset is asynchronous, it does not require a running DCO Clock. However, the internal reset circuit of the 9S12I32PIMV1 cannot sequence out of current reset condition without a running DCO Clock. After 516 DCO Clock cycles, the RESET pin is released. The reset generator of the 9S12I32PIMV1 waits for additional 256 DCO Clock cycles and then samples the RESET pin to determine the originating source. Table 334 shows which vector will be fetched. The internal reset of the MCU remains asserted while the reset generator completes the 768 DCO Clock long reset sequence. In case the RESET pin is externally driven low for more than these 768 DCO Clock cycles (External Reset), the internal reset remains asserted longer.

Figure 77. RESET Timing

4.32.5.2.1 Oscillator Monitor Reset

for values), the 9S12I32PIMV1 generates a Oscillator Monitor Reset. Table 334. Reset Vector Selection

0 X X POR /Illegal Address Access/ External pin RESET

4.32.5.2.2 Computer Operating Properly Watchdog (COP) Reset

A COP timeout will generate a reset. See COP description for details.

4.32.5.2.3 Powe r-On Reset

The on-chip voltage POR circuitry detects when VDD to the MCU has reached a certain level and asserts a Power-on reset.

4.32.6 Interrupts

4.32.6.1 Description of Interrupt Operation

4.32.6.1.1 FLL Lock Interrupt

Table 335. 9S12I32PIMV1 Interrupt Vectors

4.33 External Oscill ator (S12SS12SCRGV1)

4.33.1 Introduction

The full swing Pierce oscillator (S12SCRG) module provides a robust clock source with an external crystal or ceramic resonator.

4.33.2 Features

• Full rail-to-rail (2.5 V nominal) swing oscillation with low EM susceptibility
• High noise immunity due to input hysteresis
• Low power consumption due to oper ation with 2.5 V (nominal) supply

4.33.3 Modes of Operation

1. Full swing Pierce oscillator (OSCEN=1)

4.33.4 Block Diagram

Figure 78 shows a block diagram of the S12SCRG module. Figure 78. S12SCRG Block Diagram

4.33.5 External Signals EXTAL and XTAL — Input and Output Pins

crystal, by the resonator or crystal supplier. The oscillator circuit is not suited for overtone resonators and crystals. EXTAL is the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. Figure 79. Full Swing Pierce Oscillator Connections Figure 80. External Connections, if S12SCRG is Unused The circuit shown in Figure 79 is recommended when using either a crystal or a ceramic resonator. output will be forced to VDD by the MCU.

• Rs can be zero (shorted) when use with higher frequency crystals.

Refer to manufacturer’s data.

4.34 Real Time Inte rrupt (S12SRTIV1)

4.34.1 Introduction

the interrupt will occur at the rate selected by the RTICTL and RTICNT register. new RTI timeout period starts immediately. The RTI contains two asynchronous clock domains (one for the Modulus Down Counter/Prescaler and one for the register bank). be done in appliance to the write protection rules.

4.34.2 Overview

Figure 81. Block Diagram

4.34.3 Features

• Generate hardware interrupt at a fixed periodic rate
• Software selectable RTI operation in WAIT and STOP mode
• Software selectable RTI freeze during BDM active mode

4.34.4 Modes of Operation

• R u n M o d e If RTI functionality is required, the individual bits (RTIRT) of the associated rate select registers (RTICTL) have to be set to a non-zero value. In addition, to generate RTI requests, the RTI must be enabled (RTIE bit set). The RTI counter is stopped if all rate select bits in the RTICTL register are zero. Interrupt requests will be disabled if the corresponding bit (RTIE) is cleared.
• Wait mode If the respective enable bit (RTISWAI) is cleared, the RTI will continue to run, else RTI will remain frozen.
• Stop mode If the respective enable bit (RTIRSTP) is set, the RTI will continue to run, else RTI will remain frozen.

4.34.5 External Signal Description

There are no external signals associated with this module.

4.34.6 Memory Map and Register

4.34.6.1 Module Memory Map

A summary of the registers associated with the RTI module is shown in Table 336.

4.34.6.2 Register Descriptions

4.34.6.2.1 RTI Contro l Register (RTICTL)

This register controls the RTI (Real Time Interrupt). Table 336. RTI Register Summary Table 337. RTI Control Register (RTICTL) Table 338. RTICTL Field Descriptions effect The flag cannot be set by writing a 1. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred.

0 RTI keeps running in BDM active mode

1 RTI frozen during BDM active mode

of RTIF, RTISWAI, RTIRSTP, RTIE and RTIRT[1:0] Bits.

0 Write of RTIF, RTISWAI, RTIRSTP, RTIE and RTIRT[1:0] Bits has an effect with this write of RTICTL

1 Write of RTIF, RTISWAI, RTIRSTP, RTIE and RTIRT[1:0] Bits has no effect with this write of RTICTL.

4.34.6.2.2 RTI Counter select bits (RTICNT)

This register is used to restart the RTI time-out period. Special modes: Write anytime. 0 RTI keeps running in Wait mode. 1 RTI stops and initializes the RTI counter whenever the part enters Wait mode. Special modes: Write anytime.

0 RTI stops in Stop mode

1 RTI continues in Stop mode

Wait mode with RTISWAI bit set. 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. Write anytime in appliance of the write protection rules (see 4.34.7.1, “RTI register write protection rules“). Table 339. RTICNT Register Diagram Table 340. RTI Frequency Divide Rates Table 338. RTICTL Field Descriptions (continued)

4.34.7 Functional Description

time interrupt flag (RTIF) is set to 1 when a time-out occurs, and is cleared to 0 by writing a 1 to the RTIF bit. the RTI interrupt is enabled. Wait if the RTI interrupt is enabled. If the RTIFRZ bit of the RTICTL register is set the RTI timer is frozen during BDM active mode. rate (RTICNT register)“ for RTI register access rules.

4.34.7.1 RTI register wr ite protection rules

synchronized results in ignored values. In general it should be avoided to access both registers in a single word access if only one of the registers should be modified.

4.34.7.2 Modification of Prescaler rate (RTIRT bits)

follow below recommendations.

1. Denotes the default value out of reset.This value disable the RTI.

Table 340. RTI Frequency Divide Rates (continued)

Functional Description and Application Information Real Time Interrupt (S12SRTIV1) MM912F634 Freescale Semiconductor 259 If the Frequency Divider Rate is set lower or equal to three the RTI interrupt service routine will access the RTICTL register with in a timing window which is less or equal the synchronization delay. Hence the interrupt service routine which access the RTICTL register to clear the RTIF bit is executed such frequently that the RTIRT bits are permanently locked. Therefore the following sequence is recommended if RTIRT bits should be changed for a current selected Frequency Divider Rate of two or three:

• - Access the RTICTL register to clear the RTI interrupt flag (R TIF bit) and disable the RTI interrupt (clear RTIE bit) by a single write access.
• - Execute a software loop in which the RTICTL register is written to modify the RTIRT bits until the new Frequency Divider Rate is taken (read back value of RTIRT bits equals new value)
• - Access RTICTL register to enable RTI interrupts again. If the actual Frequency Divider Rate of the RTI is set to a rate higher than three the write access to clear the interrupt flag (RTIF bit) in the RTICTL register can be used to modify the RTIRT bits of the RTICTL register.

4.34.7.3 Modification of Modulus Down Counter rate (RTICNT register)

Applications which frequently access the RTICNT register should follow below recommendations. If the RTICNT register is accessed with in a timing window which is less or equal the synchronization delay the following sequence is recommended:

• - Access the RTICTL register to clear the RTI interrupt flag (R TIF bit) and disable the RTI interrupt (clear RTIE bit) by a single write access.
• - Execute a software loop in which the RTICNT register is written to modify the rate until the new Frequency Divider Rate is taken (read back value of RTICNT bits equals new value)
• - Access RTICTL register to enable RTI interrupts again. If the RTICNT register is accessed in a timing window which is higher than the synchronization delay, only the RTICNT register needs to be written and wait until next time-out occurs.

4.35 Computer Operati ng Properly (S12SCOPV1)

4.35.1 Introduction

platform.The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. timeout period. Once this is done, the COP timeout period restarts. If the program fails to do this the S12SCRG will initiate a reset.

4.35.1.1 Overview

Figure 82. Block Diagram

4.35.1.2 Features

• Watchdog timer with a timeout clear window.
• Default maximum COP rate and no Window COP in Special Single Chip mode after system reset.
• Auto COP rate load after system reset in SoC Normal mode. (For source of COP rate bits please refer to the Device User Guide)
• Software selectable COP operation in WAIT and STOP mode.
• Customer selectable COP off while BDM active (debugging session). Modulus Down Counter ARMCOP-Register Int_Ref_Clock CR[2:0] Control Logic COP reset requestWCOP SSC_Mode (26,..., 216)

4.35.1.3 Modes of Operation

• R u n m o d e If COP functionality is required, the individual bits of the associated rate select registers (COPCTL) have to be set to a non-zero value. The COP is stopped if all rate select bits are zero.
• Wait mode If the respective enable bit (COPSWAI) is cleared, the COP will continue to run, else COP remains frozen.
• Stop mode If the respective enable bit (COPRSTP) is set, the COP will continue to run, else COP remains frozen.

4.35.2 External Signal Description

There are no external signals associated with this module.

4.35.3 Memory Map and Register

4.35.3.1 Module Memory Map

A summary of the registers associated with the COP module is shown in Table 336.

4.35.3.2 Register Descriptions

Table 341. COP Register Summary

4.35.3.2.1 COP Control Register (COPCTL)

This register controls the COP (Computer Operating Properly) watchdog.

1. RSBCK: anytime in special modes; write to “1” but not to “0” in all other modes

– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. – Writing WCOP to “0” has no effect, but counts for the “write once” condition.

1. Writing a non-zero value to CR[2:0] (anytime in sp ecial modes, once in all other modes) with WRTMASK = 0.
2. Changing RSBCK bit from “0” to “1”.

Table 342. COP Control Register (COPCTL) Table 343. COPCTL Field Descriptions window before writing to ARMCOP . Table 344 shows the duration of this window for the seven available COP rates.

0 Normal COP operation

1 Window COP operation

0 Allows the COP and RTI to keep running in Active BDM mode. 1 Stops the COP and RTI counters whenever the part is in Active BDM mode. WCOP, CR[2:0], COPSWAI, and COPRSTP .

0 Write of WCOP , CR[2:0], COPSWAI and COPRSTP has an effect with this write of COPCTL

1 Write of WCOP , CR[2:0], COPSWAI and COPRSTP has no effect with this write of COPCTL. 0 COP continues in Wait mode. 1 COP stops and initializes the COP counter whenever the part enters Wait mode.

0 COP stops in Stop mode

1 COP continues in Stop mode

in Wait mode with COPSWAI bit set. avoided by periodically (before timeout) re-initialize the COP counter via the ARMCOP register. Table 344. COP Watchdog Rates(180)

1. Refer to Device User Guide ( Section 4.35.4.1, “COP Configuration") for reset values of WCOP,

Table 343. COPCTL Field Descriptions (continued)

4.35.3.2.2 COP Timer Arm/ Reset Register (ARMCOP)

This register is used to restart the COP timeout period. When the COP is disabled (CR[2:0] = “000”), writing to this register has no effect. last 25% of the selected timeout period. Writing any value in the first 75% of the selected period will cause a COP reset. Only sequences of $55 are allowed if the WCOP bit is set.

4.35.4 Functional Description

internal reference clock. Three control bits in the COPCTL register allow a selection of seven COP timeout periods. $AA writes are allowed if the WCOP bit is not set. after the $55, the timeout logic restarts, and the user must wait until the next window before writing to the ARMCOP register. If the COPRSTP bit is set, the COP will continue to run in Stop mode. The COP continues to run during Wait mode if the COPSWAI bit is cleared. Table 345. ARMCOP Register Diagram

4.35.4.1 COP Configuration

is always set to the longest period (CR[2:0] = 111) after COP reset. the global address $03_FF0E during the reset sequence. Table 346. Initial COP Rate Configuration Table 347. Initial WCOP Configuration

Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) MM912F634 Freescale Semiconductor 266 4.36 32 kbyte Flash M odule (S12SFTSR32KV1)

4.36.1 Introduction

This document describes the S12SFTSR32K module, that includes a 32 kbyte Flash (nonvolatile) memory. CAUTION A Flash block address must be in the erased state before being programmed. Cumulative programming of bits within a Flash block address is not allowed, except for status field updates required in EEPROM emulation applications. The Flash memory is ideal for single-supply applications, allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. Array read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is not possible to read from a Flash block while any command is executing on that specific Flash block.

4.36.1.1 Glossary

Command Write Sequence — A three step MCU instruction sequenc e to execute built-in algorithms (including program and erase) on the Flash memory. Flash Array — The Flash array constitutes the main memory portion of a Flash block. Flash Block — An analog block consisting of the Flash array a nd Flash IFR with supporting high voltage and parametric test circuitry. Flash IFR — Nonvolatile information memory, consisting of 128 bytes, located in the Flash block outside of Flash main memory. Refer to the SoC Guide on how to make the Flash IFR visible in the global memory map.

4.36.1.2 Features

• 32 kbytes of Flash memory comprised of one 32 kbyte block divided into 64 sectors of 512 bytes
• Nonvolatile information memory (Flash IFR) comprised of one 128 byte block
• Automated program and erase algorithm
• Interrupt on Flash command completion, command buffer empty
• Fast program and sector erase operation
• Burst program command for faster Flash array program times
• Flexible protection scheme to prev ent accidental program or erase
• Single power supply for all Flash operations including program and erase
• Security feature to prevent unauthorized access to the Flash memory

4.36.1.3 Block Diagram

A block diagram of the Flash module is shown in Figure 83. Figure 83. S12SFTSR32K Block Diagram

4.36.2 External Signal Description

The Flash module has no external signals.

4.36.3 Memory Map and Register Definition

This section describes the Flash array map, Flash IFR map, and Flash register map shown in Figure 84.

4.36.3.1 Flash Array Map

The MCU memory map places the Flash array addresses between Flash array base + 0x0000 and 0x7FFF. Figure 84. Flash Memory Map

4.36.3.1.1 Flash Configuration Field Description

Flash security features. The Flash configuration field starts at Flash array base + 0x7F00, as shown in Table 348. Table 348. Flash Configuration Field

4.36.3.2 Flash IFR Map

memory map places the Flash IFR addresses between Flash IFR base + 0x0000 and 0x007F as shown in Table 349.

4.36.3.3 Register Descriptions

The Flash module contains a set of 16 control and status registers located between Flash register base + 0x0000 and 0x000F. descriptions of each register bit are provided in the following sections. Table 349. Flash IFR Description

1. Refer to the SoC Guide for details on how to enable the Flash IFR

Table 350. S12SFTSR32K Register Summary (Normal/Special Mode) Table 348. Flash Configuration Field (continued)

4.36.3.3.1 Flash Clock Divider Register (FCLKDIV)

to the FCLKDIV register (see Table 352). Table 351. Flash Clock Divider Register (FCLKDIV) Table 352. FCLKDIV Field Descriptions 0 Writing a 0 to FDIVLD locks the FCLKDIV register c ontents; all future writes to FCLKDIV are ignored. 1 Writing a 1 to FDIVLD keeps the FCLKDIV register writable; next write to FCLKDIV is allowed. 0 FCLKDIV register has not been written to since the last reset. 1 FCLKDIV register has been written to since the last reset. Table 350. S12SFTSR32K Register Summary (Normal/Special Mode) (continued)

4.36.3.3.2 Flash Security Register (FSEC)

The FSEC register holds all bits associated with the security of the MCU and Flash module. All bits in the FSEC register are readable but are not writable. 0 The bus clock is directly fed into the clock divider. 1 The bus clock is divided by 8 bef ore feeding into the clock divider. Table 353. Flash Security Register (FSEC) Table 354. FSEC Field Descriptions unsecured using backdoor key access, the SEC[1:0] bits are forced to the unsecured state. Table 355. Flash KEYEN States

00 DISABLED

10 ENABLED

11 DISABLED

1. Preferred KEYEN state to disable Backdoor Key Access.

Table 356. Flash Security States

00 SECURED

10 UNSECURED

1. Preferred SEC state to set MCU to secured state.

Table 352. FCLKDIV Field Descriptions (continued)

The security feature in the Flash module is described in Section 4.36.6, “Flash Module Security"”.

4.36.3.3.3 Flash Reserved0 Register (FRSV0)

The FRSV0 register is reserved for factory testing. All bits in the FRSV0 register read 0 and are not writable.

4.36.3.3.4 Flash Configur ation Register (FCNFG)

Flash array reads are allowed while KEYACC is set. The FCNFG register enables the Flash interrupts and gates the security backdoor writes. Table 357. Flash Reserved0 Register (FRSV0) Table 358. Flash Configuration Register (FCNFG) Table 359. FCNFG Field Descriptions 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”) is set. 0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”) is set. 0 Writes to the Flash block are interpreted as the start of a command write sequence. 1 Writes to the Flash block are interpreted as keys to open the backdoor.

4.36.3.3.5 Flash Protection Register (FPROT)

The FPROT register defines which Flash sectors are protected against program or erase operations. In Normal mode, FPROT bits are readable and writable as long as the size of the protected Flash memory is being increased. Any write to FPROT that attempts to decrease the size of the protected Flash memory will be ignored. In special mode, FPROT bits are readable and writable without restrictions. Flash configuration field must be unprotected, then the Flash protection byte must be reprogrammed. Table 360. Flash Protection Register (FPROT) Table 361. FPROT Field Descriptions Table 362. Flash Protection Higher Address Range

Table 363. Flash Protection Lower Address Range

111 No Lower Protection 0 kbytes

1. Flash memory fully protected.
2. Reserved for future use. If wri tten, these FPLS values will be

treated the same as FPLS = 000. Table 362. Flash Protection Higher Address Range (continued)

4.36.3.4 Flash Status Register (FSTAT)

The FSTAT register defines the operational status of the Flash module. remaining bits read 0 and are not writable. In special mode, BLANK and FAIL are readable and writable. FAIL must be clear when starting a command write sequence. Table 364. Flash Status Register (FSTAT - Normal Mode) Table 365. Flash Status Register (FSTAT - Special Mode) Table 366. FSTAT Field Descriptions bit in the FCNFG register to generate an interrupt request (see Figure 92). 1 Command buffers are ready to accept a new command. register to generate an interrupt request (see Figure 92). 1 All commands are completed. area of the Flash memory or Flash IFR during a command write sequence. Writing a 0 to the PVIOL flag has no effect on PVIOL. 0 No protection violation detected. 1 Protection violation has occurred. set, it is not possible to launch a command or start a command write sequence. 1 Access error has occurred.

4.36.3.4.1 Flash Command Register (FCMD)

The FCMD register is the Flash command register. All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. mode where the BLANK flag can be cleared by writing a 1 to BLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased. not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. 0 Flash operation completed without error. Table 367. Flash Command Register (FCMD) Table 368. FCMD Field Descriptions listed in Table 369 in normal mode sets the ACCERR flag in the FSTAT register. Table 369. Valid Flash Command List Table 366. FSTAT Field Descriptions (continued)

4.36.3.4.2 Flash Reserved1 Register (FRSV1)

The FRSV1 register is reserved for factory testing. All FRSV1 bits read 0 and are not writable.

4.36.3.4.3 Flash Address Registers (FADDR)

block is not byte addressable. The FADDR registers are the Flash address registers. Table 370. Flash Reserved1 Register (FRSV1) Table 371. Flash Address High Register (FADDRHI - Normal Mode) Table 372. Flash Address Low Register (FADDRLO - Normal Mode) Table 373. Flash Address High Register (FADDRHI - Special Mode) Table 374. Flash Address Low Register (FADDRLO - Special Mode)

All FADDR bits read 0 and are not writable in normal mode. All assigned FADDR bits are readable and writable in special mode.

4.36.3.4.4 Flash Data Registers (FDATA)

The FDATA registers are the Flash data registers. All FDATA bits read 0 and are not writable in normal mode. within the Flash block, as part of a command write sequence. Table 375. Flash Data High Register (FDATAHI - Normal Mode) Table 376. Flash Data Low Register (FDATALO - Normal Mode) Table 377. Flash Data High Register (FDATAHI - Special Mode) Table 378. Flash Data Low Register (FDATALO - Special Mode) Table 374. Flash Address Low Register (FADDRLO - Special Mode) (continued)

4.36.3.4.5 Flash Reserved2 Register (FRSV2)

The FRSV32 register is reserved for factory testing. All FRSV32 bits read 0 and are not writable.

4.36.3.4.6 Flash Reserved3 Register (FRSV3)

The FRSV3 register is reserved for factory testing. All FRSV3 bits read 0 and are not writable.

4.36.3.4.7 Flash Reserved4 Register (FRSV4)

The FRSV4 register is reserved for factory testing. All FRSV4 bits read 0 and are not writable. Table 379. Flash Reserved2 Register (FRSV2) Table 380. Flash Reserved3 Register (FRSV3) Table 381. Flash Reserved4 Register (FRSV4)

4.36.3.4.8 Flash Reserved5 Register (FRSV5)

The FRSV5 register is reserved for factory testing. All FRSV5 bits read 0 and are not writable.

4.36.4 Functional Description

4.36.4.1 Flash Command Operations

clock via a programmable divider.

1. How to write the FCLKDIV register to set FCLK
2. Command write sequences to program, erase, and erase verify operations on the Flash memory
3. Effects resulting from illegal Flash command write sequences or aborting Flash operations

4.36.4.1.1 Writing the FCLKDIV Register

to within the 150 to 200 kHz range.

• FCLK as the clock of the Flash timing control block
• INT(x) as taking the integer part of x (e.g. INT(4.323) = 4) then FCLKDIV bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 85. For example, if the bus clock frequency is 20 MHz, FCLKDIV bits FDIV[5:0] should be set to 0x0C (001100), and bit PRDIV8 set to 1. The resulting FCLK frequency is then 192 kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target by:

Table 382. Flash Reserved5 Register (FRSV5)

FCLK. Programming or erasing the Flash memory with FCLK < 150 kHz should be avoided. incomplete programming or erasure of the Flash memory cells. sequence will not execute and the ACCERR flag in the FSTAT register will set. Figure 85. Determination Procedure for PRDIV8 and FDIV Bits

4.36.4.1.2 Command Write Sequence

flag must be set (see Section 4.36.3.4).

1. Write to a valid address in the Flash array memory.
2. Write a valid command to the FCMD register.
3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command.

4.36.4.2 Flash Commands

updates required in EEPROM emulation applications. Table 383 summarizes the valid Flash commands along with the effects of the commands on the Flash block. Table 383. Flash Command Description the BLANK flag in the FSTAT register will set upon command completion. 0x20 Program Program an address in the Flash array. 0x40 Sector Erase Erase all memory bytes in a sector of the Flash array. no protection is enabled prior to launching the command. Set sense-amp margin levels for verifying Flash array contents (special mode only).

Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) MM912F634 Freescale Semiconductor 283

4.36.4.2.1 Erase Verify Command

The erase verify operation will verify that the entire Flash array memory is erased. An example flow to execute the erase verify operation is shown in Figure 86. The erase verify command write sequence is as follows: 1. Write to an aligned Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writ ing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in the Flash array memory plus several bus cycles, as measured from the time the CBEIF flag is cleared, until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the Flash array memory are verified to be erased. If any address in the Flash array memory is not erased, the erase verify operation will terminate, the BLANK flag in the FSTAT register will remain clear, and the FAIL flag in the FSTAT register will set in special mode.

Figure 86. Example Erase Verify Command Flow

4.36.4.2.2 Program Command

The program operation will program a previously erased address in the Flash memory using an embedded algorithm.

1. Write to an aligned Flash block address to start the command write sequence for the program command. The data

written will be programmed to the address written.

1. Write the program command, 0x20, to the FCMD register.
2. Clear the CBEIF flag in the FSTAT register by wr iting a 1 to CBEIF to launch the program command.

will set after the program operation has completed. Figure 87. Example Program Command Flow

4.36.4.2.3 Burst Program Command

The burst program operation will program previously erased data in the Flash memory using an embedded algorithm. on a specific row in the Flash array as the high voltage generation can be kept active in between two programming commands.

1. Write to an aligned Flash block address to start the comma nd write sequence for the burst program command. The data

written will be programmed to the address written.

Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) MM912F634 Freescale Semiconductor 286 2. Write the program burst command, 0x25, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writ ing a 1 to CBEIF to launch the program burst command. 4. After the CBEIF flag in the FSTAT register returns to a 1 (interrupt generated, if enabled), repeat steps 1 through 3. The address written is ignored but is incremented internally. The burst program procedure can be used to program the entire Flash memory, even while crossing row boundaries within the Flash array. If data to be burst programmed falls within a protected area of the Flash array, the PVIOL flag in the FSTAT register will set and the burst program command will not launch. Once the burst program command has successfully launched, the CCIF flag in the FSTAT register will set after the burst program operation has completed, unless a new burst program command write sequence has been buffered. By executing a new burst program command write sequence on sequential addresses after the CBEIF flag in the FSTAT register has been set, greater than 50% faster programming time for the entire Flash array can be effectively achieved, when compared to using the basic program command.

Figure 88. Example Burst Program Command Flow

Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) MM912F634 Freescale Semiconductor 288

4.36.4.2.4 Sector Erase Command

In case the PVIOL or ACCERR flags are asserted by some event occurring in between the erase pulses, the customer application must clear the flags in FSTAT register before resuming the sequence of 16 pulses. The sector erase operation will erase all addresses in a 512 byte sector of Flash memory using an embedded algorithm. The overall erase time has been divided into 16 erase pulses to allow faster system response. The customer application has to guarantee all 16 pulses are performed before writing into the Flash sector being erased. There is no requirement to have those pulses as consecutive operations. An example flow to execute the sector erase operation is shown in Figure 89. The sector erase command write sequence is as follows: 1. Write to an aligned Flash block address to start the comm and write sequence for the sector erase command. The Flash address written determines the sector to be erased while the data written is ignored. 2. Write the sector erase command , 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writ ing a 1 to CBEIF to launch the sector erase command. 4. Wait for the CCIF flag in the FSTAT register to se t signifying completion of the sector erase operation. 5. Repeat steps 1 through 4 until all 16 sector erase puls es have been executed. Address must be in the same Flash sector. If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed.

Figure 89. Example Sector Erase Command Flow

16 Erase

4.36.4.2.5 Mass Erase Command

The mass erase operation will erase the entire Flash array memory using an embedded algorithm.

1. Write to an aligned Flash block address to start the command write sequence for the mass erase command. The

address and data written will be ignored.

1. Write the mass erase command, 0x41, to the FCMD register.
2. Clear the CBEIF flag in the FSTAT register by wr iting a 1 to CBEIF to launch the mass erase command.

register will set after the mass erase operation has completed. Figure 90. Example Mass Erase Command Flow

4.36.4.2.6 Set Verify Margin Level Command

should only be used to validate initial programming of the Flash array.

1. Write to an aligned Flash block address to start the command write sequence for the set verify margin level command.

The address will be ignored while the data written sets the margin level as shown in Table 384.

1. Write the set verify margin level command, 0x75, to the FCMD register.
2. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the set verify margin level command.

verify margin level operation has completed. Table 384. Flash Array Margin Level Settings

Figure 91. Example Set Verify Margin Level Command Flow (Special Mode only)

4.36.4.3 Illegal Flash Operations

4.36.4.3.1 Flash Access Violations

1. Writing to a Flash address before initializing the FCLKDIV register.
2. Writing a byte or misaligned word to a valid Flash address. Writing to any Flash register other than FCMD after writing
3. Writing to a second Flash address in the same command write sequence.
4. Writing an invalid command to the FCMD register, unless the address written was in a protected area of the Flash array.
5. Writing a command other than burst program, while CBEIF is set and CCIF is clear.
6. When security is enabled, writing a command other than eras e verify or mass erase to the FCMD register, when the

write originates from a non-secure memory location or from the background debug mode.

1. Writing to a Flash address after writing to the FCMD register.
2. Writing to any Flash register other than FSTAT (t o clear CBEIF) after writing to the FCMD register.

Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) MM912F634 Freescale Semiconductor 293 9. Writing a 0 to the CBEIF flag in the FSTA T register to abort a command write sequence. The ACCERR flag will also be set if the MCU enters stop mode while any command is active (CCIF=0). The operation is aborted immediately and, if burst programming, any pending burst program command is purged (see Section 4.36.5.2, “Stop Mode"”). The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”).

4.36.4.3.2 Flash Protection Violations

The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence, if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if the address written in t he command write sequence was in a protected area of the Flash array. 2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the Flash array. 3. Writing the mass erase command while any Flash protection is enabled. 4. Writing an invalid command if the address written in the co mmand write sequence was in a protected area of the Flash array. If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 4.36.3.4, “Flash Status Register (FSTAT)"”).

4.36.5 Operating Modes

4.36.5.1 Wait Mode

If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 4.36.8, “Interrupts"”).

4.36.5.2 Stop Mode

As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations. If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash array will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting

Functional Description and Application Information 32 kbyte Flash Module (S12SFTSR32KV1) MM912F634 Freescale Semiconductor 294

4.36.5.3 Background Debug Mode

In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 383 can be executed. If the MCU is secured and is in special mode, only the erase verify and mass erase commands can be executed.

4.36.6 Flash Module Security

The Flash module provides the necessary security information to the MCU. During each reset sequence, the Flash module The contents of the Flash security byte in the Flash configuration field (see Section 4.36.3.1.1) must be changed directly by programming the Flash security byte location, when the MCU is unsecured and the sector containing the Flash security byte is unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize into a secure operating mode.

4.36.6.1 Unsecuring the MCU Using Backdoor Key Access

The MCU may be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the bit is set, a write to a backdoor key address in the Flash memory triggers a comparison between the written data and the backdoor key data stored in the Flash memory. If all backdoor keys are written to the correct addresses in the correct order, and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially. Values 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return valid data. The user code stored in the Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 4.36.3.3.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the Flash configuration register (FCNFG). 2. Sequentially write the correct four words to the Flash addresses containing the backdoor keys. 3. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEYACC bit. 4. If all data written match the backdoor keys, the MCU is unse cured and the SEC[1:0] bits in the FSEC register are forced to an unsecured state. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. If any of the keys written does not match th e backdoor keys programmed in the Flash array. 2. If the keys are written in the wrong sequence. 3. If any of the keys written are all 0’s or all 1’s. 4. If the KEYACC bit does not remain set while the keys are written. 5. If any of the keys are written on successive MCU clock cycles. 6. Executing a STOP instruction before all keys have been written. After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming the associated addresses

and erase protections defined in the Flash protection register (FPROT).

4.36.6.2 Unsecuring the MCU in Special Mode Using BDM

1. Reset the MCU into special mode, delay while the erase test is performed by the BDM secure ROM.
2. Send BDM commands to disable protection in the Flash module.
3. Execute a mass erase command write sequence to erase the Flash memory.

register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured.

1. Send BDM commands to execute a program sequence to pr ogram the Flash security byte to the unsecured state.

4.36.7 Resets

4.36.7.1 Flash Reset Sequence

• MCU control parameters (see Section 4.36.3.2)
• Flash nonvolatile byte (see Section 4.36.3.1.1)

4.36.7.2 Reset While Flash Command Active

address being programmed or the sector/block being erased is not guaranteed.

4.36.8 Interrupts

Vector addresses and their relative interrupt priority are determined at the MCU level. and command buffers are empty. Table 385. Flash Interrupt Sources

4.36.8.1 Description of Flash Interrupt Operation

The logic used for generating interrupts is shown in Figure 92. Figure 92. Flash Command Interrupt Implementation Section 4.36.3.4, “Flash Status Register (FSTAT)"”.

4.37 Die-to-Die Initiator (D2DIV1)

4.37.1 Introduction

between a microcontroller die (Interface Initiator) and an analog die (Interface Target) located in the same package.

• realizes the initiator part of the D2D interface, including supervision and error interrupt generation
• generates the clock for this interface
• disables/enables the interrupt from the D2D interface

4.37.1.1 Overview

Figure 93. Die-to-Die Initiator (D2DI) Block Diagram

4.37.1.2 Features

• Software transparent, memory mapped access to peripherals on target die — 256 Byte address window — Supports blocking read or write as we ll as non-blocking write transactions
• Scalable interface clock divide by 1, 2, 3 of bus clock D2DCLK D2DDAT[7:0] n=1 … 8Bus Clock D2DINT D2DCW Address and Data Buffer D2DIE Address Bus Write Data Bus Read Data Bus D2DINTI D2DERR_INT xfr_wait D2DIF D2DCLKDIV

Functional Description and Application Information Die-to-Die Initiator (D2DIV1) MM912F634 Freescale Semiconductor 298

• Clock halt on system STOP
• Configurable for 4- or 8-bit wide transfers
• Configurable timeout period
• Non-maskable interrupt on transaction errors
• Transaction Status and Error Flags
• Interrupt enable for receiving interrupt (from D2D target)

4.37.1.3 Modes of Operation

4.37.1.3.1 D2DI in STOP/WAIT Mode

The D2DI stops working in STOP/WAIT mode. The D2DCLK signal as well as the data signals used are driven low (only after the end of the current high phase, as defined by D2DCLKDIV). Waking from STOP/WAIT mode, the D2DCLK line starts clocking again and the data lines will be driven low until the first transaction starts. STOP and WAIT mode are entered by different CPU instructions. In the WAIT mode, the behavior of the D2DI can be configured (D2DSWAI). Every (enabled) interrupt can be used to leave the STOP and WAIT mode.

4.37.1.3.2 D2DI in special modes

The MCU can enter a special mode (used for test and debugging purposes as well as programming the FLASH). In the D2DI the “write-once” feature is disabled. See the MCU description for details.

4.37.2 External Signal Description

The D2DI optionally uses 6 or 10 port pins. The functions of those pins depends on the settings in the D2DCTL0 register, when the D2DI module is enabled.

4.37.2.1 D2DCLK

The maximum allowed D2D target frequency (fD2D) might be lower than the maximum initiator frequency. When the D2DI is enabled this pin is the clock output. This signal is low if the initiator is disabled, in STOP mode or in WAIT mode (with D2DSWAI asserted), otherwise it is a continuos clock. This pin may be shared with general purpose functionality if the D2DI is disabled.

4.37.2.2 D2DDAT[7:4]

When the D2DI is enabled and the interface connection width D2DCW is set to be 8-bit wide, those lines carry the data bits 7:4 acting as outputs or inputs. When they act as inputs pull-down elements are enabled. If the D2DI is disabled or if the interface connection width is set as 4-bit wide, the pins may be shared with general purpose pin functionality.

4.37.2.3 D2DDAT[3:0]

When the D2DI is enabled those lines carry the data bits 3:0 acting as outputs or inputs. When they act as inputs pull-down elements are enabled. If the D2DI is disabled the pins and may be shared with general purpose pin functionality.

4.37.2.4 D2DINT

The D2DINT is an active input interrupt input driven by the target device. The pin has an active pull-down device. If the D2DI is disabled, the pin may be shared with general purpose pin functionality.

See the port interface module (PIM) guide for details of the GPIO function.

4.37.3 Memory Map and Register Definition

4.37.3.1 Memory Map

The D2DI memory map is split into three sections.

1. An eight byte set of control registers.
2. A 256 byte window for blocking transactions.
3. A 256 byte window for non-blocking transactions.

See the chapter “Device Memory Map” for the register layout (distribution of these sections). Figure 94. D2DI Top Level Memory Map Table 386. Signal Properties

1. Active if in input state, only if D2DEN=1

8 Byte Control

256 Byte Window

are given in the subsections that follow.

4.37.3.2 Register Definition

4.37.3.2.1 D2DI Control Register 0 (D2DCTL0)

This register is used to enable and configure the interface width, the wait behavior and the frequency of the interface clock. Table 387. D2DI Register Summary Table 388. D2DI Control Register 0 (D2DCTL0) Table 389. D2DCTL0 Register Field Descriptions D2DI Enable — Enables the D2DI module. This bi t is write-once in normal mode and can always be written in special modes. 0 D2DI initiator is disabled. No lines are not us ed, the pins have their GPIO (secondary) function. command; the D2DCLK is driven by the divided bus clock. always be written in special modes. 0 Lines D2DDAT[3:0] are used for four line data transfer. D2DDAT[7:4] are unused. 1 All eight interface lines D2DDAT[7:0] are used for data transfer.

is shorter than 50% or equal but never longer, since this is beneficial for the transaction speed. Figure 95. Interface Clock Waveforms for Various D2DCLKDIV Encoding

4.37.3.2.2 D2DI Control Register 1 (D2DCTL1)

This register is used to enable the D2DI interrupt and set number of D2DCLK cycles before a timeout error is asserted. D2D Stop In Wait — Controls the WAIT behavior. This bit can be written at any time.

0 Interface clock continues to run if the CPU enters WAIT mode

1 Interface clock stops if the CPU enters WAIT mode. 4:2 Reserved, should be written to 0 to ensure compat ibility with future versions of this interface. 00 Encoding 0. Bus clock divide by 1. 01 Encoding 1. Bus clock divide by 2. 10 Encoding 2. Bus clock divide by 3. 11 Encoding 3. Bus clock divide by 4. Table 390. D2DI Control Register 1 (D2DCTL1) Table 391. D2DCTL1 Register Field Descriptions

0 External Interrupt is disabled

1 External Interrupt is enabled

6:4 Reserved, should be written to 0 to ensure compat ibility with future versions of this interface. Table 389. D2DCTL0 Register Field Descriptions (continued)

4.37.3.2.3 D2DI Status Register 0 (D2DSTAT0)

This register reflects the status of the D2DI transactions.

4.37.3.2.4 D2DI Status Register 1 (D2DSTAT1)

This register holds the status of the external interrupt pin and an indicator about the D2DI transaction status. case of a timeout the TIMEF flag in the D2DSTAT0 register will be set. These bits are write once in normal modes and can always be written in special modes. 0000 The acknowledge is expected directly after the last tr ansfer, i.e. the target must not insert a wait cycle. Table 392. D2DI Status Register 0 (D2DSTAT0) Table 393. D2DI Status Register 0 Field Descriptions following five flags).This interrupt is not locally maskable. Write a 1 to clear the flag. Writing a 0 has no effect. 0 D2DI has not detected an error during a transaction. 1 D2DI has detected an error during a transaction. indicating a potential broken wire. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. pending error flag (ERRIF). This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. bit is cleared by writing a 1 to the ERRIF bit. the transaction. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. Parity Error Flag — This read-only flag indicates the initiator has detected a parity error. Parity bits[1:0] contain further information. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit. Table 394. D2DI Status Register 1 (D2DSTAT1) Table 391. D2DCTL1 Register Field Descriptions (continued)

4.37.3.2.5 D2DI Address Buffer Register (D2DADR)

when a new transaction starts. In error cases the user can track back, which transaction failed. Table 395. D2DSTAT1 Register Field Descriptions target specific interrupt acknowledge sequence.

0 External Interrupt is negated

1 External Interrupt is asserted

D2D Initiator Busy — This read-only status bit indi cates that a D2D transaction is ongoing. 1 D2D initiator transaction ongoing. 5:0 Reserved, should be masked to ensure compatibili ty with future versions of this interface. Table 396. D2DI Address Buffer Register (D2DADR) Table 397. D2DI Address Buffer Register Bit Descriptions

0 Write Transaction

1 Read Transaction

13 Reserved, should be masked to ensure compatibility with future versions of this interface. 11:8 Reserved, should be masked to ensure compatibili ty with future versions of this interface. Table 394. D2DI Status Register 1 (D2DSTAT1) (continued)

4.37.3.2.6 D2DI Data Buff er Register (D2DDATA)

finalized when the transaction is acknowledged by the target. In error cases, the user can track back what has happened. Both D2DDATA and D2DADR can be read with byte accesses.

4.37.4 Functional Description

4.37.4.1 Init ialization

4.37.4.2 Transactions

read or write instructions determines if 8-bit or 16-bit wide data are transferred. There is always only one transaction active. Figure 96 shows the various types of transactions explained in more detail below. cause the “CPU halted” phases (see Figure 96). Table 398. D2DI Data Buffer Register (D2DDATA) Table 399. D2DI Data Buffer Register Bit Descriptions

Figure 96. Blocking and Non-blocking Transfers.

4.37.4.2.1 Blocking Writes

at the target is completed before proceeding with the CPU instruction stream.

4.37.4.2.2 Non-blocking Writes

are not affected by the change in the target caused by the previous transaction.

Functional Description and Application Information Die-to-Die Initiator (D2DIV1) MM912F634 Freescale Semiconductor 306

4.37.4.2.3 Blocking Read

When reading from the address window associated with blocking transactions, the CPU is held until the data is returned from the target, before completing the instruction.Figure 96 shows the behavior of the CPU for a blocking read transaction shown in the following example. LDAA BLK_WINDOW+OFFS0 ; Read 8-bit as a blocking transaction STAA MEM ; Store result to local Memory LDAA BLK_WINDOW+OFFS1 ; Read 8-bit as a blocking transaction

4.37.4.2.4 Non-blocking Read

Read access to the non-blocking window is reserved for future use. When reading from the address window associated with non-blocking writes, the read returns an all 0s data byte or word. This behavior can change in future revisions.

4.37.4.3 Transfer Width

8-bit wide writes or reads are translated into 8-bit wide interface transactions. 16-bit wide, aligned writes or reads are translated into 16-bit wide interface transactions. 16-bit wide, misaligned writes or reads are split up into two consecutive 8-bit transactions, with the transaction on the odd address first followed by the transaction on the next higher even address. Due to the much more complex error handling (by the MCU), misaligned 16-bit transfers should be avoided.

4.37.4.4 Error Conditions and Handling faults

Since the S12 CPU (as well as the S08) do not provide a method to abort a transfer once started, the D2DI asserts an D2DERRINT. The ERRIF Flag is set in the D2DSTAT0 register. Depending on the error condition, further error flags will be set as described below. The content of the address and data buffers are frozen, and all transactions will be replaced by an IDLE command, until the error flag is cleared. If an error is detected during the read transaction of a read-modify-write instruction, or a non-blocking write transaction was followed by another write or read transaction, the second transaction is cancelled. The CNCLF is set in the D2DSTAT0 register to indicate that a transaction has been cancelled. The D2DERRINT handler can read the address and data buffer register to assess the error situation. Any further transaction will be replaced by IDLE until the ERRIF is cleared.

4.37.4.4.1 Missing Acknowledge

If the target detects a wrong command, it will not send back an acknowledge. The same situation occurs if the acknowledge is corrupted. The D2DI detects this missing acknowledge after the timeout period configured in the TIMOUT parameter of the D2DCTL1 register. In case of a timeout, the ERRIF and the TIMEF flags in the D2DSTAT0 register will be set.

4.37.4.4.2 Pa rity error

In the final acknowledge cycle of a transaction, the target sends two parity bits. If this parity does not match the parity calculated by the initiator, the ERRIF and the PARF flags in the D2DSTAT0 register will be set. The PAR[1:0] bits contain the parity value received by the D2DI.

4.37.4.4.3 Error Signal

During the acknowledge cycle the target can signal a target specific error condition. If the D2DI finds the error signal asserted during a transaction, the ERRIF and the TERRF flags in the D2DSTAT0 register will be set.

4.37.4.5 Low Power Mode Options

4.37.4.5.1 D2DI in Run Mode

4.37.4.5.2 D2DI in Wait Mode

D2DI operation in wait mode depends upon the state of the D2DSWAI bit in D2D control register 0.

• If D2DSWAI is clear, the D2DI operates no rmally when the CPU is in the wait mode
• If D2DSWAI is set and the CPU enters the wait mode, any pending transmission is completed. When the D2DCLK output is driven low, the clock generation is stopped, all internal clocks to the D2DI module are stopped, and the module enters a power saving state.

4.37.4.5.3 D2DI in Stop Mode

If the CPU enters the STOP mode, the D2DI shows the same behavior as with the wait mode with an activated D2DSWAI bit.

4.37.4.6 Reset

In case of reset, any transaction is immediately stopped and the D2DI module is disabled.

4.37.4.7 Interrupts

requests from the D2D module. The interrupt vector offset and interrupt priority are chip dependent.

4.37.4.7.1 D2D Ex ternal Interrupt

pin can be observed by reading the D2DIF bit in the D2DSTAT1 register. The D2DINIT signal is asserted also in the wait and stop mode; it can be used to leave these modes. Figure 97. D2D External Interrupt Scheme

4.37.4.7.2 D2D Error Interrupt

architecture to the XIRQ. See the chapter “Vectors” of the MCU description for details.

Figure 98. D2D Internal Interrupts

4.37.5 Initializat ion Information

before starting any transaction. See the D2D Target specification for details.

4.37.6 Application Information

4.37.6.1 Entering low power mode

1. CPU determines there is no more work pending.
2. CPU writes a byte to a register on the analog die using blocking write configuring which mode to enter.
3. Analog die acknowledges that write sending back an acknowledge symbol on the interface.
4. CPU executes WAIT or STOP command.
5. Analog die can enter low-power mode - (S12 needs some more cycles to stack data!)
6. Analog die detects a wake-up condition e.g. on a switch input or start bit of a LIN message.
7. Analog die exits Voltage Regulator low-power mode.
8. Analog die asserts the interrupt signal D2DINT.
9. CPU starts clock generation.
10. CPU enters interrupt handler routine.
11. CPU services interrupt and acknowle dges the source on the analog die.

high duty cycle portion and settle at low level.

Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) MM912F634 Freescale Semiconductor 309

4.38 Serial Peripheral Interface (S12SPIV4)

4.38.1 Introduction

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.

4.38.1.1 Glossary of Terms

SPI — Serial Peripheral Interface SS — Slave Select SCK — Serial Clock MOSI — Master Output, Slave Input MISO — Master Input, Slave Output MOMI — Master Output, Master Input SISO — Slave Input, Slave Output

4.38.1.2 Features

The S12SPIV4 includes these distinctive features:

• Master mode and slave mode
• Bi-directional mode
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mode

4.38.1.3 Modes of Operation

The SPI functions in three modes: run, wait, and stop.

• R u n m o d e This is the basic mode of operation.
• Wait mode SPI operation in wait mode is a configurable low-power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master.
• Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. This is a high level description only, detailed descriptions of operating modes are contained in Section 4.38.4.7, “Low Power Mode Options"”.

4.38.1.4 Block Diagram

baud rate generator, master/slave control logic, and port control logic. Figure 99. SPI Block Diagram

4.38.2 External Signal Description

S12SPIV4 module has a total of four external pins.

4.38.2.1 MOSI — Master Out/Slave In Pin

4.38.2.2 MISO — Master In/Slave Out Pin

4.38.2.3 SS — Slave Select Pin

when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave.

4.38.2.4 SCK — Serial Clock Pin

In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.

4.38.3 Memory Map and Register Definition

This section provides a detailed description of address space and registers used by the SPI.

4.38.3.1 Module Memory Map

The memory map for the S12SPIV4 is given in Table 400.

4.38.3.2 Register Descriptions

associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Table 400. SPI Register Summary

4.38.3.2.1 SPI Control Register 1 (SPICR1)

Table 401. SPI Control Register 1 (SPICR1) Table 402. SPICR1 Field Descriptions SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if the SPIF or MODF status flag is set. cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if the SPTEF flag is set. from master to slave or vice versa forces the SPI system into idle state. force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock. 0 Data is transferred most significant bit first. 1 Data is transferred leas t significant bit first.

4.38.3.2.2 SPI Control Register 2 (SPICR2)

Table 403. SS Input / Output Selection

00 S S not used by the SPI SS input

01 S S not used by the SPI SS input

10 S S input with MODF feature SS input

11 S S is slave select output SS input

Table 404. SPI Control Register 2 (SPICR2) Table 405. SPICR2 Field Descriptions mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0S S port pin is not used by the SPI. 1S S port pin with MODF feature. transmission in progress and force the SPI into idle state. SPI Stop in Wait Mode Bit — This bit is used for power c onservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. of this bit will abort a transmission in progress and force the SPI system into idle state.

4.38.3.2.3 SPI Baud Rate Register (SPIBR)

For maximum allowed baud rates, refer to Section 3.6.2.4, “SPI Timing" in this data sheet. Table 406. Bidirectional Pin Configurations

1 Master I/O

1 Slave I/O

Table 407. SPI Baud Rate Register (SPIBR) Table 408. SPIBR Field Descriptions of these bits will abort a transmission in progress and force the SPI system into idle state. these bits will abort a transmission in progress and force the SPI system into idle state. Table 409. Example SPI Baud Rate Selection (20 MHz Bus Clock)

Table 409. Example SPI Baud Rate Selection (20 MHz Bus Clock) (continued)

4.38.3.2.4 SPI Status Register (SPISR)

Table 410. SPI Status Register (SPISR)

4.38.3.2.5 SPI Data Register (SPIDR)

SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. the receive shift register until the start of another transmission. The byte in the SPIDR does not change. the byte in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 100). the byte in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 101). Table 411. SPISR Field Descriptions cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 0 Transfer not yet complete. SPI data register without reading SPTEF = 1, is effectively ignored. 0 SPI data register not empty. write to the SPI control register 1. 0 Mode fault has not occurred. Table 412. SPI Data Register (SPIDR)

Figure 100. Reception with SPIF Serviced in Time Figure 101. Reception with SPIF Serviced Too Late

4.38.4 Functional Description

poll the SPI status flags or SPI operation can be interrupt driven.

• Slave select (SS )
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO) The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This 8-bit data register acts as the SPI Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received Data B = Unspecified = Reception in progress Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received Data B Lost = Unspecified = Reception in progress

Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) MM912F634 Freescale Semiconductor 319 receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 4.38.4.3, “Transmission Formats"”). NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.

4.38.4.1 Master Mode

A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock.

• Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral.
• MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits.
• S S pin If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low, this indicates a mode fault error, where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). The result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 4.38.4.3, “Transmission Formats"”).

Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) MM912F634 Freescale Semiconductor 320

4.38.4.2 Slave Mode

When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.

• Serial clock In slave mode, SCK is the SPI clock input from the master.
• MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.
• S S pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. NOTE A change of the CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE bits with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set.

4.38.4.3 Transmission Formats

master SPI device, the slave select line can be used to indicate multiple-master bus contention. Figure 102. Master/Slave Transfer Block Diagram

4.38.4.3.1 Clock Phase and Polarity Controls

Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats.

4.38.4.3.2 CPHA = 0 Transfer Format

selected. In this format, the first SCK edge is issued a half cycle after SS has become low. from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. edges and shifted on even numbered edges. parallel SPI data register after the last bit is shifted in.

• Data that was previously in the master SPI data register should now be in the slave data register, and the data that was in the slave data register should be in the master.
• The SPIF flag in the SPI status register is set, indicating that the transfer is complete. SHIFT REGISTER SHIFT REGISTER BAUD RATE GENERATOR MASTER SPI SLAVE SPI MOSI MOSI MISO MISO SCK SCK SS SSVDD

Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) MM912F634 Freescale Semiconductor 323

4.38.4.3.3 CPHA = 1 Transfer Format

Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th SCK edge:

• Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master.
• The SPIF flag bit in SPISR is set indi cating that the transfer is complete. Figure 104 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.

Figure 104. SPI Clock Format 1 (CPHA = 1) in systems having a single fixed master and a single slave that drive the MISO data line.

• Back-to-back transf ers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI data register, this byte is sent out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge.

4.38.4.4 SPI Baud Rate Generation

For maximum allowed baud rates, refer to Section 3.6.2.4, “SPI Timing" in this data sheet. SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 4. the module clock divisor becomes 8, etc.

Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) MM912F634 Freescale Semiconductor 325 When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 409 for baud rate calculations for all bit conditions, based on a 20 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current.

4.38.4.5 Special Features

4.38.4.5.1 SS Output

Care must be taken when using the SS output feature in a multi master system because the mode fault feature is not available for detecting system errors between masters. The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 403. The mode fault feature is disabled while SS output is enabled.

4.38.4.5.2 Bidirectional Mode (MOMI or SISO)

In bidirectional master mode, with mode fault enabled, both MISO and MOSI data pins can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode, and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case, MISO becomes occupied by the SPI and MOSI is not used. This must be considered if the MISO pin is used for another purpose. The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 413). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.

register is driven out on the pin. The same pin is also the serial input to the shift register.

• The SCK is output for the master mode and input for the slave mode.
• T h e S S is the input or output for the master mode, and it is always the input for the slave mode.
• The bidirectional mode does not affect SCK and SS functions.

4.38.4.6 Error Conditions

• Mode fault error

4.38.4.6.1 Mode Fault Error

this data byte will be lost. the SPI status register is set automatically, provided the MODFEN bit is set. is a dedicated input pin. Mode fault error doesn’t occur in slave mode. SCK, MISO, and MOSI pins are forced to be high-impedance inputs, to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. Table 413. Normal Mode and Bidirectional Mode

Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) MM912F634 Freescale Semiconductor 327

4.38.4.7 Low Power Mode Options

4.38.4.7.1 SPI in Run Mode

In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled.

4.38.4.7.2 SPI in Wait Mode

Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a transmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur. SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.

• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode.
• If SPISWAI is set and the SPI is configured for master, an y transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode.
• If SPISWAI is set and the SPI is config ured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK.
• If the master transmits severa l bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else, if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte).

4.38.4.7.3 SPI in Stop Mode

Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit.

Functional Description and Application Information Serial Peripheral Interface (S12SPIV4) MM912F634 Freescale Semiconductor 328

4.38.4.7.4 Reset

The reset values of registers and signals are described in Section 4.28.2, “Memory Map and Registers", which details the registers and their bit fields.

• If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset.
• Reading from the SPIDR after reset will always read a byte of zeros.

4.38.4.7.5 Interrupts

The S12SPIV4 only originates interrupt requests when the SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the S12SPIV4 makes a request, and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request. MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 403). After MODF is set, the current transfer is aborted and the following bit is changed:

• MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will Status Register (SPISR)". SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced.

Packaging Package Dimensions MM912F634 Freescale Semiconductor 329

5 Packaging

5.1 Package Dimensions

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. AE SUFFIX 48-PIN 98ASA00173D REVISION 0

Packaging Package Dimensions MM912F634 Freescale Semiconductor 330 AE SUFFIX 48-PIN 98ASA00173D REVISION 0

Packaging Package Dimensions MM912F634 Freescale Semiconductor 331 AE SUFFIX 48-PIN 98ASA00173D REVISION 0

Packaging Package Dimensions MM912F634 Freescale Semiconductor 332 AP SUFFIX 48-PIN 98ASH00962A REVISION G

Packaging Package Dimensions MM912F634 Freescale Semiconductor 333 AP SUFFIX 48-PIN 98ASH00962A REVISION G

Revision History Package Dimensions MM912F634 Freescale Semiconductor 334

6 Revision History

1.0 05/2010 • Initial release. 2.0 7/2010 • MM912F634Cxxxx (Revision C) Introduced

• MM912F634Cxxxx (Revision C) Lx Input Thres hold / Hysteresis Limit added. See Table 23, Static Electrical Characteristics - High Voltage Inputs - Lx
• V DDXSTOP minimum value deleted. See Table 17, Static Electrical Characteristics - Voltage Regulator 5.0 V (VDDX)
• I VDDLIMXSTOP ratings changed. See Table 17, Static Electrical Characteristics - Voltage Regulator 5.0 V (VDDX)
• I VDDLIMRUN minimum value deleted for all values of TJ. See Table 18, Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD)
• I VDDLIMSTOP minimum value deleted. See Table 18, Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD)
• TSg typical value changed to 9.17 mV/k. See Tabl e 27, Static Electrical Characteristics - Temperature Sensor - TSENSE
• Deleted devices MM912F634BC1AE, MM912F634BV2AE, MM912F634BC2AE, MM912F634BV3AE, MM912F634BC3AE, MM912F634CC1AE, MM912F634CC2AE, MM912F634CV3AE, MM912F634CC3AE from Table 1, Ordering Information, as well as references to these devices in sections 3.5, 3.6 & 3.7
• Deleted "Data Flash" column in Table 1, Ordering Information, since this feature is not available for the MM912F634
• Deleted all references to Analog Options "A3" & "A4" in Section 4.1.3, Analog Die Options
• Changed Analog Option designations from "A1" & "A2" to "1" & "2", respectively, in Table 1, Ordering Information, and Table 2, Analog Options
• Clarified instructions on use of unused pins in devices with Analog Option "2"
• Changed MM912F634Cxxxx Lx High Detection Threshold V THH (min) from 2.7 V to 2.6 V for the range 7.0 V ≤ VSUP ≤ 27 V. Changed max & typical Hysteresis VHYS for MM912F634Cxxxx. Applied these new values to the full range of 5.5 V ≤ VSUP ≤ 27 V. See Table 19, Static Electrical Characteristics - High Voltage Inputs – Lx
• Added separate HBM ESD rating (V HBM) for HSx pins of +/-3000V. See Table 46, ESD and Latch-up Protection Characteristics 3.0 10/2010 • Added MM912F634CV2AP to the ordering information
• Updated to standard form and style
• Added the 98ASA00173D (48-PIN LQFP) package drawing to the Packaging section
• Added symbol f BUSMAX to Max. Bus Frequency (MHz) column in Table 1.
• Replaced all references to 20 MHz bus frequency with f BUSMAX, and added a note referring to Table 1. See Table 8 – Operating Conditions, Table 9 – Supply Currents, Table 28 – Dynamic Electrical Characteristics – Die to Die Interface – D2D.
• Added reference to 16 MHz maximum CPU Bus Frequency for MM1912F634CV2AP to section 4.25.1.1 (MM912F634 – MCU Die Overview: Features)
• Changed Baud Rate data to reflect a 20 MHz Bus Clock in Table 409 – Example SPI Baud Rate Selection. 4.0 10/2010 • Removed part number MM912F634BV1AE from data sheet. 5.0 11/2010 • Corrected several typos throughout the document - No technical changes

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P .O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2010. All rights reserved. MM912F634 Rev. 5.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.