MM908E625ACEK

908E625_10 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• High-Performance M68HC908EY16 Core
• 16K Bytes of On-Chip Flash Memory & 512 Bytes of RAM
• Internal Clock Generation Module
• Two 16-bit, 2-Channel Timers
• 10-Bit Analog-to-Digital Converter
• LIN Physical Layer
• Autonomous Watchdog with Cyclic Wake-up
• Three Two-Pin Hall-Effect Sensor Input Ports
• One Analog Input with Switchable Current Source
• Four Low RDS(ON) Half-Bridge Outputs
• One Low RDS(ON) High-Side Output
• 13 Micro Controller I/Os
• Pb-free packaging designated by suffix code EK

Figure 1. 908E625 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MM908E625ACDWB -40°C to 85°C 54 SOICW EPMM908E625ACEK DWB SUFFIX EK SUFFIX (Pb-FREE) 98ARL105910 54-PIN SOICWB-EP VSS EVSS VSSA VREFL VDD EVDD VDDA VREFH LIN M M M FGEN PTD1/TACH1 PTE1/RXD RXD PTD0/TACH0/BEMF PTB1/AD1 BEMF SS IRQ_A RST_A IRQ RST Port C I/Os Port B I/Os Port A I/Os PA1 HVDD HS HB4 HB3 HB2 HB1 EP 908E625

4 Half-Bridges

3 Loads

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Figure 2. 908E625 Simplified Internal Block Diagram

64 Bytes

36 Bytes

24 Internal System

10 Bit Analog-to-

Figure 3. 908E625 Pin Connections (Transparent Package Top View) Table 1. 908E625 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 14. are shared with other functional modules in the MCU. are shared with other functional modules in the MCU. IRQ External Interrupt Input This pin is an asynchronous external interrupt input pin. is driven low when any internal reset source is asserted. are shared with other functional modules in the MCU. – 14, 21, 22, 33 NC No Connect Not connected.

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is shared with other functional modules in the MCU. These pins are the ground and power supply pins, respectively. The MCU operates from a single power supply. are shared with other functional modules in the MCU. MCU 51 FLSVPP Test Pin For test purposes only. Do not connect in the application. high-side inrush current limiter PWM frequency. RST_A Internal Reset This pin is the bidirectional reset pin of the analog die. Analog 19 SS Slave Select This pin is the SPI sl ave select pin for the analog chip. Analog 20 LIN LIN Bus This pin represents the single-wire bus transmitter and receiver. Power Supply Pins These pins ar e device power supply pins. Power Ground Pins These pins are device power ground connections. These pins provide inputs for Hall-effect sensors and switches. the embedded microcontroller. Analog 39 PA1 Analog Input This pin is an analog i nput port with selectable source values. connections (microcontroller and sensors). Analog 41 RXD LIN Transceiver Output This pin is the output of LIN transceiver. conducts heat from the chip to the PCB board. Table 1. 908E625 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 908E625

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. Transient capability for pulses with a time of t < 0.5 sec.
2. ESD voltage testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω)
3. ESD voltage testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω)
4. ESD voltage testing is performed in accord ance with Charge Device Model, robotic (CZAP =4.0 pF).
5. The limiting factor is junction temperatur e, taking into account the power dissipation, thermal resistance, and heat sinking.
6. The temperature of analog and MCU die is strongly linked vi a the package, but can differ in dynamic load conditions, usually because

of higher power dissipation on the analog die. The analog die temperature must not exceed 150°C under these conditions.

1. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

1. STOP mode current will increase if V SUP exceeds 15 V.
2. This parameter is guaranteed by proces s monitoring but is not production tested.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 908E625 STATIC ELECTRICAL CHARACTERISTICS SYSTEM RESETS AND INTERRUPTS High-Voltage Reset Threshold Hysteresis VHVRON VHVRH 1.5 V Low-Voltage Reset Threshold Hysteresis VLVRON VLVRH 3.6 4.0 100 4.5 V mV High-Voltage Interrupt Threshold Hysteresis VHVION VHVIH 17.5 1.0 V Low-Voltage Interrupt Threshold Hysteresis VLVION VLVIH 6.5 0.4 8.0 V High-Temperature Reset (11) Threshold Hysteresis TRON TRH 5.0 170 High-Temperature Interrupt (12) Threshold Hysteresis TION TIH 5.0 160 VOLTAGE REGULATOR Normal Mode Output Voltage IOUT = 60 mA, 6.0 V < VSUP < 18 V VDDRUN 4.75 5.0 5.25 V Load Regulation IOUT = 80 mA, VSUP = 9.0 V, TJ = 125°C VLR – – 100 mV STOP Mode Output Voltage (Maximum Output Current 100 μA) VDDSTOP 4.5 4.7 4.9 V LIN PHYSICAL LAYER Output Low Level TXD LOW, 500 Ω Pullup to VSUP VLIN-LOW – – 1.4 V Output High Level TXD HIGH, IOUT = 1.0 μA VLIN-HIGH VSUP -1.0 – – V Pullup Resistor to VSUP RSLAVE 20 30 60 kΩ Leakage Current to GND Recessive State (-0.5 V < VLIN < VSUP) IBUS_PAS_rec 0.0 – 20 μA Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18 V Including Internal Pullup Resistor, VLIN @ +18 V IBUS_NO_GND IBUS -600 μA Notes 11. This parameter is guaranteed by proces s monitoring but is not production tested. 12. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C). Table 3. Static Electrical Characteristics (continued) microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS LIN Receiver Recessive Dominant Threshold Input Hysteresis VIH VIL VITH VIHY

0.6 VLIN

0.0

0.01 VSUP

0.4 VLIN

0.1 VSUP

V LIN Wake-Up Threshold VWTH – VSUP/2 – V HIGH-SIDE OUTPUT (HS) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A RDS(ON)HS – 600 700 mΩ High-Side Overcurrent Shutdown IHSOC 3.9 – 7.0 A HALF-BRIDGE OUTPUTS (HB1:HB4) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A High Side Low Side RDS(ON)HB_HS RDS(ON)HB_LS 425 400 500 500 mΩ High-Side Overcurrent Shutdown IHBHSOC 4 . 0–7 . 5 A Low-Side Overcurrent Shutdown IHBLSOC 2 . 8–7 . 5 A Low-Side Current Limitation @ TJ = 25°C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) I CL1 ICL2 ICL3 ICL4 ICL5 210 300 450 600 260 370 550 740 315 440 650 880 mA Half-Bridge Output HIGH Threshold for BEMF Detection V BEMFH –- 3 00 V Half-Bridge Output LOW Threshold for BEMF Detection V BEMFL –- 6 0 - 5 . 0 m V Hysteresis for BEMF Detection V BEMFHY –3 0– m V Low-Side Current-to-Voltage Ratio (VADOUT [V]/I HB [A]) CSA = 1 CSA = 0 RATIOH RATIOL 7.0 1.0 12.0 2.0 14.0 3.0 V/A SWITCHABLE VDD OUTPUT (PH.D.) Overcurrent Shutdown Threshold IHVDDOCT 24 30 40 mA VSUP DOWN-SCALER Voltage Ratio (RATIOVSUP = VSUP /VADOUT)R A T I O VSUP 4.8 5.1 5.35 – INTERNAL DIE TEMPERATURE SENSOR Voltage/Temperature Slope S TtoV –1 9– m V / ° C Output Voltage @ 25°C V T25 1.7 2.1 2.5 V HALL-EFFECT SENSOR INPUTS (H1:H3) Output Voltage VSUP < 16.2 V VSUP > 16.2 V VHALL1 VHALL2 VSUP-1.2 V microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 908E625 STATIC ELECTRICAL CHARACTERISTICS Sense Current Threshold Hysteresis IHSCT IHSCH 6.9 8.8 0.88 mA Output Current Limitation IHL – 90 – mA Overcurrent Warning HP_OCF Flag Threshold] VHPOCT – 3.0 – V Dropout Voltage @ ILOAD = 15 mA VHPDO – 0.5 – V ANALOG INPUT (PA1) Current Source PA1 CSSEL1 = 1, CSSEL0 = 1 ICSPA1 570 670 770 μA Selectable Scaling Factor Current Source PA1 (I(N) = ICSPA1* N) CSSEL1 = 0, CSSEL0 = 0 CSSEL1 = 0, CSSEL0 = 1 CSSEL1 = 1, CSSEL0 = 0 NCSPA1-0 NCSPA1-1 NCSPA1-2 8.5 28.5 58.5 11.5 31.5 61.5 microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS MICROCONTROLLER PARAMETRICS Table 4. Dynamic Electrical Characteristics microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

1. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00).

Table 5. Microcontroller Description For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 908E625 MICROCONTROLLER PARAMETRICS ESCI Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment ICG Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%) BEMF Counter Special Counter for SMARTMOS™ BEMF Output For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.

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Figure 4. LIN Timing Description Figure 5. LIN Slew Rate Description

0.9 VSUP

0.4 VSUP

0.6 VSUP

0.8 VSUP

0.2 VSUP

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The 908E625 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E625 is well suited to perform complete mirror, door lock, and light-levelling control all via a three-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS ™ IC chip. The SMARTMOS™ IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS™ IC configured as half-bridge outputs with one high-side switch. Other ports are also provided; they include Hall-effect sensor input ports, analog input ports, and a selectable HVDD pin. An internal voltage regulator is provided on the SMARTMOS™ IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL PIN DESCRIPTION See Figure 1 for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on Figure 3 for a depiction of the pin locations on the package. PORT A I/O PINS (PTA0:4) These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt pins, KBD0:KBD4. The PTA5/SPSCK pin is not accessible in this device and is internally connected to the SPI clock pin of the analog die. The PTA6/SS pin is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT B I/O PINS (PTB1, PTB3:7) These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. All pins are shared with the ADC module. The PTB6:PTB7 pins are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT pin of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, V SUP, etc. The PTB2/AD2 pin is not accessible in this device. For details refer to the 68HC908EY16 datasheet. PORT C I/O PINS (PTC2:4) These pins are special-function, bidirectional I/O port pins that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI pins of the analog die. For details refer to the 68HC908EY16 datasheet. PORT D I/O PINS (PTD0:1) PTD1/TACH1 and PTD0/TACH0/BEMF are special- function, bidirectional I/O port pins that can also be programmed to be timer pins. In step motor applications the PTD0 pin should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 pin is recommended for use as an output pin for generating the FGEN signal (PWM signal) if required by the application. PORT E I/O PIN (PTE1) PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port pins that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD pin of the analog die. The connection for the receiver must be done externally. EXTERNAL INTERRUPT PIN (IRQ) The IRQ pin is an asynchronous external interrupt pin. This pin contains an internal pull-up resistor that is always activated, even when the IRQ pin is pulled LOW. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET PIN (RST) A Logic [0] on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This pin contains an internal pull-up resistor that is always activated, even when the reset pin is pulled LOW. For details refer to the 68HC908EY16 datasheet.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 908E625 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CURRENT LIMITATION FREQUENCY INPUT PIN (FGEN) Input pin for the half-bridge current limitation and the high- side inrush current limiter PWM frequency. This input is not a real PWM input pin; it should just supply the period of the PWM. The duty cycle will be generate automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. BACK ELECTROMAGNETIC FORCE OUTPUT PIN (BEMF) This pin gives the user information about back electromagnetic force (BEMF). This feature is mainly used in step motor applications for detecting a stalled motor. In order to evaluate this signal the pin must be directly connected to pin PTD0/TACH0/BEMF. RESET PIN (RST_A) RST_A is the bidirectional reset pin of the analog die. It is an open drain with pull-up resistor and must be connected to the RST pin of the MCU. INTERRUPT PIN (IRQ_A) IRQ_A is the interrupt output pin of the analog die indicating errors or wake-up events. It is an open drain with pull-up resistor and must be connected to the IRQ pin of the MCU. SLAVE SELECT PIN (SS) This pin is the SPI Slave Select pin for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I/O of the microcontroller. LIN BUS PIN (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. HALF-BRIDGE OUTPUT PINS (HB1:HB4) The 908E625 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1:HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs. POWER SUPPLY PINS (VSUP1:VSUP3) VSUP1:VSUP3 are device power supply pins. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple VSUP pins are provided. All VSUP pins must be connected to get full chip functionality. POWER GROUND PINS (GND1 AND GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple pins are provided. GND1 and GND2 pins must be connected to get full chip functionality. HIGH-SIDE OUTPUT PIN (HS) The HS output pin is a low RDS(ON) high-side switch. The switch is protected against over-temperature and overcurrent. The output is capable of limiting the inrush current with an automatic PWM generation using the FGEN module. SWITCHABLE VDD OUTPUT PIN (HVDD) The HVDD pin is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-pin Hall-effect sensors. The output is short-circuit protected. HALL-EFFECT SENSOR INPUT PINS (H1:H3) The Hall-effect sensor input pins H1:H3 provide inputs for Hall-effect sensors and switches. +5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD) The VDD pin is needed to place an external capacitor to stabilize the regulated output voltage. The VDD pin is intended to supply the embedded microcontroller. Important The VDD pin should not be used to supply other loads; use the HVDD pin for this purpose. The VDD, EVDD, VDDA, and VREFH pins must be connected together. ANALOG INPUT PIN (PA1) This pin is an analog input port with selectable current source values. VOLTAGE REGULATOR GROUND PIN (VSS) The VSS pin is the ground pin for the connection of all non- power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL pins must be connected together. LIN TRANSCEIVER OUTPUT PIN (RXD) This pin is the output of LIN transceiver. The pin must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD pin).

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FUNCTIONAL PIN DESCRIPTION ADC REFERENCE PINS (VREFL AND VREFH) VREFL and VREFH are the reference voltage pins for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these pins. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. ADC SUPPLY PINS (VDDA AND VSSA) VDDA and VSSA are the power supply pins for the analog- to-digital converter (ADC). It is recommended that a high- quality ceramic decoupling capacitor be placed between these pins. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground pin for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY PINS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short- duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. TEST PIN (FLSVPP) This pin is for test purposes only. This pin should be either left open (not connected) or connected to GND. EXPOSED PAD PIN The exposed pad pin on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 908E625 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTERRUPTS The 908E625 has seven different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. LOW-VOLTAGE INTERRUPT The Low-Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. HIGH-VOLTAGE INTERRUPT The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. HIGH-TEMPERATURE INTERRUPT The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the High- Temperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. AUTONOMOUS WATCHDOG INTERRUPT (AWD) Refer to Autonomous Watchdog Autonomous Watchdog (AWD) on page 39. LIN INTERRUPT If the LINIE bit is set, a falling edge on the LIN pin will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up. HALL-EFFECT SENSOR INPUT PIN INTERRUPT If the PHIE bit is set, the enabled Hall-Effect Sensor input pins H1:H3 can generate an interrupt if a current above the threshold is detected. During STOP mode this interrupt, combined with the cyclic wake-up feature of the AWD, can wake up the system. Refer to pin Hall-Effect Sensor Input Pins (H1:H3). OVERCURRENT INTERRUPT If an overcurrent condition on a half-bridge occurs, the high-side or the HVDD output is detected and the OCIE bit is set and an interrupt generated. SYSTEM WAKE-UP System wake-up can be initiated by any of four events:

• A falling edge on the LIN pin
• A wake-up signal from the AWD
• A Logic [1] at Hall-effect sensor input pin during cyclic check via AWD
• An LVR condition If one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake-up the microcontroller as well as the main voltage regulator (MREG) (Figure 8

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Figure 8. STOP Mode/Wake-Up Procedure

microcontroller and the 908E625.

• SS—Slave Select
• MOSI—Master-Out Slave-In
• MISO—Master-In Slave-Out
• SPSCK—Serial Clock A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address.

Figure 9. SPI Protocol clock edges are present in the active phase of SS. is transferred. SS HIGH forces MISO to high impedance. Contains the address of the desired register. Contains information about a read or a write operation.

• I f R /W = 1, the second byte of master contains no valid information, slave just transmits back register data.
• I f R /W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to write operation, write data is latched in the SMARTMOS™ register on rising edge of SS. PARITY P The parity bit is equal to 0 if the number of 1 bits is an even number contained within R/W, A4:A0. If the number of 1 bits is odd, P equals 1. For example, if R/W = 1, A4:A0 = 00001, then P equals 0. The parity bit is only evaluated during a write operation. BIT X Not used. MASTER DATA BYTE Contains data to be written or no valid data during a read operation. SLAVE STATUS BYTE Contains the contents of the System Status Register ($0c) independent of whether it is a write or read operation or which register was selected. S7 S6 S5 S4 S3 S2 S1 S0 R/W A4 A3 A2 A1 A0 P X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 System Status Register Read/Write, Address, Parity Data (Register write) Data (Register read) Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data SS MOSI MISO SPSCK

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Table 6. List of Registers

0 HPIE LINIE HTIE LVIE HVIE OCIE

0 HPF LINF HTF LVF HVF

by writing a Logic [1] to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has no effect.

• 1 = State change on the hallflags detected
• 0 = No state change on the hallflags detected STOP Mode An interrupt will be generated when AWDCC is set and a current above the threshold is detected on any enabled Hall- effect sensor input pin. Clear HPF by writing a Logic [1] to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has no effect.
• 1 = One or more of the selected Hall-effect sensor input pins had been pulled HIGH
• 0 = None of the selected Hall-effect sensor input pins has been pulled HIGH LIN Flag Bit (LINF) This read/write flag is set on the falling edge at the LIN data line. Clear LINF by writing a Logic [1] to LINF. Reset clears the LINF bit. Writing a Logic [0] to LINF has no effect.
• 1 = Falling edge on LIN data line has occurred
• 0 = Falling edge on LIN data line has not occurred since last clear High-Temperature Flag Bit (HTF) This read/write flag is set on a high-temperature condition. Clear HTF by writing a Logic [1] to HTF. If a high-temperature condition is still present while writing a Logic [1] to HTF, the writing has no effect. Therefore, a high-temperature interrupt cannot be lost due to inadvertent clearing of HTF. Reset clears the HTF bit. Writing a Logic [0] to HTF has no effect.
• 1 = High-temperature condition has occurred
• 0 = High-temperature condition has not occurred Low-Voltage Flag Bit (LVF) This read/write flag is set on a low-voltage condition. Clear LVF by writing a Logic [1] to LVF. If a low-voltage condition is still present while writing a Logic [1] to LVF, the writing has no effect. Therefore, a low-voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a Logic [0] to LVF has no effect.
• 1 = Low-voltage condition has occurred
• 0 = Low-voltage condition has not occurred High-Voltage Flag Bit (HVF) This read/write flag is set on a high-voltage condition. Clear HVF by writing a Logic [1] to HVF. If high-voltage condition is still present while writing a Logic [1] to HVF, the writing has no effect. Therefore, a high-voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a Logic [0] to HVF has no effect.
• 1 = High-voltage condition has occurred
• 0 = High-voltage condition has not occurred Overcurrent Flag Bit (OCF) This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a Logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 10 ,illustrating the three signals triggering the OCF.
• 1 = High-current condition has occurred
• 0 = High-current condition has not occurred

Figure 10. Principal Implementation for OCF

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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS INTERRUPT MASK REGISTER (IMR) Hall-Effect Sensor Input Pin Interrupt Enable Bit (HPIE) This read/write bit enables CPU interrupts by the Hall- effect sensor input pin flag, HPF. Reset clears the HPIE bit.

• 1 = Interrupt requests from HPF flag enabled
• 0 = Interrupt requests from HPF flag disabled LIN Line Interrupt Enable Bit (LINIE) This read/write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit.
• 1 = Interrupt requests from LINF flag enabled
• 0 = Interrupt requests from LINF flag disabled High-Temperature Interrupt Enable Bit (HTIE) This read/ write bit enables CPU interrupts by the high- temperature flag, HTF. Reset clears the HTIE bit.
• 1 = Interrupt requests from HTF flag enabled
• 0 = Interrupt requests from HTF flag disabled Low-Voltage Interrupt Enable Bit (LVIE) This read/write bit enables CPU interrupts by the low- voltage flag, LVF. Reset clears the LVIE bit.
• 1 = Interrupt requests from LVF flag enabled
• 0 = Interrupt requests from LVF flag disabled High-Voltage Interrupt Enable Bit (HVIE) This read/write bit enables CPU interrupts by the high- voltage flag, HVF. Reset clears the HVIE bit.
• 1 = Interrupt requests from HVF flag enabled
• 0 = Interrupt requests from HVF flag disabled Overcurrent Interrupt Enable Bit (OCIE) This read/write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit.
• 1 = Interrupt requests from OCF flag enabled
• 0 = Interrupt requests from OCF flag disabled Register Name and Address: IMR - $04 Bits 7 6 5 4 3 2 1 0 Read

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RESET EXTERNAL SOURCE External Reset Pin The microcontroller has the capability of resetting the SMARTMOS™ device by pulling down the RST pin. RESET MASK REGISTER (RMR) High-Temperature Reset Test (TTEST) This read/write bit is for te st purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the HTRE bit.

• 1 = Low-temperature threshold enabled
• 0 = Low-temperature threshold disabled High-Voltage Reset Enable Bit (HVRE) This read/write bit enables resets on high-voltage conditions. Reset clears the HVRE bit.
• 1 = High-voltage reset enabled
• 0 = High-voltage reset disabled High-Temperature Reset Enable Bit (HTRE) This read/write bit enables resets on high-temperature conditions. Reset clears the HTRE bit.
• 1 = High-temperature reset enabled
• 0 = High-temperature reset disabled Register Name and Address: RMR - $06 Bits 7 6 5 4 3 2 1 0 Read TTEST 0 0 0 0 0 HVRE HTRE Write Reset 0 0 0 0 0 0 0 0

Analog Integrated Circuit Device Data Freescale Semiconductor 25 908E625 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS ANALOG DIE I/OS LIN Physical Layer The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull- up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. TXD PIN The TXD pin is the MCU interface to control the state of the LIN transmitter (see Figure 1). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD pin has an internal pull-up current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD PIN The RXD transceiver pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP MODE/WAKE-UP FEATURE During STOP mode operation the transmitter of the physical layer is disabled. The receiver pin is still active and able to detect wake-up events on the LIN bus line. If LIN interrupt is enabled (LINIE bit in the Interrupt Mask Register is set), a falling edge on the LIN line causes an interrupt. This interrupt switches on the main voltage regulator and generates a system wake-up. Analog Multiplexer/ADOUT Pin The ADOUT pin is the analog output interface to the ADC of the MCU. See Figure 12 . An analog multiplexer is used to read seven internal diagnostic analog voltages. Current Recopy The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V/2.5 A or 5.0 V/500 mA, respectively. Refer to Half- Bridge Current Recopy on page 34.) Analog Input PA1 The analog input PA1 is directly connected to the analog multiplexer, permitting analog values from the periphery to be read. TEMPERATURE SENSOR The 908E625 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP PRESCALER The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP/RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. ANALOG MULTIPLEXER CONFIGURATION REGISTER (ADMUX) SS3, SS2, SS1, and SS0—A/D Input Select Bits These read/write bits select the input to the ADC in the microcontroller according to Table 7. Reset clears SS3, SS2, SS1, and SS0 bits. Register Name and Address: ADMUX - $07 Bits 7 6 5 4 3 2 1 0 Read 0 0 0 0 SS3 SS2 SS1 SS0 Write Reset 0 0 0 0 0 0 0 0

26 Freescale Semiconductor

potentiometers or resistor values, etc. multiple switches on one input. Output Register (POUT) is set. Figure 12. Analog Input PA1 and Multiplexer Table 7. Analog Multiplexer Configuration Register Table 8. PA1 Current Source Level Selection Bits

These read/write bits select the current source values. Reset clears the CSSEL0:CSSEL1 bits. This read/write bit enables the current source for PA1. Reset clears the CSEN bit (Table 9).

• 1 = HVDD enabled
• 0 = HVDD disabled Lamp Driver On Bit (HS_ON) This read/write bit enables the Lamp driver. Reset clears the HS_ON bit.
• 1 = Lamp driver enabled
• 0 = Lamp driver disabled Hall-Effect Sensor Input Pins (H1:H3) Function The Hall-effect sensor input pins provide three inputs for two-pin Hall-effect sensors for detecting stall and position or reading Hall-effect sensor contact switches. The Hall-effect sensor input pins are not influenced by the PSON bit in the System Control Register. Each pin of the Hall-effect sensor can be enabled by setting the HxEN bit in the Hall-Effect Sensor Input Pin Control Register (HACTL). If the pins are enabled, the Hall- effect sensors are supplied with V SUP voltage and the sense circuitry is working. An internal clamp circuity limits the supply voltage to the sensor to 15 V. This sense circuitry monitors the current to VSS. The result of this sense operation is given by the HxF flags in the Hall-Effect Sensor Input Pin Status Register (HASTAT). The flag is set if the sensed current is higher than IHSCT. To prevent noise on this flag, a hysteresis is implemented on these pins. After switching on the Hall-effect sensor input pins (HxEN = 1), the Hall-effect sensors need some time to stabilize the output. In RUN mode the software must wait at least 40 μs between enabling the Hall-effect sensor and reading the hall flag. The Hall-effect sensor input pin works in an dynamic output voltage range from VSUP down to 2.0 V. Below 2.0 V the hallflags are not functional anymore. If the output voltage is below a certain threshold, the Hall-Effect Sensor Input Pin Overcurrent Flag (HP_OCF) in the System Status Register is set. Figures 13 through 15 illustrate the connections to the Hall-effect input sensors. Register Name and Address: POUT - $0b Bits 7 6 5 4 3 2 1 0 Read 0 0 CSSEL1 CSSEL0 CSEN 0(16) HVDDON HS_ON Write Reset 0 0 0 0 0 0 0 0 Notes 16. This bit must always be set to 0.

Table 9. PA1 Current Source Enable Bit

0 Current Source Off

1 Current Source On

28 Freescale Semiconductor

Figure 13. Hall-Effect Sensor Input Pin Connected to Two-Pin Hall-Effect Sensor Figure 14. Hall-Effect Sensor Input Pin Connected to Local Switch

Figure 15. Hall-Effect Sensor Input Pin Connected to Three-Pin Hall-Effect Sensor The Hall-effect sensor input pins are interrupt capable. operating mode, RUN or Stop. flag should be cleared in order to prevent a wrong interrupt. disabled independent of the state of the HxEN flags. wake-up feature of the AWD (Autonomous Watchdog). wakes up the MCU and starts the main voltage regulator.

• The two-pin Hall-effect sensor input is enabled (HxEN = 1)
• The cyclic wake-up of the AWD is enabled (AWDCC = 1); see Figure 16
• The Hall-effect sensor input pin interrupt is enabled (HPIE = 1) HxEN HxF Sense Circuitry V Hx GND Three-Terminal Hall-Effect Sensor Out Vs GND

30 Freescale Semiconductor

Figure 16. Hall-Effect Sensor Input Pin Cyclic Check Wake-Up Feature pins. Reset clears the H3EN:H1EN bits.

• 1 = Hall-effect sensor input pin Hx switched on and sensed
• 0 = Hall-effect sensor input pin Hx disabled SPI: AWDCC = 1 GS = 1 STOP IRQ? SPI: Reason for Wakeup Operate STOP MREG AWD Timer Overflow? Switch on Selected Hallport Wait 40 µs Hallport = 1Assert IRQ_A Yes No Yes No Yes No IRQ_A = 0 Start MREG SPI Command Switch off Selected Hallport MREG = Main Voltage Regulator Register Name and Address: HACTL - $08 Bits 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 H3EN H2EN H1EN Write Reset 0 0 0 0 0 0 0 0

• 1 = Hall-effect sensor input pin current above threshold
• 0 = Hall-effect sensor input pin current below threshold HALF-BRIDGES Outputs HB1:HB4 provide four low-resistive half-bridge output stages. The half-bridges can be used in H-Bridge, high-side, or low-side configurations. Reset clears all bits in the H-Bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1:HB4 output features:
• Short circuit (overcurrent) protection on high-side and low-side MOSFETs
• Current recopy feature (low side MOSFET)
• Overtemperature protection
• Overvoltage and undervoltage protection
• Current limitation feature (low side MOSFET)

Figure 17. Half-Bridge Push-Pull Output Driver high-side MOSFET has a higher priority. the high-side MOSFET did not fall below a certain threshold.

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS HALF-BRIDGE OUTPUT REGISTER (HBOUT) Low-Side On/Off Bits (HBx_L) These read/write bits turn on the low-side MOSFETs. Reset clears the HBx_L bits.

• 1 = Low-side MOSFET turned on for half-bridge output x
• 0 = Low-side MOSFET turned off for half-bridge output x High-Side On/Off Bits (HBx_H) These read/write bits turn on the high-side MOSFETs. Reset clears the HBx_H bits.
• 1 = High-side MOSFET turned on for half-bridge output x
• 0 = High-side MOSFET turned on for half-bridge output x HALF-BRIDGE CURRENT LIMITATION Each low-side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width modulation on the low-side MOSFET. The pulse width modulation on the outputs is controlled by the FGEN input and the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics. The recommended frequency range for the FGEN and the PWM is 0.1 kHz to 20 kHz. Functionality Each low-side MOSFET switches off if a current above the selected current limit was detected. The 908E625 offers five different current limits. Refer to Table 10 for current limit values. The low-side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 18). Register Name and Address: HBOUT - $01 Bits 7 6 5 4 3 2 1 0 Read HB4_ H HB4_ L HB3_ H HB3_ L HB2_ H HB2_ L HB1_ H HB1_ L Write Reset 0 0 0 0 0 0 0 0

Figure 18. Half-Bridge Current Limitation

34 Freescale Semiconductor

Figure 19. Offset Chopping for Step Motor Control and switched to the analog multiplexer. selected via bit CSA in the System Control Register.

• CSA = 1: Low resolution selected (500 mA measurement range)
• CSA = 0: High resolution selected (2.5 A measurement range) HALF-BRIDGE BEMF GENERATION The BEMF output is set to 1 if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal), see Figure 20 Coil2 Current Coil1 Current Current in VSUP Line FGEN Input (MCU PWM Signal) Coil1….. Coil2….. HB1 HB2 HB3 HB4

Figure 20. BEMF Signal Generation HB_OCF in the System Status Register (SYSSTAT) is set. System Status Register or by reset.

• 1 = Offset chopping enabled
• 0 = Offset chopping disabled Coil Current Voltage on BEMF Signal Register Name and Address: HBCTL - $02 Bits 7 6 5 4 3 2 1 0 Read OFC_EN CSA 0 0 0 CLS2 CLS1 CLS0 Write Reset 0 0 0 0 0 0 0 0

36 Freescale Semiconductor

of the H-Bridges. Reset clears the CSA bit.

• 1 = Current sense amplification set for measuring 0.5 A.
• 0 = Current sense amplification set for measuring 2.5 A. H-Bridge Current Limitation Selection Bits (CLS2:CLS0) These read/write bits select the current limitation value according to Table 10. Reset clears the CLS2:CLS0 bits. HIGH-SIDE DRIVER The high-side output is a low-resistive high-side switch targeted for driving lamps. The high side is protected against over-temperature. To limit the high inrush current of bulbs, overcurrent protection circuitry is used to limit the current. The output is enabled with bit PSON in the System Control Register and can be switched on/off with bit HS_ON in the Power Output Register. Figure 21 depicts the high-side switch circuitry and connection to external lamp. HIGH-SIDE OVERVOLTAGE/UNDERVOLTAGE PROTECTION The high-side output pin, HS, is protected against under- voltage/over-voltage conditions . This protection is done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the output is disabled. The overvoltage/undervoltage status flags are cleared and the output re-enabled by writing a Logic [1] to the LVF/ HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present.

Figure 21. High-Side Circuitry Table 10. H-Bridge Current Limitation Value Selection

the part generates a reset and disables all power outputs. automatically switches off and the overcurrent flag is set. Figure 22. Inrush Current Limiter on High-Side Output used for driving external circuitry that requires a VDD voltage. HVI) have no influence on this circuitry. temperature reset is enabled. the System Status Register is set.

38 Freescale Semiconductor

and HVDD output). Reset clears the PSON bit.

• 1 = Power stages enabled.
• 0 = Power stages disabled. LIN Slew Rate Selection Bits (SRS0:SRS1) These read/write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 11. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application. Go to STOP Mode Bit (GS) This write-only bit instructs the 908E625 to power down and go into STOP mode. Reset or CPU interrupt requests clear the GS bit.
• 1 = Power down and go into STOP mode
• 0 = Not in STOP mode SYSTEM STATUS REGISTER (SYSSTAT) Hall-Effect Sensor Input Pin Overcurrent Flag Bit (HP_OCF) This read/write flag is set on an overcurrent condition at one of the Hall-effect sensor input pins. Clear HP_OCF and enable the output by writing a Logic [1] to the HP_OCF flag. Reset clears the HP_OCF bit. Writing a Logic [0] to HP_OCF has no effect.
• 1 = Overcurrent condition on Hall-effect sensor input pin has occurred
• 0 = No overcurrent condition on Hall-effect sensor input pin has occurred LIN Current Limitation Bit (LINCL) This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately.
• 1 = Transmitter operating in current limitation region
• 0 = Transmitter not operating in current limitation region HVDD Output Overcurrent Flag Bit (HVDD_OCF) This read/write flag is set on an overcurrent condition at the HVDD pin. Clear HVDD_OCF and enable the output by writing a Logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF bit. Writing a Logic [0] to HVDD_OCF has no effect.
• 1 = Overcurrent condition on HVDD has occurred
• 0 = No overcurrent condition on HVDD has occurred High-Side Overcurrent Flag Bit (HS_OCF) This read/write flag is set on an overcurrent condition at the high-side driver. Clear HS_OCF and enable the high-side driver by writing a Logic [1] to HS_OCF. Reset clears the HS_OCF bit. Writing a Logic [0] to HS_OCF has no effect.
• 1 = Overcurrent condition on high-side drivers has occurred
• 0 = No overcurrent condition on high-side drivers has occurred Low-Voltage Bit (LVF) This read only bit is a copy of the LVF bit in the Interrupt Flag Register.
• 1 = Low-voltage condition has occurred
• 0 = No low-voltage condition has occurred High-Voltage Sensor Bit (HVF) This read-only bit is a copy of the HVF bit in the Interrupt Flag Register.
• 1 = High-voltage condition has occurred
• 0 = No high-voltage condition has occurred H-Bridge Overcurrent Flag Bit (HB_OCF) This read / write flag is set on an overcurrent condition at the H-Bridges. Clear HB_OCF and enable the H-Bridge driver by writing a Logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a Logic [0] to HB_OCF has no effect.
• 1 = Overcurrent condition on H-Bridges has occurred
• 0 = No overcurrent condition on H-Bridges has occurred Register Name and Address: SYSCTL - $03 Bits 7 6 5 4 3 2 1 0 Read PSON SRS1 SRS0 0 0 0 0 0 Write GS Reset 00000000

Table 11. LIN Slew Rate Selection Bits

Analog Integrated Circuit Device Data Freescale Semiconductor 39 908E625 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Overtemperature Status Bit (HTF) This read-only bit is a copy of the HTF bit in the Interrupt Flag Register.

• 1 = Overtemperature condition has occurred
• 0 = No overtemperature condition has occurred AUTONOMOUS WATCHDOG (AWD) The Autonomous Watchdog module consists of three functions:
• Watchdog function for the CPU in RUN mode
• Periodic interrupt function in STOP mode
• Cyclic wake-up function in STOP mode The AWD is enabled if AWDIE, AWDRE, or AWDCC in the AWDCTL Register is set. If these bits are cleared, the AWD oscillator is disabled and the watchdog switched off. WATCHDOG The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. PERIODIC INTERRUPT Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. CYCLIC WAKE-UP The cyclic wake-up feature is only available in STOP mode. If this feature is enabled, the selected Hall-effect sensor input pins are switched on and sensed. If a “1” is detected on one of these inputs and the interrupt for the Hall- effect sensors is enabled, a system wake-up is performed. (Switch on main voltage regulator and assert IRQ_A to the microcontroller). AUTONOMOUS WATCHDOG CONTROL REGISTER (AWDCTL) Autonomous Watchdog Reset Bit (AWDRST) This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit.
• 1 = Reset AWD and restart timeout period
• 0 = No effect Autonomous Watchdog Reset Enable Bit (AWDRE) This read/write bit enables resets on AWD time-outs. A reset on the RST_A is only asserted when the device is in RUN mode. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit.
• 1 = Autonomous watchdog enabled
• 0 = Autonomous watchdog disabled Autonomous Watchdog Interrupt Enable Bit (AWDIE) This read/write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit.
• 1 = CPU interrupt requests from AWDF enabled
• 0 = CPU interrupt requests from AWDF disabled Autonomous Watchdog Cyclic Check (AWDCC) This read/write bit enables the cyclic check of the two-pin Hall-effect sensor and the analog inputs. Reset clears the AWDCC bit.
• 1 = Cyclic check of the Hall-effect sensor and analog port
• 0 = No cyclic check of the Hall-effect sensor and analog port Autonomous Watchdog Timeout Flag Bit (AWDF) This read/write flag is set when the Autonomous Watchdog has timed out. Clear AWDF by writing a Logic [1] to AWDF. Clearing AWDF also resets the AWD counter and starts a new timeout period. Reset clears the AWDF bit. Writing a Logic [0] to AWDF has no effect.
• 1 = AWD has timed out
• 0 = AWD has not yet timed out Register Name and Address: AWDCTL - $0a Bits 7 6 5 4 3 2 1 0 Read 00 0 AWDR E AWDI E AWDC C AWDF AWD RWrite AWDRS T Reset 00 0 0 0 0 0 0

Analog Integrated Circuit Device Data

40 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION FACTORY TRIMMING AND CALIBRATION Autonomous Watchdog Rate Bit (AWDR) This read/write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit.

• 1 = Fast rate selected (10 ms)
• 0 = Slow rate selected (20 ms) VOLTAGE REGULATOR The 908E625 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD pin to provide the 5.0 V to the microcontroller. RUN Mode During RUN mode the main voltage regulator is on. It provides a regulated supply to all digital sections. STOP Mode During STOP mode the STOP mode regulator supplies a regulated output voltage. The STOP mode regulator has a very limited output current capability. The output voltage will be lower than the output voltage of the main voltage regulator. FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E625, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state:
• 0xFD80:0xFDDF Trim and Calibration Values
• 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate this dependencies a ICG trim values is located at address $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) V DD = 5V, TAmbient~25°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to copied after every reset.

• nominal 12V rather than 5V or 3V supply
• high voltage V TST might be applied not only to IRQ pin, but IRQ_A pin For a detailed information on the MCU related development support see the MC68HC908EY16 datasheet - section development support. The programming is principally possible at two stages in the manufacturing process - first on chip level, before the IC is soldered onto a pcb board and second after the IC is soldered onto the pcb board. Chip level programming On Chip level the easiest way is to only power the MCU with +5V (see Figure 23) and not to provide the analog chip with VSUP, in this setup all the analog pin should be left open (e.g. VSUP[1:3]) and interconnections between MCU and analog die have to be separated (e.g. IRQ - IRQ_A). This mode is well described in the MC68HC908EY16 datasheet - section development support.

Figure 23. Normal Monitor Mode Circuit (MCU only) Vsup (12V) instead as described in Figure 24, page 42.

42 Freescale Semiconductor

Figure 24. Normal Monitor Mode Circuit Table 12. Monitor Mode Signal Requirements and Options

1. PTA0 must have a pull-up resistor to V DD in monitor mode
2. External clock is a 4.9152MHz, 9.8304M Hz or 19.6608MHz canned oscillator on OCS1
3. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
4. V TST is a high voltage VDD +3 . 5 V ≤ VTST ≤ VDD +4 . 5 V

44 Freescale Semiconductor

Figure 26. PCB Layout Recommendations Table 13. Component Value Recommendation should be connected right at the C3. C5 180pF, SMD Ceramic, Low ESR Close (<5mm) to LIN pin. Total Capacitance on LIN has to be below 220pF.

1. Freescale does not assume liability, endorse , or want components from external manufactures that are referenced in circuit drawings
2. Components are recommended to improve EMC and ESD performance.

Analog Integrated Circuit Device Data Freescale Semiconductor 45 908E625 PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL105910. DWB SUFFIX 54-PIN PLASTIC PACKAGE 98ARL105910 ISSUE B NOTES: DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF HTE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM. EXACT SHAPE OF EACH CORNER IS OPTIONAL. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTOM OF THE PLASTIC BODY. 17.8 7.4 27 28 B C7.6 18.0 10.3 5.15

0.3 A B C

0.10 A 2.35 SEATING PLANE 0.65 A 54X 52X 2.65 0.9 SECTION B-B R0.08 MIN 0.1 0.0 0.50˚ 0.25 GAUGE PLANE MIN (1.43) A A CC (0.29) 0.38 0.30 (0.25) PLATING BASE METAL SECTION A-A ROTATED 90˚ CLOCKWISE 0.25 0.22 M0.13 CAB 10.9 9.7

0.30 CAB

5.3 4.8

46 Freescale Semiconductor

electrical, application and packaging information is provided in the data sheet. temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. RθJ21 and RθJ22, respectively. by measurement and simulation according to the standards listed below. Figure 27. Thermal Land Pattern for Direct Thermal Table 14. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7and
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

1. Single layer thermal test board per JEDEC JESD51-3 and
2. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

Figure 28. Thermal Test Board where the junction temperature is sensed. Table 15. Thermal Resistance Performance

Analog Integrated Circuit Device Data

48 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 7.0 9/2010 • Implemented Revision History page

• Changed Peak Package Reflow Temperature During Reflow(7)(8) description.
• Added note (8)

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