908E625 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• High-Performance M68HC908EY16 Core • 16 K Bytes of On-Chip Flash Memory • 512 Bytes of RAM • Internal Clock Generation Module • Two 16-bit, 2-Channel Timers • 10-Bit Analog-to-Digital Converter • LIN Physical Layer • Autonomous Watchdog with Cyclic Wakeup • Three Two-Terminal Hall-Effect Sensor Input Ports • One Analog Input with Switchable Current Source • Four Low RDS(ON) Half-Bridge Outputs • One Low RDS(ON) High-Side Output • 13 Micro Controller I/Os Figure 1. 908E625 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MM908E625ACDWB -40°C to 85°C 54 SOICW EP DWB SUFFIX 98ARL105910 54-TERMINAL SOICWB-EP VSS EVSS VSSA VREFL VDD EVDD VDDA VREFH LIN M M M FGEN PTD1/TACH1 PTE1/RXD RXD PTD0/TACH0/BEMF PTB1/AD1 BEMF SS IRQ_A RST_A IRQ RST Port C I/Os Port B I/Os Port A I/Os PA1 HVDD HS HB4 HB3 HB2 HB1 EP 908E625

4 Half-Bridges

3 Loads

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Figure 2. 908E625 Simplified Internal Block Diagram

64 Bytes

36 Bytes

24 Internal System

10 Bit Analog-to-

Figure 3. 908E625 Terminal Connections (Transparent Package Top View) Table 1. 908E625 Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 15. – 14, 21, 22, 33 NC No Connect Not connected.

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that can is shared with other functional modules in the MCU. analog-to-digital converter (ADC). respectively. The MCU operates from a single power supply. MCU 51 FLSVPP Test Terminal For test purposes only. Do not connect in the application. and the high-side inrush current limiter PWM frequency. electromagnetic force (BEMF). RST_A Internal Reset This terminal is the bidirectional reset terminal of the analog die. indicating errors or wake-up events. Analog 19 SS Slave Select This terminal is the SPI sl ave select terminal for the analog chip. These terminals are device power supply terminals. These terminals are device power ground connections. supply the embedded microcontroller. connections (microcontroller and sensors). Table 1. 908E625 Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 15.

Analog 41 RXD LIN Transceiver Output This term inal is the output of LIN transceiver. conducts heat from the chip to the PCB board. A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 15.

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Table 2. Maximum Ratings permanent damage to the device.

  1. Transient capability for pulses with a time of t < 0.5 sec.
  2. ESD voltage testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω)
  3. ESD voltage testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω)
  4. ESD voltage testing is performed in accord ance with Charge Device Model, robotic (CZAP =4.0 pF).
  5. The limiting factor is junction temperatur e, taking into account the power dissipation, thermal resistance, and heat sinking.
  6. The temperature of analog and MCU die is strongly linked vi a the package, but can differ in dynamic load conditions, usually because

of higher power dissipation on the analog die. The analog die temperature must not exceed 150°C under these conditions.

  1. Terminal soldering temperature is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

Table 3. Static Electrical Characteristics microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

  1. STOP mode current will increase if V SUP exceeds 15 V.
  2. This parameter is guaranteed by proces s monitoring but is not production tested.

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  1. This parameter is guaranteed by proces s monitoring but is not production tested.
  2. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C).

Table 3. Static Electrical Characteristics (continued) microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

0.6 VLIN

0.01 VSUP

0.4 VLIN

0.1 VSUP

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Table 4. Dynamic Electrical Characteristics microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

  1. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00).

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Table 5. Microcontroller Description For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.

Figure 4. LIN Timing Description Figure 5. LIN Slew Rate Description

0.9 VSUP

0.4 VSUP

0.6 VSUP

0.8 VSUP

0.2 VSUP

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Figure 6. Free Wheel Diode Forward Voltage vs ILOAD Figure 7. Dropout Voltage on HVDD vs ILOAD

Analog Integrated Circuit Device Data Freescale Semiconductor 15 908E625 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 908E625 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E625 is well suited to perform complete mirror, door lock, and light-levelling control all via a three-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS ™ IC chip. The SMARTMOS™ IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS™ IC configured as half-bridge outputs with one high-side switch. Other ports are also provided; they include Hall-effect sensor input ports, analog input ports, and a selectable HVDD terminal. An internal voltage regulator is provided on the SMARTMOS™ IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1 for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on Figure 3 for a depiction of the terminal locations on the package. PORT A I/O TERMINALS (PTA0:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals, KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/ SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PORT B I/O TERMINALS (PTB1, PTB3:7) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, V SUP, etc. The PTB2/AD2 terminal is not accessible in this device. For details refer to the 68HC908EY16 datasheet. PORT C I/O TERMINALS (PTC2:4) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet. PORT D I/O TERMINALS (PTD0:1) PTD1/TACH1 and PTD0/TACH0/BEMF are special- function, bidirectional I/O port terminals that can also be programmed to be timer terminals. In step motor applications the PTD0 terminal should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 terminal is recommended for use as an output terminal for generating the FGEN signal (PWM signal) if required by the application. PORT E I/O TERMINAL (PTE1) PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pull-up resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET TERMINAL (RST) A Logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pull-up resistor that is always activated, even when the reset terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet.

Analog Integrated Circuit Device Data

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FUNCTIONAL TERMINAL DESCRIPTION CURRENT LIMITATION FREQUENCY INPUT TERMINAL (FGEN) Input terminal for the half-bridge current limitation and the high-side inrush current limiter PWM frequency. This input is not a real PWM input terminal; it should just supply the period of the PWM. The duty cycle will be generate automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. BACK ELECTROMAGNETIC FORCE OUTPUT TERMINAL (BEMF) This terminal gives the user information about back electromagnetic force (BEMF). This feature is mainly used in step motor applications for detecting a stalled motor. In order to evaluate this signal the terminal must be directly connected to terminal PTD0/TACH0/BEMF. RESET TERMINAL (RST_A) RST_A is the bidirectional reset terminal of the analog die. It is an open drain with pull-up resistor and must be connected to the RST terminal of the MCU. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pull-up resistor and must be connected to the IRQ terminal of the MCU. SLAVE SELECT TERMINAL (SS) This terminal is the SPI Slave Select terminal for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I/O of the microcontroller. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. HALF-BRIDGE OUTPUT TERMINALS (HB1:HB4) The 908E625 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1:HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs. POWER SUPPLY TERMINALS (VSUP1:VSUP3) VSUP1:VSUP3 are device power supply terminals. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple VSUP terminals are provided. All VSUP terminals must be connected to get full chip functionality. POWER GROUND TERMINALS (GND1 AND GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple terminals are provided. GND1 and GND2 terminals must be connected to get full chip functionality. HIGH-SIDE OUTPUT TERMINAL (HS) The HS output terminal is a low RDS(ON) high-side switch. The switch is protected against overtemperature and overcurrent. The output is capable of limiting the inrush current with an automatic PWM generation using the FGEN module. SWITCHABLE VDD OUTPUT TERMINAL (HVDD) The HVDD terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. The output is short-circuit protected. HALL-EFFECT SENSOR INPUT TERMINALS (H1:H3) The Hall-effect sensor input terminals H1:H3 provide inputs for Hall-effect sensors and switches. +5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. Important The VDD terminal should not be used to supply other loads; use the HVDD terminal for this purpose. The VDD, EVDD, VDDA, and VREFH terminals must be connected together. ANALOG INPUT TERMINAL (PA1) This terminal is an analog input port with selectable current source values. VOLTAGE REGULATOR GROUND TERMINAL (VSS) The VSS terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL terminals must be connected together.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 908E625 FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD terminal). ADC REFERENCE TERMINALS (VREFL AND VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. ADC SUPPLY TERMINALS (VDDA AND VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals. The MCU operates from a single power supply. Fast signal transitions on MCU terminals place high, short- duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. TEST TERMINAL (FLSVPP) This terminal is for test purposes only. This terminal should be either left open (not connected) or connected to GND. EXPOSED PAD TERMINAL The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential.

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTERRUPTS The 908E625 has seven different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. LOW-VOLTAGE INTERRUPT The Low-Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. HIGH-VOLTAGE INTERRUPT The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. HIGH-TEMPERATURE INTERRUPT The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the High- Temperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. AUTONOMOUS WATCHDOG INTERRUPT (AWD) Refer to Autonomous Watchdog Autonomous Watchdog (AWD). LIN INTERRUPT If the LINIE bit is set, a falling edge on the LIN terminal will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up. HALL-EFFECT SENSOR INPUT TERMINAL INTERRUPT If the PHIE bit is set, the enabled Hall-Effect Sensor input terminals H1:H3 can generate an interrupt if a current above the threshold is detected. During STOP mode this interrupt, combined with the cyclic wake-up feature of the AWD, can wake up the system. Refer to terminal Hall-Effect Sensor Input Terminals (H1:H3). OVERCURRENT INTERRUPT If an overcurrent condition on a half-bridge occurs, the high-side or the HVDD output is detected and the OCIE bit is set and an interrupt generated. SYSTEM WAKE-UP System wake-up can be initiated by any of four events: • A falling edge on the LIN terminal • A wake-up signal from the AWD • A Logic [1] at Hall-effect sensor input terminal during cyclic check via AWD • An LVR condition If one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake-up the microcontroller as well as the main voltage regulator (MREG) (Figure 8

Figure 8. STOP Mode/Wake-Up Procedure

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microcontroller and the 908E625. A complete data transfer via the SPI consists of 2 bytes. and data of the selected address. Figure 9. SPI Protocol clock edges are present in the active phase of SS. is transferred. SS HIGH forces MISO to high impedance. Contains the address of the desired register. Contains information about a read or a write operation. information, slave just transmits back register data. The parity bit is only evaluated during a write operation.

Table 6. List of Registers

0 HPIE LINIE HTIE LVIE HVIE OCIE

0 HPF LINF HTF LVF HVF

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HPF by writing a Logic [1] to HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has no effect. clears the LINF bit. Writing a Logic [0] to LINF has no effect. This read/write flag is set on a high-temperature condition. clears the HTF bit. Writing a Logic [0] to HTF has no effect. to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a Logic [0] to LVF has no effect. This read/write flag is set on a high-voltage condition. clears the HVF bit. Writing a Logic [0] to HVF has no effect. This read-only flag is set on an overcurrent condition. to the appropriate overcurrent flag in the SYSSTAT Register. Figure 10. Principal Implementation for OCF

Analog Integrated Circuit Device Data Freescale Semiconductor 23 908E625 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS INTERRUPT MASK REGISTER (IMR) Hall-Effect Sensor Input Terminal Interrupt Enable Bit (HPIE) This read/write bit enables CPU interrupts by the Hall- effect sensor input terminal flag, HPF. Reset clears the HPIE bit. • 1 = Interrupt requests from HPF flag enabled • 0 = Interrupt requests from HPF flag disabled LIN Line Interrupt Enable Bit (LINIE) This read/write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit. • 1 = Interrupt requests from LINF flag enabled • 0 = Interrupt requests from LINF flag disabled High-Temperature Interrupt Enable Bit (HTIE) This read/ write bit enables CPU interrupts by the high- temperature flag, HTF. Reset clears the HTIE bit. • 1 = Interrupt requests from HTF flag enabled • 0 = Interrupt requests from HTF flag disabled Low-Voltage Interrupt Enable Bit (LVIE) This read/write bit enables CPU interrupts by the low- voltage flag, LVF. Reset clears the LVIE bit. • 1 = Interrupt requests from LVF flag enabled • 0 = Interrupt requests from LVF flag disabled High-Voltage Interrupt Enable Bit (HVIE) This read/write bit enables CPU interrupts by the high- voltage flag, HVF. Reset clears the HVIE bit. • 1 = Interrupt requests from HVF flag enabled • 0 = Interrupt requests from HVF flag disabled Overcurrent Interrupt Enable Bit (OCIE) This read/write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit. • 1 = Interrupt requests from OCF flag enabled • 0 = Interrupt requests from OCF flag disabled Register Name and Address: IMR - $04 Bits 7 6 5 4 3 2 1 0 Read

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external reset source, as explained in the paragraphs below. Figure 11 depicts the internal reset sources. reset the high-temperature reset is disabled. Figure 11. Internal Reset Routing

Analog Integrated Circuit Device Data Freescale Semiconductor 25 908E625 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS RESET EXTERNAL SOURCE External Reset Terminal The microcontroller has the capability of resetting the SMARTMOS™ device by pulling down the RST terminal. RESET MASK REGISTER (RMR) High-Temperature Reset Test (TTEST) This read/write bit is for te st purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the HTRE bit. • 1 = Low-temperature threshold enabled • 0 = Low-temperature threshold disabled High-Voltage Reset Enable Bit (HVRE) This read/write bit enables resets on high-voltage conditions. Reset clears the HVRE bit. • 1 = High-voltage reset enabled • 0 = High-voltage reset disabled High-Temperature Reset Enable Bit (HTRE) This read/write bit enables resets on high-temperature conditions. Reset clears the HTRE bit. • 1 = High-temperature reset enabled • 0 = High-temperature reset disabled Register Name and Address: RMR - $06 Bits 7 6 5 4 3 2 1 0 Read TTEST 0 0 0 0 0 HVRE HTRE Write Reset 0 0 0 0 0 0 0 0

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS ANALOG DIE I/OS LIN Physical Layer The LIN bus terminal provides a physical layer for single- wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull- up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. TXD TERMINAL The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure 1). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD terminal has an internal pull-up current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD TERMINAL The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP MODE/WAKE-UP FEATURE During STOP mode operation the transmitter of the physical layer is disabled. The receiver terminal is still active and able to detect wake-up events on the LIN bus line. If LIN interrupt is enabled (LINIE bit in the Interrupt Mask Register is set), a falling edge on the LIN line causes an interrupt. This interrupt switches on the main voltage regulator and generates a system wake-up. Analog Multiplexer/ADOUT Terminal The ADOUT terminal is the analog output interface to the ADC of the MCU. See Figure 12 . An analog multiplexer is used to read seven internal diagnostic analog voltages. Current Recopy The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V/2.5 A or 5.0 V/500 mA, respectively. Refer to Half- Bridge Current Recopy.) Analog Input PA1 The analog input PA1 is directly connected to the analog multiplexer, permitting analog values from the periphery to be read. TEMPERATURE SENSOR The 908E625 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP PRESCALER The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP/RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. ANALOG MULTIPLEXER CONFIGURATION REGISTER (ADMUX) SS3, SS2, SS1, and SS0—A/D Input Select Bits These read/write bits select the input to the ADC in the microcontroller according to Table 7. Reset clears SS3, SS2, SS1, and SS0 bits. Register Name and Address: ADMUX - $07 Bits 7 6 5 4 3 2 1 0 Read 0 0 0 0 SS3 SS2 SS1 SS0 Write Reset 0 0 0 0 0 0 0 0

potentiometers or resistor values, etc. multiple switches on one input. Output Register (POUT) is set. Figure 12. Analog Input PA1 and Multiplexer Table 7. Analog Multiplexer Configuration Register Table 8. PA1 Current Source Level Selection Bits

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These read/write bits select the current source values. Reset clears the CSSEL0:CSSEL1 bits. This read/write bit enables the current source for PA1. Reset clears the CSEN bit (Table 9). PSON bit in the System Control Register. Input Terminal Status Register (HASTAT). The flag is set if the sensed current is higher than IHSCT.

  1. This bit must always be set to 0.

Table 9. PA1 Current Source Enable Bit

0 Current Source Off

1 Current Source On

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Figure 15. Hall-Effect Sensor Input Terminal Connected to Three-Terminal Hall-Effect Sensor the operating mode, RUN or Stop. flag should be cleared in order to prevent a wrong interrupt. disabled independent of the state of the HxEN flags. wake-up feature of the AWD (Autonomous Watchdog). wakes up the MCU and starts the main voltage regulator.

Figure 16. Hall-Effect Sensor Input Terminal Cyclic Check Wake-Up Feature terminals. Reset clears the H3EN:H1EN bits.

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high-side, or low-side configurations. Figure 17. Half-Bridge Push-Pull Output Driver high-side MOSFET has a higher priority. the high-side MOSFET did not fall below a certain threshold. These read/write bits turn on the low-side MOSFETs. Reset clears the HBx_L bits.

These read/write bits turn on the high-side MOSFETs. Reset clears the HBx_H bits. Figure 18. Half-Bridge Current Limitation

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Figure 19. Offset Chopping for Step Motor Control and switched to the analog multiplexer. selected via bit CSA in the System Control Register. BEMF output as long as a recirculation current is detected.

Figure 20. BEMF Signal Generation HB_OCF in the System Status Register (SYSSTAT) is set. System Status Register or by reset.

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of the H-Bridges. Reset clears the CSA bit. • 1 = Current sense amplification set for measuring 0.5 A. • 0 = Current sense amplification set for measuring 2.5 A. according to Table 10. Reset clears the CLS2:CLS0 bits. overcurrent protection circuitry is used to limit the current. switch circuitry and connection to external lamp. flags (LVF, HVF) is set, the output is disabled. Figure 21. High-Side Circuitry Table 10. H-Bridge Current Limitation Value Selection

the part generates a reset and disables all power outputs. automatically switches off and the overcurrent flag is set. Figure 22. Inrush Current Limiter on High-Side Output conditions (LVI/HVI) have no influence on this circuitry. temperature reset is enabled. the System Status Register is set.

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and HVDD output). Reset clears the PSON bit. • 0 = Power stages disabled. HS_OCF bit. Writing a Logic [0] to HS_OCF has no effect. HB_OCF bit. Writing a Logic [0] to HB_OCF has no effect. Table 11. LIN Slew Rate Selection Bits

Analog Integrated Circuit Device Data Freescale Semiconductor 39 908E625 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Overtemperature Status Bit (HTF) This read-only bit is a copy of the HTF bit in the Interrupt Flag Register. • 1 = Overtemperature condition has occurred • 0 = No overtemperature condition has occurred AUTONOMOUS WATCHDOG (AWD) The Autonomous Watchdog module consists of three functions: • Watchdog function for the CPU in RUN mode • Periodic interrupt function in STOP mode • Cyclic wake-up function in STOP mode The AWD is enabled if AWDIE, AWDRE, or AWDCC in the AWDCTL Register is set. If these bits are cleared, the AWD oscillator is disabled and the watchdog switched off. WATCHDOG The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. PERIODIC INTERRUPT Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. CYCLIC WAKE-UP The cyclic wake-up feature is only available in STOP mode. If this feature is enabled, the selected Hall-effect sensor input terminals are switched on and sensed. If a “1” is detected on one of these inputs and the interrupt for the Hall- effect sensors is enabled, a system wake-up is performed. (Switch on main voltage regulator and assert IRQ_A to the microcontroller). AUTONOMOUS WATCHDOG CONTROL REGISTER (AWDCTL) Autonomous Watchdog Reset Bit (AWDRST) This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. • 1 = Reset AWD and restart timeout period • 0 = No effect Autonomous Watchdog Reset Enable Bit (AWDRE) This read/write bit enables resets on AWD time-outs. A reset on the RST_A is only asserted when the device is in RUN mode. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. • 1 = Autonomous watchdog enabled • 0 = Autonomous watchdog disabled Autonomous Watchdog Interrupt Enable Bit (AWDIE) This read/write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit. • 1 = CPU interrupt requests from AWDF enabled • 0 = CPU interrupt requests from AWDF disabled Autonomous Watchdog Cyclic Check (AWDCC) This read/write bit enables the cyclic check of the two- terminal Hall-effect sensor and the analog inputs. Reset clears the AWDCC bit. • 1 = Cyclic check of the Hall-effect sensor and analog port • 0 = No cyclic check of the Hall-effect sensor and analog port Autonomous Watchdog Timeout Flag Bit (AWDF) This read/write flag is set when the Autonomous Watchdog has timed out. Clear AWDF by writing a Logic [1] to AWDF. Clearing AWDF also resets the AWD counter and starts a new timeout period. Reset clears the AWDF bit. Writing a Logic [0] to AWDF has no effect. • 1 = AWD has timed out • 0 = AWD has not yet timed out Register Name and Address: AWDCTL - $0a Bits 7 6 5 4 3 2 1 0 Read 00 0 AWDR E AWDI E AWDC C AWDF AWD RWrite AWDRS T Reset 00 0 0 0 0 0 0

Analog Integrated Circuit Device Data

40 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION FACTORY TRIMMING AND CALIBRATION Autonomous Watchdog Rate Bit (AWDR) This read/write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. • 1 = Fast rate selected (10 ms) • 0 = Slow rate selected (20 ms) VOLTAGE REGULATOR The 908E625 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. RUN Mode During RUN mode the main voltage regulator is on. It provides a regulated supply to all digital sections. STOP Mode During STOP mode the STOP mode regulator supplies a regulated output voltage. The STOP mode regulator has a very limited output current capability. The output voltage will be lower than the output voltage of the main voltage regulator. FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E625, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the empty (0xFF) state: • 0xFD80:0xFDDF Trim and Calibration Values • 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values Below the usage of the trim values located in the flash memory is explained Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate this dependancies a ICG trim values is located at adress $FDC2. After trimming the ICG is a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) V DD = 5V, TAmbient~25°C) and will vary over temperature and voltage (VDD) as indicated in the 68HC908EY16 datasheet. To trim the ICG this values has to be copied to the ICG Trim Register ICGTR at adress $38 of the MCU. Important The value has to copied after every reset.

section development support. soldered onto the pcb board. and analog die have to be separated (e.g. datasheet - section development support. Figure 23. Normal Monitor Mode Circuit (MCU only) Vsup (12V) instead as descibted in Figure 24, page 42.

42 Freescale Semiconductor

Figure 24. Normal Monitor Mode Circuit Table 12. Monitor Mode Signal Requirements and Options

  1. PTA0 must have a pullup resistor to V DD in monitor mode
  2. External clock is a 4.9152MHz, 9.8304M Hz or 19.6608MHz canned oscillator on OCS1
  3. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
  4. V TST is a high voltage VDD +3 . 5 V ≤ VTST ≤ VDD +4 . 5 V

44 Freescale Semiconductor

Figure 26. PCB Layout Recommendations Table 13. Component Value Recommendation should be connected right at the C3. C5 180pF, SMD Ceramic, Low ESR Close (<5mm) to LIN terminal. Total Capacitance on LIN has to be below 220pF.

  1. Freescale does not assume liability, endorse , or want components from external manufactures that are referenced in circuit drawings
  2. Components are recommended to improve EMC and ESD performance.

Analog Integrated Circuit Device Data Freescale Semiconductor 45 908E625 TYPICAL APPLICATIONS PACKAGING DIMENSIONS PACKAGING DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL105910. DWB SUFFIX 54-TERMINAL PLASTIC PACKAGE 98ARL105910 ISSUE B NOTES: DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF HTE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM. EXACT SHAPE OF EACH CORNER IS OPTIONAL. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTOM OF THE PLASTIC BODY. 17.8 7.4 27 28 B C7.6 18.0 10.3 5.15

0.3 A B C

0.10 A 2.35 SEATING PLANE 0.65 A 54X 52X 2.65 0.9 SECTION B-B R0.08 MIN 0.1 0.0 0.50˚ 0.25 GAUGE PLANE MIN (1.43) A A CC (0.29) 0.38 0.30 (0.25) PLATING BASE METAL SECTION A-A ROTATED 90˚ CLOCKWISE 0.25 0.22 M0.13 CAB 10.9 9.7

0.30 CAB

5.3 4.8

46 Freescale Semiconductor

electrical, application and packaging information is provided in the data sheet. temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. RθJ21 and RθJ22, respectively. Figure 27. Thermal Land Pattern for Direct Thermal Table 14. Thermal Performance Comparison

  1. Per JEDEC JESD51-2 at natural convection, still air
  2. 2s2p thermal test board per JEDEC JESD51-7and
  3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

  1. Single layer thermal test board per JEDEC JESD51-3 and
  2. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

Figure 28. Thermal Test Board where the junction temperature is sensed. Table 15. Thermal Resistance Performance

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