MM908E625 MOTOROLA | Alldatasheet
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High-Performance M68HC08EY16 Core 16 K Bytes of On-Chip Flash Memory 512 Bytes of RAM Internal Clock Generation Module Two 16-Bit, 2-Channel Timers 10-Bit Analog-to-Digital Converter Three 2-Terminal Hall-Effect Sensor Input Ports One Analog Input with Switchable Current Source Four Low R DS(ON) Half-Bridge Outputs One Low R DS(ON) High-Side Output 13 Microcontroller I/Os DWB SUFFIX CASE 1400-01 54-TERMINAL SOICWB-EP
ORDERING INFORMATION
Range (TA) Package MM908E625ACDWB/R2 -40°C to 85°C 54 SOIC WB-EP 908E625 Simplified Application Diagram Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Figure 1. 908E625 Simplified Internal Block Diagram
64 Bytes
36 Bytes
24 Internal System
10 Bit Analog-to-
Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS PA1 VDD HVDD NC HB4 VSUP3 GND2 HB3 HS FLSVPP PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF RST_A IRQ_A SS LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2 Exposed Pad Transparent Top View of Package TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section beginning on page 15. Die Terminal Terminal Name Formal Name Definition MCU 1 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 Port B I/Os These terminals are special-functi on, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 3 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK Port C I/Os These terminals are special-functi on, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 9 IRQ External Interrupt Input This terminal is an asynchronous external interrupt input terminal. MCU 10 RST External Reset This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. MCU 12 PTD0/TACH0/BEMF PTD1/TACH1 Port D I/Os These terminals are special-functi on, bidirectional I/O port terminals that are shared with other functional modules in the MCU. 14, 21, 22, NC No Connect Not connected. MCU 42 PTE1/RXD Port E I/O This terminal is a special- function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. MCU 43 VREFL VREFH ADC References These terminals are the refe rence voltage terminals for the analog-to- digital converter (ADC). MCU 44 VSSA VDDA ADC Supply Terminals These terminals are the power supply terminals for the analog-to-digital converter. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA MCU 45 EVSS EVDD MCU Power Supply Terminals These terminals are the ground and power supply terminals, respectively. The MCU operates from a single power supply. MCU 49 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 Port A I/Os These terminals are special-func tion, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 51 FLSVPP Test Terminal For test purposes only. Do not connect in the application. Analog 15 FGEN Current Limitation Frequency Input This is the input terminal for the half-bridge current limitation and the high- side inrush current limiter PWM frequency. Analog 16 BEMF Back Electromagnetic Force Output This terminal gives the user information about back electromagnetic force (BEMF). Analog 17 RST_A Internal Reset This terminal is the bidirectional reset terminal of the analog die. Analog 18 IRQ_A Internal Interrupt Output This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. Analog 19 SS Slave Select This terminal is the SPI sl ave select terminal for the analog chip. Analog 20 LIN LIN Bus This terminal represents the single-wire bus transmitter and receiver. Analog 23 HB1 HB2 HB3 HB4 Half-Bridge Outputs This device includes power MOSFETs configured as four half-bridge driver outputs. These outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. Analog 24 VSUP1 VSUP2 VSUP3 Power Supply Terminals These terminals are device power supply terminals. Analog 25 GND1 GND2 Power Ground Terminals These terminals are device power ground connections. Analog 28 HS High-Side Output This output terminal is a low R DS(ON) high-side switch. Analog 34 HVDD Switchable V DD Output This terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. Analog 35 Hall-Effect Sensor Inputs These terminals provide inputs for Hall-effect sensors and switches. Analog 38 VDD Voltage Regulator Output The +5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. Analog 39 PA1 Analog Input This terminal is an analog input port with selectable source values. Analog 40 VSS Voltage Regulator Ground Ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Analog 41 RXD LIN Transceiver Output This terminal is the output of LIN transceiver. EP Exposed Pad Exposed Pad The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. TERMINAL DEFINITIONS (continued) A functional description of each terminal can be found in the System/Application Information section beginning on page 15. Die Terminal Terminal Name Formal Name Definition Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Unit ELECTRICAL RATINGS Supply Voltage Analog Chip Supply Voltage under Normal Operation (Steady-State) Analog Chip Supply Voltage under Transient Conditions (Note 1) Microcontroller Chip Supply Voltage VSUP(SS) VSUP(PK) VDD -0.3 to 28 -0.3 to 40 -0.3 to 6.0 V Input Terminal Voltage Analog Chip Microcontroller Chip VIN(ANALOG) VIN(MCU) -0.3 to 5.5 VSS-0.3 to VDD+0.3 V Maximum Microcontroller Current per Terminal All Terminals Except VDD, VSS, PTA0:PTA6, PTC0:PTC1 Terminals PTA0:PTA6, PTC0:PTC1 IPIN(1) IPIN(2) ±15 ±25 mA Maximum Microcontroller VSS Output Current I MVSS 100 mA Maximum Microcontroller VDD Input Current I MVDD 100 mA LIN Supply Voltage Normal Operation (Steady-State) Transient Conditions (Note 1) VBUS(SS) VBUS(DYNAMIC) -18 to 28 V ESD Voltage Human Body Model (Note 2) Machine Model (Note 3) Charge Device Model (Note 4) VESD1 VESD2 VESD3 ±3000 ±150 ±500 V THERMAL RATINGS Storage Temperature T STG -40 to 150 °C Operating Case Temperature (Note 5) T C -40 to 85 °C Operating Junction Temperature Analog MCU TJ(ANALOG) TJ(MCU) -40 to 150 -40 to 125 Terminal Soldering Temperature (Note 6) T SOLDER 245 °C Thermal Resistance (Junction to Ambient) All Outputs ON (Note 7), (Note 9) Single Output ON (Note 8), (Note 9) RθJA1 RθJA2 °C/W Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω). 3. ESD2 testing is performed in ac cordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω). 4. ESD3 testing is performed in accordanc e with Charge Device Model, robotic (CZAP =4.0 pF). 5. The limiting factor is junction temperat ure, taking into account the power dissipation, thermal resistance, and heat sinking. 6. Terminal soldering temperature is for 10 seconds maximum durat ion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. All outputs ON and dissipating equal power. 8. One output ON and dissipating power. 9. Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7 and JESD51-5 (thermal vias connected to top ground plane). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA STATIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit SUPPLY VOLTAGE Nominal Operating Voltage V SUP 8.0 18 V SUPPLY CURRENT NORMAL Mode VSUP = 12 V, Power Die ON (PSON=1), MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled STOP Mode (Note 10) VSUP = 12 V, Cyclic Wake-Up Disabled IRUN ISTOP mA µA DIGITAL INTERFACE RATINGS (ANALOG DIE) Output Terminals RST_A, IRQ_A Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Voltage (IOUT = 1.0 µA) VOL VOH 3.85 0.4 V Output Terminals BEMF, RXD Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Voltage (IOUT = 1.5 mA) VOL VOH 3.85 0.4 V Output Terminal RXDCapacitance (Note 11) C IN 4 . 0 p F Input Terminals RST_A, FGEN, SS Input Logic Low Voltage Input Logic High Voltage VIL VIH 3.5 1.5 V Input Terminals RST_A, FGEN, SSCapacitance (Note 11) C IN 4 . 0 p F Terminals RST_A, IRQ_APullup Resistor R PULLUP1 1 0 k Ω Terminal SSPullup Resistor R PULLUP2 6 0 k Ω Terminals FGEN, MOSI, SPSCKPulldown Resistor R PULLDOWN 6 0 k Ω Terminal TXDPullup Current Source I PULLUP 3 5 µA Notes 10. STOP mode current will increase if V SUP exceeds 15 V. 11. This parameter is guaranteed by process monitoring but is not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 SYSTEM RESETS AND INTERRUPTS High-Voltage Reset Threshold Hysteresis VHVRON VHVRH 1.5 V Low-Voltage Reset Threshold Hysteresis VLVRON VLVRH 3.6 4.0 100 4.5 V mV High-Voltage Interrupt Threshold Hysteresis VHVION VHVIH 17.5 1.0 V Low-Voltage Interrupt Threshold Hysteresis VLVION VLVIH 6.5 0.4 8.0 V High-Temperature Reset (Note 12) Threshold Hysteresis T RON TRH 5.0 170 High-Temperature Interrupt (Note 13) Threshold Hysteresis TION TIH 5.0 160 VOLTAGE REGULATOR Normal Mode Output Voltage IOUT = 60 mA, 6.0 V < VSUP < 18 V VDDRUN 4.75 5.0 5.25 V Load Regulation IOUT = 80 mA, VSUP = 9.0 V, TJ = 125°C VLR 100 mV STOP Mode Output Voltage (Maximum Output Current 100 µA) V DDSTOP 4.5 4.7 4.9 V Notes 12. This parameter is guaranteed by process monitoring but is not production tested. 13. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C). STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA LIN PHYSICAL LAYER Output Low Level TXD LOW, 500 Ω Pullup to VSUP VLIN-LOW 1 . 4 V Output High Level TXD HIGH, IOUT = 1.0 µA VLIN-HIGH VSUP -1.0 V Pullup Resistor to VSUP RSLAVE 20 30 60 k Ω Leakage Current to GND Recessive State (-0.5 V < VLIN < VSUP) IBUS_PAS_rec 0 2 0 µA Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18 V Including Internal Pullup Resistor, VLIN @ +18 V IBUS_NO_GND IBUS -600 µA LIN Receiver Recessive Dominant Threshold Input Hysteresis V IH VIL VITH VIHY
0.6 VLIN
0.01 VSUP
V SUP/2 VSUP
0.4 VLIN
0.1 VSUP
V LIN Wake-Up Threshold V WTH V SUP/2 V HIGH-SIDE OUTPUT (HS) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A RDS(ON)HS 600 700 m Ω High-Side Overcurrent Shutdown I HSOC 3.9 7.0 A STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 HALF-BRIDGE OUTPUTS (H1:H4) Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A High Side Low Side RDS(ON)HB_HS RDS(ON)HB_LS 425 400 500 500 mΩ High-Side Overcurrent Shutdown IHBHSOC 4.0 7.5 A Low-Side Overcurrent Shutdown IHBLSOC 3.5 7.5 A Low-Side Current Limitation @ TJ = 25°C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) I CL1 ICL2 ICL3 ICL4 ICL5 210 300 450 600 260 370 550 740 315 440 650 880 mA Half-Bridge Output HIGH Threshold for BEMF Detection V BEMFH - 3 00 V Half-Bridge Output LOW Threshold for BEMF Detection V BEMFL - 6 0 - 5 . 0 m V Hysteresis for BEMF Detection V BEMFHY 3 0 m V Low-Side Current-to-Voltage Ratio (VADOUT [V]/I HB [A]) CSA = 1 CSA = 0 RATIOH RATIOL 7.0 1.0 12.0 2.0 14.0 3.0 V/A SWITCHABLE VDD OUTPUT (HVDD) Overcurrent Shutdown Threshold I HVDDOCT 24 30 40 mA VSUP DOWN-SCALER Voltage Ratio (RATIOVSUP = VSUP /VADOUT)R A T I O VSUP 4.8 5.1 5.35 INTERNAL DIE TEMPERATURE SENSOR Voltage/Temperature Slope S TtoV 1 9 m V / ° C Output Voltage @ 25°C V T25 1.7 2.1 2.5 V HALL-EFFECT SENSOR INPUTS (H1:H3) Output Voltage VSUP < 16.2 V VSUP > 16.2 V VHALL1 VHALL2 VSUP-1.2 V Sense Current Threshold Hysteresis IHSCT IHSCH 6.9 8.8 0.88 mA Output Current Limitation IHL 9 0 m A Overcurrent Warning HP_OCF Flag Threshold] V HPOCT 3 . 0 V Dropout Voltage @ ILOAD = 15 mA V HPDO 0 . 5 V STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA ANALOG INPUT (PA1) Current Source PA1 CSSEL1 = 1, CSSEL0 = 1 ICSPA1 570 670 770 µA Selectable Scaling Factor Current Source PA1 (I(N) = ICSPA1* N) CSSEL1 = 0, CSSEL0 = 0 CSSEL1 = 0, CSSEL0 = 1 CSSEL1 = 1, CSSEL0 = 0 N CSPA1-0 NCSPA1-1 NCSPA1-2 8.5 28.5 58.5 11.5 31.5 61.5 STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 DYNAMIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER Propagation Delay (Note 14), (Note 15) TXD LOW to LIN LOW TXD HIGH to LIN HIGH LIN LOW to RXD LOW LIN HIGH to RXD HIGH TXD Symmetry RXD Symmetry t TXD-LIN-low tTXD-LIN-high tLIN-RXD-low tLIN-RXD-high tTXD-SYM tRXD-SYM -2.0 -2.0 4.0 4.0 6.0 6.0 8.0 8.0 2.0 2.0 µs Output Falling Edge Slew Rate (Note 14), (Note 16) 80% to 20% SR F -1.0 -2.0 -3.0 V/µs Output Rising Edge Slew Rate (Note 14), (Note 16) 20% to 80%, RBUS > 1.0 kΩ, CBUS < 10 nF SRR 1.0 2.0 3.0 V/µs LIN Rise/Fall Slew Rate Symmetry (Note 14), (Note 16) SR S -2.0 2.0 µs HALL-EFFECT SENSOR INPUTS (H1:H3) Propagation Delay t HPPD 1 . 0 µs AUTONOMOUS WATCHDOG (AWD) AWD Oscillator Period t OSC 4 0 µs AWD Period Low = 512 tOSC tAWDPH 16 22 28 ms AWD Period High = 256 t OSC tAWDPL 8.0 11 14 ms AWD Cyclic Wake-Up On Time t AWDHPON 9 0 µs Notes 14. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00). 15. See Figure 2, page 11. 16. See Figure 3, page 11. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA MICROCONTROLLER For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet. Module Description Core High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Timer Two 16-Bit Timers with Two Channels (TIM A and TIM B) Flash 16 K Bytes RAM 512 Bytes ADC 10-Bit Analog-to-Digital Converter SPI SPI Module ESCI Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment ICG Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%) BEMF Counter Special Counter for SMARTMOS BEMF Output Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Figure 2. LIN Timing Description Figure 3. LIN Slew Rate Description
0.9 VSUP
0.4 VSUP
0.6 VSUP
0.8 VSUP
0.2 VSUP
Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 SYSTEM/APPLICATION INFORMATION INTRODUCTION The 908E625 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E625 is well suited to perform complete mirror, door lock, and light-levelling control all via a 3-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS IC chip. The SMARTMOS IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS IC configured as half-bridge outputs with one high-side switch. Other ports are also provided; they include Hall-effect sensor input ports, analog input ports, and a selectable HVDD terminal. An internal voltage regulator is provided on the SMARTMOS IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1, 908E625 Simplified Internal Block Diagram, page 2, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. Port A I/O Terminals These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals, KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet. Port B I/O Terminals These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 terminal is not accessible in this device. For details refer to the 68HC908EY16 datasheet. Port C I/O Terminals These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet. Port D I/O Terminals PTD1/TACH1 and PTD0/TACH0/BEMF are special- function, bidirectional I/O port terminals that can also be programmed to be timer terminals. In step motor applications the PTD0 terminal should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 terminal is recommended for use as an output terminal for generating the FGEN signal (PWM signal) if required by the application. Port E I/O Terminal PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. External Interrupt Terminal (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. External Reset Terminal (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Current Limitation Frequency Input Terminal (FGEN) Input terminal for the half-bridge current limitation and the high-side inrush current limiter PWM frequency. This input is not a real PWM input terminal; it should just supply the period of the PWM. The duty cycle will be generate automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. Back Electromagnetic Force Output Terminal (BEMF) This terminal gives the user information about back electromagnetic force (BEMF). This feature is mainly used in step motor applications for detecting a stalled motor. In order to evaluate this signal the terminal must be directly connected to terminal PTD0/TACH0/BEMF. Reset Terminal (RST_A) RST_A is the bidirectional reset terminal of the analog die. It is an open drain with pullup resistor and must be connected to the RST terminal of the MCU. Interrupt Terminal (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pullup resistor and must be connected to the IRQ terminal of the MCU. Slave Select Terminal (SS) This terminal is the SPI Slave Select terminal for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I/O of the microcontroller. LIN Bus Terminal (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. Half-Bridge Output Terminals (HB1:HB4) The 908E625 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1:HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs. Power Supply Terminals (VSUP1:VSUP3) VSUP1:VSUP3 are device power supply terminals. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple VSUP terminals are provided. All VSUP terminals must be connected to get full chip functionality. Power Ground Terminals (GND1 and GND2) GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple terminals are provided. GND1 and GND2 terminals must be connected to get full chip functionality. High-Side Output Terminal (HS) The HS output terminal is a low RDS(ON) high-side switch. The switch is protected against overtemperature and overcurrent. The output is capable of limiting the inrush current with an automatic PWM generation using the FGEN module. Switchable VDD Output Terminal (HVDD) The HVDD terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. The output is short-circuit protected. Hall-Effect Sensor Input Terminals (H1:H3) The Hall-effect sensor input terminals H1:H3 provide inputs for Hall-effect sensors and switches. +5.0 V Voltage Regulator Output Terminal (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. Important The VDD terminal should not be used to supply other loads; use the HVDD terminal for this purpose. The VDD, EVDD, VDDA, and VREFH terminals must be connected together. Analog Input Terminal (PA1) This terminal is an analog input port with selectable current source values. Voltage Regulator Ground Terminal (VSS) The VSS terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VR EFL terminals must be connected together. LIN Transceiver Output Terminal (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontrollers Enhanced Serial Communications Interface (ESCI) module (RXD terminal). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 ADC Reference Terminals (VREFL and VREFH) VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet. ADC Supply Terminals (VDDA and VSSA) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. MCU Power Supply Terminals (EVDD and EVSS) EVDD and EVSS are the power supply and ground terminals. The MCU operates from a single power supply. Fast signal transitions on MCU terminals place high, short- duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. Test Terminal (FLSVPP) For test purposes only. Do not connect in the application. Exposed Pad Terminal The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential. ANALOG DIE DESCRIPTION Interrupts The 908E625 has seven different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. Low-Voltage Interrupt The Low-Voltage Interrupt (LVI) is related to the external supply voltage, V SUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. High-Voltage Interrupt The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. High-Temperature Interrupt The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the High- Temperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. Autonomous Watchdog Interrupt (AWD) Refer to Autonomous Watchdog (AWD) on page 36. LIN Interrupt If the LINIE bit is set, a falling edge on the LIN terminal will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up. Hall-Effect Sensor Input Terminal Interrupt If the PHIE bit is set, the enabled Hall-effect sensor input terminals H1:H3 can generate an interrupt if a current above the threshold is detected. During STOP mode this interrupt, combined with the cyclic wake-up feature of the AWD, can wake up the system (refer to Hall-Effect Sensor Input Terminals (H1:H3) on page 25). Overcurrent Interrupt If an overcurrent condition on a half-bridge occurs, the high- side or the HVDD output is detected and the OCIE bit is set and an interrupt generated. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
A falling edge on the LIN terminal. A wake-up signal from the AWD. Figure 6. STOP Mode/Wake-Up Procedure This read/write flag is set depending on RUN/STOP mode. the HPF bit. Writing a logic [0] to HPF has no effect. 1 = State change on the hallflags detected. 0 = No state change on the hallflags detected. terminals had been pulled HIGH. LINF bit. Writing a logic [0] to LINF has no effect. 1 = Falling edge on LIN data line has occurred. This read/write flag is set on a high-temperature condition. the HTF bit. Writing a logic [0] to HTF has no effect. 1 = High-temperature condition has occurred. 0 = High-temperature condition has not occurred.
0 HPF LINF HTF LVF HVF
Freescale Semiconductor, Inc.
present while writing a logic [1] to LVF, the writing has no effect. logic [0] to LVF has no effect. 1 = Low-voltage condition has occurred. 0 = Low-voltage condition has not occurred. present while writing a logic [1] to HVF, the writing has no effect. logic [0] to HVF has no effect. 1 = High-voltage condition has occurred. 0 = High-voltage condition has not occurred. Figure 7, which shows the three signals triggering the OCF. 1 = High-current condition has occurred. 0 = High-current condition has not occurred. Figure 7. Principal Implementation for OCF sensor input terminal flag, HPF. Reset clears the HPIE bit. 1 = Interrupt requests from HPF flag enabled. 0 = Interrupt requests from HPF flag disabled. LINF. Reset clears the LINIE bit. 1 = Interrupt requests from LINF flag enabled. 0 = Interrupt requests from LINF flag disabled. temperature flag, HTF. Reset clears the HTIE bit. 1 = Interrupt requests from HTF flag enabled. 0 = Interrupt requests from HTF flag disabled. voltage flag, LVF. Reset clears the LVIE bit. 1 = Interrupt requests from LVF flag enabled. 0 = Interrupt requests from LVF flag disabled. voltage flag, HVF. Reset clears the HVIE bit. 1 = Interrupt requests from HVF flag enabled. 0 = Interrupt requests from HVF flag disabled. flag, OCF. Reset clears the OCIE bit. 1 = Interrupt requests from OCF flag enabled. 0 = Interrupt requests from OCF flag disabled.
0 HPIE LINIE HTIE LVIE HVIE OCIE
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conditions. Reset clears the HVRE bit. 1 = High-voltage reset enabled. 0 = High-voltage reset disabled. conditions. Reset clears the HTRE bit. 1 = High-temperature reset enabled. 0 = High-temperature reset disabled. Figure 9. SPI Protocol a new data transfer and puts MISO in the low-impedance mode. The MISO output changes data on a rising edge of SPSCK. present in the active phase of SS. transferred. SS HIGH forces MISO to high impedance. Freescale Semiconductor, Inc.
Contains the address of the desired register. Contains information about a read or a write operation. information, slave just transmits back register data. latched in the SMARTMOS register on rising edge of SS. The parity bit is only evaluated during a write operation. Table 1. List of Registers Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 Analog Die I/Os LIN Physical Layer The LIN bus terminal provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. TXD Terminal The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure 1, page 2). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD terminal has an internal pullup current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD Terminal The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP Mode/Wake-Up Feature During STOP mode operation the transmitter of the physical layer is disabled. The receiver terminal is still active and able to detect wake-up events on the LIN bus line. If LIN interrupt is enabled (LINIE bit in the Interrupt Mask Register is set), a falling edge on the LIN line causes an interrupt. This interrupt switches on the main voltage regulator and generates a system wake-up. Analog Multiplexer/ADOUT Terminal The ADOUT terminal is the analog output interface to the ADC of the MCU (see Figure 1, page 2). An analog multiplexer is used to read seven internal diagnostic analog voltages. Current Recopy The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V/2.5 A or 5.0 V/500 mA, respectively. (Refer to Half-Bridge Current Recopy on page 31.) Analog Input PA1 The analog input PA1 is directly connected to the analog multiplexer, permitting analog values from the periphery to be read. Temperature Sensor The 908E625 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP Prescaler The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP/ RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. Analog Multiplexer Configuration Register (ADMUX) SS3, SS2, SS1, and SS0A/D Input Select Bits These read/write bits select the input to the ADC in the microcontroller according to Table 2, page 24. Reset clears SS3, SS2, SS1, and SS0 bits. Register Name and Address: ADMUX - $07 Bit7 6 5 4 3 2 1 Bit0 Read 0 0 0 0 SS3 SS2 SS1 SS0 Write Reset 0 0 0 0 0 0 0 0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Table 2. Analog Multiplexer Configuration Register Analog Input PA1 the need of an additional supply line for the sensor (Figure 10). Output Register (POUT) is set. Table 3. PA1 Current Source Level Selection Bits Figure 10. Analog Input PA1 and Multiplexer6 Freescale Semiconductor, Inc.
clears the CSSEL0:CSSEL1 bits. clears the CSEN bit (Table 4). Table 4. PA1 Current Source Enable Bit PSON bit in the System Control Register. Terminal Status Register (HASTAT). The flag is set if the sensed current is higher than IHSCT. the Hall-effect input sensors.
- This bit must always be set to 0.
0 Current Source Off
1 Current Source On
Freescale Semiconductor, Inc.
Figure 13. Hall-Effect Sensor Input Terminal Connected to Three-Terminal Hall-Effect Sensor The Hall-effect sensor input terminals are interrupt capable. operating mode, RUN or Stop. should be cleared in order to prevent a wrong interrupt. disabled independent of the state of the HxEN flags. wake-up feature of the AWD (autonomous watchdog). wakes up the MCU and starts the main voltage regulator. Freescale Semiconductor, Inc.
Figure 14. Hall-Effect Sensor Input Terminal Cyclic Check Wake-Up Feature terminals. Reset clears the H3EN:H1EN bits. 0 = Hall-effect sensor input terminal Hx disabled. Freescale Semiconductor, Inc.
side, or low-side configurations. Current recopy feat ure (low side MOSFET). Overtemperature protection. Overvoltage and undervoltage protection. Current limitation feature (low side MOSFET). Figure 15. Half-Bridge Push-Pull Output Driver side MOSFET has a higher priority. MOSFET did not fall below a certain threshold. 1 = Low-side MOSFET turned on for half-bridge output x. 0 = Low-side MOSFET turned off for half-bridge output x. Freescale Semiconductor, Inc.
1 = High-side MOSFET turned on for half-bridge output x. 0 = High-side MOSFET turned on for half-bridge output x. edge on the FGEN input was detected (Figure 16). Figure 16. Half-Bridge Current Limitation Freescale Semiconductor, Inc.
Figure 17. Offset Chopping for Step Motor Control switched to the analog multiplexer. via bit CSA in the System Control Register. Freescale Semiconductor, Inc.
Figure 18. BEMF Signal Generation the part generates a reset and disables all power outputs. HB_OCF in the System Status Register (SYSSTAT) is set. Status Register or by reset. HVF) is set, the outputs are automatically disabled. is useless as long as a high- or low-voltage condition is present. 1 = Offset chopping enabled. 0 = Offset chopping disabled. the H-Bridges. Reset clears the CSA bit. 1 = Current sense amplification set for measuring 0.5 A. 0 = Current sense amplification set for measuring 2.5 A. Freescale Semiconductor, Inc.
according to Table 5. Reset clears the CLS2:CLS0 bits. Table 5. H-Bridge Current Limitation Value Selection Bits connection to external lamp. flags (LVF, HVF) is set, the output is disabled. useless as long as a high- or low-voltage condition is present. Figure 19. High-Side Circuitry the part generates a reset and disables all power outputs. automatically switches off and the overcurrent flag is set. Status Register (see Figure 20, page 34). Freescale Semiconductor, Inc.
Figure 20. Inrush Current Limiter on High-Side Output (LVI/HVI) have no influence on this circuitry. temperature reset is enabled. System Status Register is set. and HVDD output). Reset clears the PSON bit. 0 = Power stages disabled. Freescale Semiconductor, Inc.
Table 6. LIN Slew Rate Selection Bits 1 = Power down and go into STOP mode. enable the output by writing a logic [1] to the HP_OCF flag. 1 = Transmitter operating in current limitation region. 0 = Transmitter not operating in current limitation region. HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect. 1 = Overcurrent condition on HVDD has occurred. 0 = No overcurrent condition on HVDD has occurred. by writing a logic [1] to HS_OCF. Reset clears the HS_OCF bit. Writing a logic [0] to HS_OCF has no effect. 1 = Low-voltage condition has occurred. 0 = No low-voltage condition has occurred. 1 = High-voltage condition has occurred. 0 = No high-voltage condition has occurred. writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a logic [0] to HB_OCF has no effect. 1 = Overcurrent condition on H-Bridges has occurred. 0 = No overcurrent conditio n on H-Bridges has occurred. 1 = Overtemperature condition has occurred. 0 = No overtemperature condition has occurred. Freescale Semiconductor, Inc.
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Autonomous Watchdog (AWD) The Autonomous Watchdog module consists of three functions: Watchdog function for the CPU in RUN mode Periodic interrupt function in STOP mode Cyclic wake-up function in STOP mode The AWD is enabled if AWDIE, AWDRE, or AWDCC in the AWDCTL Register is set. If these bits are cleared, the AWD oscillator is disabled and the watchdog switched off. Watchdog The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. Periodic Interrupt Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. Cyclic Wake-Up The cyclic wake-up feature is only available in STOP mode. If this feature is enabled, the selected Hall-effect sensor input terminals are switched on and sensed. If a 1 is detected on one of these inputs and the interrupt for the Hall-effect sensors is enabled, a system wake-up is performed. (Switch on main voltage regulator and assert IRQ_A to the microcontroller). Autonomous Watchdog Control Register (AWDCTL) AWDRSTAutonomous Watchdog Reset Bit This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. 1 = Reset AWD and restart timeout period. 0 = No effect. AWDREAutonomous Watchdog Reset Enable Bit This read/write bit enables resets on AWD timeouts. A reset on the RST_A is only asserted when the device is in RUN mode. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. 1 = Autonomous watchdog enabled. 0 = Autonomous watchdog disabled. AWDIEAutonomous Watchdog Interrupt Enable Bit This read/write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit. 1 = CPU interrupt requests from AWDF enabled. 0 = CPU interrupt requests from AWDF disabled. AWDCC Autonomous Watchdog Cyclic Check This read/write bit enables the cyclic check of the two- terminal Hall-effect sensor and the analog inputs. Reset clears the AWDCC bit. 1 = Cyclic check of the Hall -effect sensor and analog port. 0 = No cyclic check of the Hall-effect sensor and analog port. AWDFAutonomous Watchdog Timeout Flag Bit This read/write flag is set when the Autonomous Watchdog has timed out. Clear AWDF by writing a logic [1] to AWDF. Clearing AWDF also resets the AWD counter and starts a new timeout period. Reset clears the AWDF bit. Writing a logic [0] to AWDF has no effect. 1 = AWD has timed out. 0 = AWD has not yet timed out. AWDRAutonomous Watchdog Rate Bit This read/write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. 1 = Fast rate selected (10 ms). 0 = Slow rate selected (20 ms). Voltage Regulator The 908E625 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. Register Name and Address: AWDCTL - $0a Bit7 6 5 4 3 2 1 Bit0 Read 00 0 ADRE AWDIE AWDCC AWDF AWDR Write AWDRST Reset 00 0 0 0 0 0 0 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
908E625 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PACKAGE DIMENSIONS NOTES: DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF HTE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM. EXACT SHAPE OF EACH CORNER IS OPTIONAL. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTOM OF THE PLASTIC BODY. 17.8 7.4 27 28 B C7.6 18.0 10.3 5.15
0.3 A B C
0.10 A 2.35 SEATING PLANE 0.65 A 54X 52X 2.65 0.9 SECTION B-B R0.08 MIN 0.1 0.0 0.50˚ 0.25 GAUGE PLANE MIN (1.43) A A CC (0.29) 0.38 0.30 (0.25) PLATING BASE METAL SECTION A-A ROTATED 90˚ CLOCKWISE 0.25 0.22 M0.13 CAB 10.9 9.7
0.30 CAB
5.3 4.8 54-TERMINAL SOIC WIDE BODY EXPOSED PAD PLASTIC PACKAGE CASE 1400-01 ISSUE B Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 908E625 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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