MM908E622 FREESCALE | Alldatasheet
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Technical content
Features
High-Performance M68HC908EY16 Core 16 K Bytes of On-Chip Flash Memory, 512 Bytes of RAM Internal Clock Generator Module (ICG) Two 16-Bit, 2-Channel Timers 10-Bit Analog-to-Digital Converter (ADC) LIN Physical Layer Interface Autonomous MCU Watchdog / MCU Supervision One Analog Input with Switchable Current Source Four Low RDS(ON) Half-Bridge Outputs Three Low RDS(ON) High-Side Outputs EC glass driver circuitry Wake-Up Input One 2/3-Pin Hall-Effect Sensor Input 12 Microcontroller I/Os Figure 1. 908E622 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package MM908E622ACDWB/R2 -40°C to 85°C 54 SOICW-EP DWB SUFFIX 98ARL10519D 54-TERMINAL SOICW-EP RST_A RST IRQ_A IRQ VSSA/VREFL LIN VDDA/VREFH EVDD VDD EVSS VSS HS1 ECR VSUP[1:8] A0CST High Side Output 3 High Side Output 2 High Side Output 1 HS2 HS3 EC HVDD GND[1:4] EC - Glas Control Switched 5V output Analog Input with current source Analog Input current source trim 2-/3-pin hall sensor input Wake Up Input 4.7µF >2 2µF HB1 HB2 MM 4 x Half Bridge Outputs HB3 M HB4 PTC2/MCLK PTC3/OSC2 PTC4/OSC1 µC PortC PTB3/AD3 PTB4/AD4 PTB5/AD5 µC PortB PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 µC PortA PTE1/RxDInternally connectedµC PortE PTD0/TACH0µC PortD PTD1/TACH1 TESTMODE Pull to ground for user modeEP 1 00nF 1 00nF Internally connected 908E622
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10 Bit Analog-to-
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Figure 2. 908E622 Simplified Internal Block Diagram
Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 21. that are shared with other functional modules in the MCU. that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. driven low when any internal reset source is asserted. MCU PTD0/TACH0 terminal with the Analog die PWM input. Note: Do not connect in the application. shared with other functional modules in the MCU. transceiver output terminal RXD. Note: Do not connect in the application.
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for the analog-to-digital converter (ADC). respectively. The MCU operates from a single power supply. that are shared with other functional modules in the MCU. MCU 51 FLSVPP Test Terminal For test purposes only. Do not connect in the application. RST_A Internal Reset This terminal is the bidirectional reset terminal of the analog die. Analog 13 LIN LIN Bus This terminal represents the single-wire bus transmitter and receiver. Analog 15 A0 Analog Input Terminal This terminal is an analog input port with selectable source values. These terminals are device power ground connections. or as high-side and low-side switches. These terminals are device power supply terminals. connected to the external ballast resistor. These output terminals are low RDS(ON) high-side switches. Analog 40 L0 Wake-up Input This terminal provides an high voltage input, which is wake-up capable. Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 21.
requiring a regulated 5.0 V supply; e.g. potentiometers. (microcontroller and sensors). heat from the chip to the PCB board. A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 21.
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Table 2. Maximum Ratings
- Transient capability for pulses with a time of t < 0.5 sec.
- ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP =1 5 0 0Ω).
- ESD2 testing is performed in ac cordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω).
- ESD3 testing is performed in accordanc e with Charge Device Model, Robotic (CZAP =4 . 0p F ) .
- The limiting factor is junction temperat ure; taking into account the power dissipation, thermal resistance, and heat sinking.
- The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because
of higher power dissipation on the analog die. The analog die temperature must not exceed 150°C under these conditions.
- Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device. Table 2. Maximum Ratings (continued)
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Table 3. Static Electrical Characteristics noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
- Device is fully functional, but some of the parameters might be out of spec.
- Total current measured at GND terminals.
- Stop and Sleep mode current will increase if V SUP exceeds 15 V.
- This parameter is guaranteed by process monitoring but is not production tested.
- This parameter is guaranteed by process monitoring but is not production tested.
- Specification with external low ESR ceramic capacitor 1.0 µF< C < 4.7 µF and 200 mΩ≤ ESR ≤ 10 Ω. Its not recommended to use
- When switching from Normal to Stop mode or from Stop mode to No rmal mode, the output voltage can vary within the output voltage
Table 3. Static Electrical Characteristics (continued) noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
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noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
- This parameter is guaranteed by process monitoring but is not production tested.
- This parameter is guaranteed only if correct trimming was applied.
- The high-side HS3 can be only used for resistive loads.
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
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- This parameter is guaranteed by process monitoring but is not production tested.
- This parameter is guaranteed only if correct trimming was applied
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
- This parameter is guaranteed by process monitoring but is not production tested.
- This parameter is guaranteed only if correct trimming was applied
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
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- This parameter is guaranteed only if correct trimming was applied
- The current values are optimized to read a NTC temperature sensor, e.g. EPCOS type B57861 (R25 = 3000Ω, R/T characteristic 8016)
- This parameter is guaranteed by process monitoring but is not production tested.
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Table 4. Dynamic Electrical Characteristics microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. to LIN signal threshold defined at each parameter.
- Measured between LIN signal threshold V IL or VIH and 50% of RXD signal.
- t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 9 and Figure 8, page 19. In Sleep mode the VDD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
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- This parameter is guaranteed by process monitoring but is not production tested.
- This parameter is guaranteed only if correct trimming was applied. Additionally See Watchdog Period Range Value (AWD Trim) on page
Table 4. Dynamic Electrical Characteristics (continued) microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
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Figure 4. Test Circuit for Transient Test Pulses Figure 5. Test Circuit for LIN Timing Measurements Figure 6. LIN Timing Measurements for Normal Slew Rate Note: Waveform in accordance to ISO7637 part 1, test pulses 1, 2, 3a and 3b.
Figure 7. LIN Timing Measurements for Slow Slew Rate Figure 8. Wake-Up Stop Mode Timing Figure 9. Wake-Up Sleep Mode Timing
0.4 VSUP
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Figure 10. Power On Reset and Normal Request Time-out Timing
Analog Integrated Circuit Device Data Freescale Semiconductor 21 908E622 Functional Description Introduction FUNCTIONAL DESCRIPTION INTRODUCTION The 908E622 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E622 is well suited to perform complete mirror control via a three-wire LIN bus. This device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as half-bridge outputs and three high-side switches. Other ports are also provided, which include a circuitry for EC-glass control, one Hall-effect sensor input port, one analog input port with a switched current source, one wake-up terminal, and a selectable HVDD terminal. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 2, 908E622 Simplified Internal Block Diagram, page 2, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. PORT A I/O TERMINALS These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals, KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is not accessible in this device and is internally connected to the SPI slave select input of the analog die. For details refer to the 68HC908EY16 datasheet. PORT B I/O TERMINALS These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. PTB0/AD0 is internally connected to the ADOUT terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB1/AD1, PTB2/AD2, PTB6/AD6/TBCH0, PTB7/ AD7/TBCH1 terminals are not accessible in this device. For details refer to the 68HC908EY16 datasheet. PORT C I/O TERMINALS These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet. PORT D I/O TERMINALS PTD0/TACH0/BEMF and PTD1/TACH1 are special- function, bidirectional I/O port terminals that can also be programmed to be timer terminals. PTD0/TACH0 terminal is internally connected to the PWM input of the analog die and only accessible for test purposes (can not be used in the application). For details refer to the 68HC908EY16 datasheet. PORT E I/O TERMINAL PTE0/TXD and PTE1/RXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. PTE1/RXD is internally connected to the RXD terminal of the analog die and only accessible for test purposes (can not be used in the application). For details refer to the 68HC908EY16 datasheet. EXTERNAL INTERRUPT TERMINAL (IRQ) The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet.
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Functional Terminal Description EXTERNAL RESET TERMINAL (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. POWER SUPPLY TERMINALS (VSUP1:VSUP8) VSUP1:VSUP8 are device power supply terminals. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output drivers, multiple VSUP terminals are provided. All VSUP terminals must be connected to get full chip functionality. POWER GROUND TERMINALS (GND1:GND4) GND1:GND4 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output drivers, multiple terminals are provided. GND1 and GND2 terminals must be connected to get full chip functionality. HALF-BRIDGE OUTPUT TERMINALS (HB1:HB4) The 908E622 device includes power MOSFETs configured as four half-bridge driver outputs. The HB3:HB4 have a lower RDS(ON), to run higher currents (e.g. fold motor), than the HB1:B2 outputs. The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy. Over current protection is done on both high-side and low- side FETs. The current recopy are done on the low-side MOSFETs. HIGH-SIDE OUTPUT TERMINALS (HS1:HS3) The HS output terminals are a low RDS(ON) high-side switches. Each HS switch is protected against overtemperature and overcurrent. The output is capable of limiting the inrush current with an automatic PWM or feature a real PWM capability using the PWM input. The HS1 has a lower RDS(ON), to run higher currents (e.g. heater), than the HS2 and HS3 outputs. For the HS1 two terminals (HS1a:HS1b) are necessary for the current capability and have to be connected externally. Important: The HS3 can be only used to drive resistive loads. EC GLASS TERMINALS (ECR, EC) These terminals are used to drive the electrochrome function on EC glass mirrors. The ECR terminal is used to connect an external ballast resistor. The EC terminal provides the mirror with an regulated output voltage up to 1.4V. The output voltage can be selected by an integrated DA converter. HALL-EFFECT SENSOR INPUT TERMINAL (H0) The Hall-effect sensor input terminal H0 provides an input for Hall-effect sensors (2pin or 3pin) or a switch. ANALOG INPUT TERMINALS (A0, A0CST) These terminals are analog inputs with selectable current source values. The A0CST is intent to trim the A0 input. WAKE-UP INPUT TERMINAL (L0) This terminal is 40V rated input. It can be used as wake-up source for a system wake-up. The input is falling or rising edge sensitive. Important: If unused this terminal should be connected to VSUP or GND to avoid parasitic transitions. In Low Power Mode this could lead to random wake-up events. SWITCHABLE VDD OUTPUT TERMINAL (HVDD) The HVDD terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors or potentiometers. The output is short-circuit protected. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. +5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. Important The VDD terminal should not be used to supply other loads; use the HVDD terminal for this purpose. The VDD, EVDD and VDDA/VREFH terminals must be connected together. VOLTAGE REGULATOR GROUND TERMINAL (VSS) The VSS terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Important VSS, EVSS and VSSA/VREFL terminals must be connected together.
Analog Integrated Circuit Device Data Freescale Semiconductor 23 908E622 Functional Description Functional Terminal Description RESET TERMINAL (RST_A) RST_A is the bidirectional reset terminal of the analog die. It is an open drain with pullup resistor and must be connected to the RST terminal of the MCU. INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pullup resistor and must be connected to the IRQ terminal of the MCU. ADC SUPPLY/REFERENCE TERMINALS (VDDA/ VREFH AND VSSA/VREFL) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). VREFH and VREFL are the reference voltage terminals for the ADC. The supply and reference signals are internally connected. It is recommended that a high quality ceramic decoupling capacitor be placed between these terminals. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals. The MCU operates from a single power supply. Fast signal transitions on MCU terminals place high, short- duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. TEST MODE TERMINAL (TESTMODE) This terminal is for test purpose only. In the application this terminal has to be forced to GND. For Programming/Test this terminal has to be forced to VDD to bring the analog die into Test mode. In Test mode the Reset Time-out (80ms) is disabled and the LIN receiver is disabled NOTE: After detecting a RESET (internal or external) the PSON bit needs to be set within 80ms. If not the device will automatically enter sleep mode. MCU TEST TERMINAL (FLSVPP) This terminal is for test purposes only. This terminal should be either left open (not connected) or can be connected to GND. EXPOSED PAD TERMINAL The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential. 4,7µF0,1µF VDDA/VREFH EVDD EVSS VSSA/VREFL VDD VSS µC Analog Die
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Sleep modes are low power modes with wake-up capabilities. SLEEP bits in the System Control Register. overview of the operating modes. Figure 11. Operating Modes and Transitions programming by applying VDD on the TESTMODE terminal. the L0IF and LINIF bits in the Interrupt Flag Register.
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MCU, refer to the MC68HC908EY16 datasheet. Register). After reset all interrupts are automatically disabled. threshold it will set the HVIF bit in the Interrupt Flag Register. interrupt will be initiated. During Stop and Sleep mode the HVI circuitry is disabled. (HTIE = 1), an interrupt will be initiated. During Stop and Sleep mode the HTI circuitry is disabled. the LINIF is indicating the reason for the wake-up / interrupt. any of the power stages (see Figure 14, page 27). During Stop and Sleep mode the PSFI circuitry is disabled. Table 6. Operating Modes Overview
- The SPI is still active in Stop mode. However, due to the limited current capability of the voltage regulator in Stop mode, the PSON
bit has to be set before the increased current caused from a running MCU causes an LVR.
During Stop and Sleep mode the H0I circuitry is disabled. maskable with the L0IE bit in the interrupt mask register. L0 input. Clear L0IF by writing a logic [1] to L0IF. H0 input. Clear H0IF by writing a logic [1] to H0IF. a logic [0] to LINIF has no effect. This read/write flag is set on high temperature condition. interrupt cannot be lost due to inadvertent clearing of HTIF. due to inadvertent clearing of LVIF. due to inadvertent clearing of HVIF. Figure 14. Principal Implementation of the PSFIF
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Functional Device Operation Operational Modes INTERRUPT MASK REGISTER (IMR) L0IE - L0 Input Interrupt Enable Bit This read/write bit enables CPU interrupts by the L0 flag, L0IF. Reset clears the L0IE bit. 1 = interrupt requests from L0IF flag enabled 0 = interrupt requests from L0IF flag disabled H0IE - H0 Input Interrupt Enable Bit This read/write bit enables CPU interrupts by the Hallport flag, H0IF. Reset clears the H0IE bit. 1 = interrupt requests from H0IF flag enabled 0 = interrupt requests from H0IF flag disabled LINIE - LIN line Interrupt Enable Bit This read/write bit enables CPU interrupts by the LIN flag, LINIF. Reset clears the LINIE bit. 1 = interrupt requests from LINIF flag enabled 0 = interrupt requests from LINIF flag disabled HTRD - High Temperature Reset Disable Bit This read/write bit disables the high temperature reset function. Reset clears the HTRD bit. 1 = high temperature reset is disabled 0 = high temperature reset is enabled Note: Disabling of the high temperature reset can lead to a destruction of the part in cases of high temperature. This bit was foreseen for test purposes only!!!!! HTIE - High Temperature Interrupt Enable Bit This read/write bit enables CPU interrupts by the high temperature flag, HTIF. Reset clears the HTIE bit. 1 = interrupt requests from HTIF flag enabled 0 = interrupt requests from HTIF flag disabled LVIE - Low Voltage Interrupt Enable Bit This read/write bit enables CPU interrupts by the low voltage flag, LVIF.Reset clears the LVIE bit. 1 = interrupt requests from LVIF flag enabled 0 = interrupt requests from LVIF flag disabled HVIE - High Voltage Interrupt Enable Bit This read/write bit enables CPU interrupts by the high voltage flag, HVIF.Reset clears the HVIE bit. 1 = interrupt requests from HVIF flag enabled 0 = interrupt requests from HVIF flag disabled PSFIE - Power Stage Fail Interrupt Enable Bit This read/write bit enables CPU interrupts by power stage fail flag, PSFIF. Reset clears the PSFIE bit. 1 = interrupt requests from PSFIF flag enabled 0 = interrupt requests from PSFIF flag disabled Register Name and Address: IMR - $09 Bit7 6 5 4 3 2 1 Bit0 Read L0IE H0IE LINIE HTRD HTIE LVIE HVIE PSFIE Write Reset 0 0 0 0 0 0 0 0
(1.25 ms typical), after the reset event is gone. Figure 15. Internal Reset Routing in the SPI including the RSR and set the POR bit. value (above LVR Threshold). Also see Figure 10, page 20).
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Functional Device Operation Operational Modes In addition the register includes two flags which will indicate the source of a wake-up from Sleep mode: Either LIN bus activity or an event on the L0 wake-up input terminal. POR Power On Reset bit This read/write bit is set after power on. Bit is cleared by writing a logic 1 to this location. 1 = Reset due to power on 0 = no power on reset PINR Reset forced from external Reset terminal bit This read/write bit is set after an reset was forced on the external reset RST_A terminal. Bit is cleared by writing an logic 1 to this location. 1 = reset source is external reset terminal 0 = no external reset WDR Watch Dog Reset bit This read/write flag is set due to watchdog time-out or wrong watchdog timer reset. Clear WDR by writing a logic 1 to WDR. 1 = reset source is watchdog 0 = no watchdog reset HTR High Temperature Reset bit This read/write bit is set if the chip temperature exceeds a certain value. Bit is cleared by writing a logic 1 to this location. 1 = reset due to high temperature condition 0 = no high temperature reset LVR Low Voltage Reset bit This read/write bit is set if the external VDD voltage coming from the main voltage regulator falls below a certain value. Bit is cleared by writing a logic 1 to this location. 1 = reset due to low voltage condition 0 = no low voltage reset LINWF LIN Wake-Up Flag This read/write bit is set if a bus activity was the case of an wake-up. Bit is cleared by writing a logic 1 to this location. 1 = Wake-up due to bus activity 0 = no wake-up due to bus activity L0WF L0 Wake-Up Flag This read/write bit is set if a event on the L0 terminal caused an wake-up. Bit is cleared by writing a logic 1 to this location. 1 = Wake-Up due to L0 terminal 0 = no Wake-Up due to L0 terminal ANALOG DIE INPUTS/OUTPUTS LIN PHYSICAL LAYER The LIN bus terminal provides a physical layer for single- wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. The slew rate can be selected for optimized operation at 10 and 20kBit/s as well as high baud rates for test and programming. The slew rate can be adapted with 2 bits SRS[1:0] in the System Control Register. The initial slew rate is optimized for 20kBit/s. The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set and the LIN transceiver is disabled after a certain time. Register Name and Address: RSR - $0D Bit7 6 5 4 3 2 1 Bit0 Read POR PINR WDR HTR LVR LINWF LOWF Write POR 1 0 0 0 0 0 0 0
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analog inputs for potentiometers, NTC, etc. bits in the A0MUCTL register. Figure 17. Analog Input and Multiplexer Bit CSON and adjusted with the bits CSSEL[1:0]. ceased during STOP and SLEEP mode operation. constant up to an output voltage of ~4.75V. value for calculating the current on A0.
selected with the SS[3:0] bits in the A0MUCTL register. and Multiplexer control register (A0MUCTL). the current through the transistor. The analog die includes an on chip temperature sensor. actual mean chip junction temperature. be able to read the actual voltage on the EC terminal. Reset clears CSSEL[1:0] bits. Table 7. A0 Current Source Level Selection Bits of the H-Bridges HB1:HB4 current recopy. Table 8. Analog Multiplexer Configuration Bits.
0 CSA SS3 SS2 SS1 SS0
1000 C h i p t e m p e r a t u r e
1001 V S U P p r e s c a l e r
1010 T e r m i n a l A 0
1011 T e r m i n a l A 0 C S T
1100 T e r m i n a l E C
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be able to read 3pin / 2pin hall sensors or switches. Figure 18. General purpose / hall-effect sensor input (H0) protected (current limitation) against short circuit to GND. before sensing the hallflags. (>100nF) close to the H0 terminal is required.
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Figure 21. H0 used to read in standard switches is selected as General Purpose or as 2pin Hallsensor input. reading VSUP or VDD related signals. Status and Control register (HLSCTL). the Interrupt Mask register. STOP or SLEEP mode a wake-up is initiated.
This read/write bit disables the H0 Pull-up resistor. high-side or low-side configurations. Figure 22. Half-Bridge Push-Pull Output Driver
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set, the high-side MOSFET is in PWM mode. the high-side MOSFET did not fall below a certain threshold. output according to the following table. Reset clears all HBx_H, HBx_L bits. Table 9. Half-Bridge Configuration PWM terminal (see Figure 2, page 2). on if the PWM controlled high-side MOSFET is off. internally amplified and switched to the Analog Multiplexer. The first threshold is the high temperature interrupt (HTI). Bits HTIS0-1 in the System Control Register (SYSCTL). the Half-Bridge Status and Control Register (HBSCTL) is set. Register (HBSCTL) or by a reset.
flags in the Interrupt Flag Register (IFR) or by a reset. low voltage condition is still present. on either the LS or the HS FET on HBx has occurred. [1] to HBxOCF. Writing a logic [0] to HBxOCF has no effect. Reset clears the HBxOCF bit. Figure 23. HS circuitry System Control Register (SYSCTL) is set. HSxON bit in the High-Side Output Register (HSOUT) is set. MOSFETs depending on the HSONx and PWMHSx bits.
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Table 10. High-Side Configuration Bits Register is cleared, the output is disabled. HS, HVDD, EC, H0) in order to protect the device. automatically switched off and the overcurrent flag is set. Status register is set beyond a certain period of time. and a real short on the output.
Figure 24. Inrush Current Limitation on HS Outputs and switched to the Analog Multiplexer. This read/write bit enables the HVDD output. Reset clears the HSxON bits.
0 HS3P
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Functional Device Operation Operational Modes HSxPWM High-Side PWM on/off Bits These read/write bits enable the PWM control of the High- Side Fets. Reset clears the HSxPWM bits. 1 = High-Side x is controlled by PWM input signal 0 = High-Side x is not controlled by PWM input signal High-Side Status Register (HSSTAT) HSxOCF High-Side Overcurrent Flag Bit This read/write flag is set by an overcurrent condition at the high-side drivers x. Clear HSxOCF and enable the HS Driver by writing a logic [1] to HSxOCF. Writing a logic [0] to HSxOCF has no effect. Reset clears the HSxOCF bit. 1 = overcurrent condition on high-side drivers has occurred 0 = no overcurrent condition on high-side drivers has occurred HVDDOCF HVDD Output Overcurrent Flag Bit This read/write flag is set by an overcurrent condition at HVDD terminal. Clear HVDDOCF and enable the output by writing a logic [1] to the HVDDOCF Flag. Writing a logic [0] to HVDDOCF has no effect. Reset clears the HVDDOCF bit. 1 = overcurrent condition on VDD output has occurred 0 = no overcurrent condition on VDD output has occurred Register Name and Address: HSSTAT - $04 Bit7 6 5 4 3 2 1 Bit0 Read HVDD OCF 0 0 0 0 HS3O CF HS2O CF HS1O CFWrite Reset 0 0 0 0 0 0 0 0
output voltage given by the 6Bit DA Converter. Figure 25. EC Circuitry ECSCTL is set indicating the open load condition. Register (ECSCTL) is set and the EC circuitry is disabled. to control the output voltage between 0 and 1,4V.
Analog Integrated Circuit Device Data
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Functional Device Operation Operational Modes EC Status and Control Register (ECSCTL) ECON Electrochrome Circuitry enable Bit This read/write bit enables transistor T2 of the electrochrome circuitry. Reset clears the ECON bit. 1 = T2 EC circuitry enabled 0 = T2 EC circuitry disabled ECOLT Electrochrome Circuitry Open Load Test Bit This read/write bit enables the open load test for the electrochrome circuitry. If this bit is set the EC Glass functionality is ceased. Reset clears the ECOLT bit. 1 = EC Open Load circuitry enabled 0 = EC Open Load circuitry disabled ECRON EC Resistor enable Bit This read/write bit enables transistor T1 of the electrochrome circuitry. Reset clears the ECRON bit. 1 = T1 EC circuitry enabled 0 = T1 EC circuitry disabled Note: Controlling the output voltage on terminal EC is done by transistor T2 only. The enable of T1 will switch the VSUP voltage via the external EC resistor to the EC glass. ECOCF EC Output Overcurrent Flag Bit This read/write flag is set on short circuit condition at the EC output (short to VSUP/ short to GND). Clear ECOCF and enable the EC circuitry by writing a logic [1] to ECOCF. Writing a logic [0] to ECOCF has no effect. Reset clears the ECOCF bit. 1 = short circuit condition on EC output detected 0 = no short circuit condition on EC output detected ECOLF EC Open Load Flag Bit This read/write flag is set on an open load condition of the EC output. Clear ECOLF and disable the EC circuitry by writing a logic [1] to ECOLF. Writing a logic [0] to ECOLF has no effect. Reset clears the ECOLF bit. 1 = open load condition on EC output detected 0 = no open load condition on EC output detected System Control Register (SYSCTL) PSON Power Stages On Bit This read/write bit enables the power stages (half bridges, high-sides, LIN transmitter, A0 Current Sources and HVDD output). Reset clears the PSON bit. 1 = power stages enabled 0 = power stages disabled STOP Change to STOP Mode Bit This write bit instructs the chip to enter Stop mode (See Operational Modes on page 24). Reset or CPU interrupt requests clear the STOP bit. 1 = go to Stop mode 0 = not in stop mode In order to safely Stop mode all other bits (Bit7-Bit2) have to be 0. Otherwise the STOP command will not be executed. SLEEP Change to SLEEP Mode Bit This write bit instructs the chip to enter Sleep mode (See Operational Modes on page 24). Reset or CPU interrupt requests clear the SLEEP bit. 1 = go to Sleep mode 0 = not in sleep mode In order to safely enter Sleep mode all other bits (Bit7-Bit2) have to be 0. Otherwise the SLEEP command will not be executed. HTIS0-1 High Temperature Interrupt Shutdown Bits This read/write bits selects the power stage behavior at High Temperature Interrupt (HTI). Reset clears the HTIS0-1 bits. The HTIS0 bit selects the behavior of the high-side HS1:3 and the high-side FET of the half-bridges HB1:4. 1 = automatic HTI shutdown of the high-side drivers disabled 0 = automatic HTI shutdown of the high-side drivers enabled The HTIS1 bit selects the behavior of the low-side drivers of the half-bridges HB1:4. 1 = automatic HTI shutdown of the low-side drivers disabled Register Name and Address: ECSCTL - $05 Bit7 6 5 4 3 2 1 Bit0 Read ECON ECOLT ECRON 0 0 0 ECOC F ECOLF Write Reset 0 0 0 0 0 0 0 0 Register Name and Address: SYSCTL - $00 Bit7 6 5 4 3 2 1 Bit0 Read PSON HTIS1 HTIS0 VIS SRS1 SRS0 Write STOP SLEEP Reset 0 0 0 0 0 0 0 0
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Figure 29. ECF flag generation recover from e.g. code runaways or similar conditions. certain time frame / window. function is enabled it is not possible to disable it via software. (WDRST) has occurred in the closed window. WDCTL, in order to get 10ms, 20ms, 40ms and 80ms period. Figure 30. Window Watchdog Period MCU the full time to reset the watchdog. WDRE can only be set and cant be cleared by software. This read/write bit select the clock rate of the Watchdog. Reset clears the WDP1:0 bits. Table 12. Watchdog Period Selection Bits
Analog Integrated Circuit Device Data Freescale Semiconductor 47 908E622 Functional Device Operation Operational Modes Voltage Regulator The 908E622 contains a low power, low drop voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main regulator and the low voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. Run mode During RUN mode the main voltage regulator is on. It will provide a regulated supply to all digital sections. STOP mode During STOP mode, the Stop mode regulator will take care of suppling a regulated output voltage. The Stop mode regulator has a limited output current capability. SLEEP mode In Sleep mode the main voltage regulator external VDD is turned off and the LVR circuitry will force the RST_A terminal low.
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communication link between the MCU and the analog die. A complete data transfer via the SPI, consists of 2 bytes. system status and the data of the selected address. Figure 31. SPI Protocol data are moved to MISO with the rising edge of SPSCK. edges are present in the active phase of SS. latched into the register, by the rising edge of SS. include the address of the desired register. includes the information if it is a read or a write operation. and ignored for read operations.
Analog Integrated Circuit Device Data Freescale Semiconductor 49 908E622 Functional Device Operation Logic Commands and Registers Master Data Byte This byte includes data to be written or no valid data during a read operation. Slave Status Byte This byte includes always the contents of the system status register ($0C) independent if it is a write or read operation or which register was selected. Slave Data Byte This byte includes the contents of selected register, during write operation in includes the register content prior to write operation.
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TABLE 13 SUMMARIZES THE SPI REGISTER ADDRESSES AND THE BIT NAMES OF EACH REGISTER. Table 13. SPI Register Overview
(VDD) as indicated in the 68HC908EY16 datasheet. Trim Register ICGTR at address $38 of the MCU. Important The value has to copied after every reset. The window watchdog supervises device recover from e.g. classifies the watchdog period into 3 ranges (Range 0, 1, 2). interval, e.g. caused by ICG variation. watchdog based on the Window No. and chosen period. Table 14. Window Clear Interval $FDCF WDP1:0 min. max. Unit t_open t_closed Unit t_opt Unit max.
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register after a reset to ensure proper trimming of the device. testing and is not allowed to be written to. capacitive load) for the HVDD over current detection. Table 15. HVDD Overcurrent Shutdown Selection Bits reset. Reset clears the ITRIM3:0 bits. Table 16. IRef Trim Bits after every reset. Reset clears the CRHBHC1:0 bits. Table 17. Current Recopy Trim for HB1:2 (CSA=0)
after every reset. Reset clears the CRHB5:3 bits. Table 18. Current Recopy Trim for HB3:4 (CSA=1) after every reset. Reset clears the CRHB2:0 bits. Table 19. Current Recopy Trim for HB1:2 (CSA=1) after every reset. Reset clears the CRHBHC3:2 bits. Table 20. Current Recopy Trim for HB3:4 (CSA=0) values have to be copied into these bits after every reset. Reset clears the CRHS5:3 bits. Table 21. Current Recopy Trim for HS2:3
Analog Integrated Circuit Device Data
54 Freescale Semiconductor
Functional Device Operation Logic Commands and Registers CRHS2:0 - Current Recopy HS1 Trim Bits These write only bits are for trimming of the current recopy of the high-side HS1. The provided Trim values have to be copied into these bits after every reset. Reset clears the CRHS2:0 bits. Current Recopy Trim for HS1 CRHS2 CRHS1 CRHS0 Adjustment 00 0 0 00 1 - 5 % 01 0 - 1 0 % 0 1 1 -15% 1 0 0 reserved 10 1 5 % 11 0 1 0 % 11 1 1 5 % CRHS2 CRHS1 CRHS0 Adjustment
section development support. soldered onto the pcb board. and analog die have to be separated (e.g. IRQ - IRQ_A). datasheet - section development support. Figure 32. Normal Monitor Mode Circuit (MCU only) Vsup instead (12V) as described in Figure 33, page 56.
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Figure 33. Normal Monitor Mode Circuit Table 22. Monitor Mode Signal Requirements and Options
- PTA0 must have a pullup resistor to V DD in monitor mode
- External clock is a 4.9152MHz, 9.8304MHz or 19.6608MHz canned oscillator on OCS1
- Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256
- V TST is a high voltage VDD +3 . 5 V ≤ VTST ≤ VDD +4 . 5 V
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Figure 35. PCB Layout Recommendations Table 23. Component Value Recommendation should be connected right at the C3. C5 180pF, SMD Ceramic, Low ESR Close (<5mm) to LIN terminal. Total Capacitance on LIN has to be below 220pF.
- Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings
- Components are recommended to improve EMC and ESD performance.
Analog Integrated Circuit Device Data Freescale Semiconductor 59 908E622 Package Dimensions PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number: 98ARL10519D. DWB SUFFIX 54-TERMINAL SOICW-EP 98ARL10519D ISSUE A
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electrical, application and packaging information is provided in the data sheet. temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. temperature while only heat source 1 is heating with P1. RθJ21 and RθJ22, respectively. simulation according to the standards listed below. Figure 36. Thermal Land Pattern for Direct Thermal Table 24. Thermal Performance Comparison
- Per JEDEC JESD51-2 at natural convection, still air
- 2s2p thermal test board per JEDEC JESD51-7and
- Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
- Single layer thermal test board per JEDEC JESD51-3 and
- Thermal resistance between the die junction and the
exposed pad, infinite heat sink attached to exposed pad.
Figure 37. Thermal Test Board number of the die where the junction temperature is sensed. Table 25. Thermal Resistance Performance
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Figure 38. Device on Thermal Test Board RθJA Figure 39. Transient Thermal Resistance RθJA (1.0 W Step Response)
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