MM74C150 FAIRCHILD | Alldatasheet

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■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: 1.0V ■ High noise immunity: 0.45 VCC (typ.) ■ TTL compatibility: Drive 1 TTL Load Ordering Code: Connection Diagram Pin Assignments for DIP Order Number Package Number Package Description MM74C150N N24A 24-Lead plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide MM82C19N N24A 24-Lead plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide

www.fairchildsemi.com 2 MM74C150 • MM82C19 Truth Table MM74C150 Note 1: For MM72C19/MM82C19 this would be Hi-Z, everything else is the same. Inputs Output D C B A STROBE E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 W X X X X 1 XXXXXXXXXXX X X X X X 1 ( N o t e 1 ) 0 0 0 0 0 0XXXXXXXXXX X X X X X 1 0 0 0 0 0 1XXXXXXXXXX X X X X X 0 0 0 0 1 0 X0XXXXXXXXX X X X X X 1 0 0 0 1 0 X1XXXXXXXXX X X X X X 0 0 0 1 0 0 XX0XXXXXXXX X X X X X 1 0 0 1 0 0 XX1XXXXXXXX X X X X X 0 0 0 1 1 0 XXX0XXXXXXX X X X X X 1 0 0 1 1 0 XXX1XXXXXXX X X X X X 0 0 1 0 0 0 XXXX0XXXXXX X X X X X 1 0 1 0 0 0 XXXX1XXXXXX X X X X X 0 0 1 0 1 0 XXXXX0XXXXX X X X X X 1 0 1 0 1 0 XXXXX1XXXXX X X X X X 0 0 1 1 0 0 XXXXXX0XXXX X X X X X 1 0 1 1 0 0 XXXXXX1XXXX X X X X X 0 0 1 1 1 0 XXXXXXX0XXX X X X X X 1 0 1 1 1 0 XXXXXXX1XXX X X X X X 0 1 0 0 0 0 XXXXXXXX0XX X X X X X 1 1 0 0 0 0 XXXXXXXX1XX X X X X X 0 1 0 0 1 0 XXXXXXXXX0X X X X X X 1 1 0 0 1 0 XXXXXXXXX1X X X X X X 0 1 0 1 0 0 XXXXXXXXXX 0 X X X X X 1 1 0 1 0 0 XXXXXXXXXX 1 X X X X X 0 1 0 1 1 0 XXXXXXXXXXX 0 X X X X 1 1 0 1 1 0 XXXXXXXXXXX 1 X X X X 0 1 1 0 0 0 XXXXXXXXXXX X 0 X X X 1 1 1 0 0 0 XXXXXXXXXXX X 1 X X X 0 1 1 0 1 0 XXXXXXXXXXX X X 0 X X 1 1 1 0 1 0 XXXXXXXXXXX X X 1 X X 0 1 1 1 0 0 XXXXXXXXXXX X X X 0 X 1 1 1 1 0 0 XXXXXXXXXXX X X X 1 X 0 1 1 1 1 0 XXXXXXXXXXX X X X X 0 1 1 1 1 1 0 XXXXXXXXXXX X X X X 1 0

3 www.fairchildsemi.com MM74C150 • MM82C19 Logic Diagrams MM74C150

www.fairchildsemi.com 4 MM74C150 • MM82C19 Logic Diagrams (Continued) MM82C19

5 www.fairchildsemi.com MM74C150 • MM82C19 Absolute Maximum Ratings(Note 2) Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The Electrical Characteristic table provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise noted. Voltage at Any Pin −0.3V to VCC +0.3V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3.0V to 15V VCC 18V Lead Temperature (soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS to CMOS VIN(1) Logical “1” Input Voltage V CC = 5.0V 3.5 V VCC = 10V 8.0 V VIN(0) Logical “0” Input Voltage V CC = 5.0V 1.5 V VCC = 10V 2.0 V VOUT(1) Logical “1” Output Voltage V CC = 5.0V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 V VOUT(0) Logical “0” Output Voltage V CC = 5.0V, IO = +10 µA0 . 5 V VCC = 10V, IO = +10 µA1 . 0 V IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 V IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA IOZ Output Current in High Impedance State MM82C19 V CC = 15V, VO = 15V 0.005 1.0 µA VCC = 15V, VO = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.05 300 µA CMOS/LPTTL Interface VIN(1) Logical “1” Input Voltage 74C, 82C, V CC = 4.75V V CC −1.5 V VIN(0) Logical “0” Input Voltage 74C, 82C, V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage 74C, 82C, V CC = 4.75V, IO = −1.6 mA 2.4 V VOUT(0) Logical “0” Output Voltage 74C, 82C, V CC = 4.75V, IO = 1.6 mA 0.4 V Output Drive (Short Circuit Current) I SOURCE Output Source Current V CC = 5.0V, VOUT = 0V, TA = 25°C −4.35 −8m A (P-Channel) ISOURCE Output Source Current V CC = 10V, VOUT = 0V, TA = 25°C −20 −40 mA (P-Channel) ISINK Output Sink Current V CC = 5.0V, VOUT = VCC , TA = 25°C4 . 3 5 8 m A (N-Channel) ISINK Output Sink Current V CC = 10V, VOUT = VCC , TA = 25°C2 0 4 0 m A (N-Channel)

www.fairchildsemi.com 6 MM74C150 • MM82C19 TA = 25°C, CL = 50 pF , unless otherwise noted Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Note 5: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics, application note AN-90. Symbol Parameter Conditions Min Typ Max Units tpd0, tpd1 Propagation Delay Time to a V CC = 5.0V 250 600 ns Logical “0” or Logical “1” V CC = 10V 110 300 ns from Data Inputs to Output V CC = 5.0V, CL = 150 pF 290 650 ns VCC = 10V, CL = 150 pF 120 330 ns tpd0, tpd1 Propagation Delay Time to a V CC = 5.0V 290 650 ns Logical “0” or Logical “1” V CC = 10V 120 330 ns from Data Select Inputs to Output tpd0, tpd1 Propagation Delay Time to a V CC = 5.0V 120 300 ns Logical “0” or Logical “1” V CC = 10V 55 150 ns from Strobe to Output MM74C150 t1H , t0H Delay from Strobe to High V CC = 5.0V, RL = 10k, CL = 5 pF 80 200 ns Impedance State V CC = 10V, RL = 10k, CL = 5 pF 60 150 ns MM82C19 tH1 , tH0 Delay from Strobe to Logical V CC = 5.0V, RL = 10k, CL = 5 pF 80 250 ns “1” Level or to Logical “0” V CC = 10V, RL = 10k, CL = 5 pF 30 120 ns Level (from High Impedance State) MM82C19 C IN Input Capacitance Any Input (Note 4) 5.0 pF C OUT Output Capacitance (Note 4) 11.0 pF MM82C19 C PD Power Dissipation Capacitance (Note 5) 100 pF

7 www.fairchildsemi.com MM74C150 • MM82C19 Switching Time Waveforms CMOS to CMOS t1H and tH1 t1H tH1 t0H and tH0 t0H Note: Delays measured with input tr, tf ≤ 20 ns. tH0

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C150 • MM82C19 16-Line to 1-Line Multiplexer 3-STATE • 16-Line to 1-Line Multiplexer LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Package Number N24A