MM80C95

MM80C95 FAIRCHILD | Alldatasheet

Document overview

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• PDF pages: 7

Technical content

Features

■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: 1.0V ■ High noise immunity: 0.45 VCC (typ.) ■ TTL compatible: Drive 1 TTL Load

Applications

• Bus drivers: Typical propagation delay into 150 pF load is 40 ns Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP MM80C95 Top View MM80C97 Top View MM80C98 Top View Order Number Package Number Package Description MM80C95N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM80C97M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM80C97N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM80C98N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 MM80C95 • MM80C97 • MM80C98 Schematic Diagrams MM80C95 3-STATE MM80C97 3-STATE MM80C98 3-STATE Truth Tables MM80C95 MM80C97 MM80C98 X = Irrelevant Note 1: Output 5–6 only Note 2: Output 1–4 only Disable Input Input Output DIS1 DIS2 00 0 0 00 1 1

01 X H - z

10 X H - z

11 X H - z

Disable Input Input Output DIS

4 DIS2

X 1 X H-z (Note 1)

1 X X H-z (Note 2)

Disable Input Input Output DIS X 1 X H-z (Note 1)

3 www.fairchildsemi.com MM80C95 • MM80C97 • MM80C98 Absolute Maximum Ratings(Note 3) Note 3: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Voltage at Any Pin −0.3V to VCC + 0.3V Operating T emperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Power Supply Voltage (V CC )1 8 V Lead Temperature (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5V 3.5 V VCC = 10V 8.0 V VIN(0) Logical “0” Input Voltage V CC = 5V 1.5 V VCC = 10V 2.0 V VOUT(1) Logical “1” Output Voltage V CC = 5V 4.5 V VCC = 10V 9.0 V VOUT(0) Logical “0” Output Voltage V CC = 5V 0.5 V VCC = 10V 1.0 V IIN(1) Logical “1” Input Current V CC = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current −1.0 −0.005 µA IOZ Output Current in High V CC = 15V, VO = 15V 0.005 1.0 µA Impedance State V CC = 15V, VO = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.01 15 µA TTL INTERFACE V IN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 V VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage V CC = 4.75V, 2.4 V IO = −1.6 mA VOUT(0) Logical “0” Output Voltage V CC = 4.75V, 0.4 V IO = 1.6 mA OUTPUT DRIVE (Short Circuit Current) ISOURCE Output Source Current V CC = 5V, VIN(1) = 5V −4.35 mA TA = 25°C, VOUT = 0V ISOURCE Output Source Current V CC = 10V, VIN(1) = 10V −20 mA TA = 25°C, VOUT = 0V ISINK Output Sink Current V CC = 5V, VIN(0) = 0V 4.35 mA TA = 25°C, VOUT = VCC ISINK Output Sink Current V CC = 10V, VIN(0) = 0V 20 mA TA = 25°C, VOUT = VCC

www.fairchildsemi.com 4 MM80C95 • MM80C97 • MM80C98 TA = 25°C, CL = 50 pF , unless otherwise noted. Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Capacitance is guaranteed by periodic testing. Note 6: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. AC Test Circuits and Switching Time Waveforms tpd0, tpd1 CMOS to CMOS t1H and tH1 t1H Symbol Parameter Conditions Min Typ Max Units tpd0, tpd1 Propagation Delay Time to a Logical “0” or Logical “1” from Data Input to Output MM80C95, MM80C97 V CC = 5V 60 100 ns VCC = 10V 25 40 ns MM80C98 V CC = 5V 70 150 ns VCC = 10V 35 75 ns tpd0, tpd1 Propagation Delay Time to a Logical “0” or Logical “1” from Data Input to Output MM80C95, MM80C97 V CC = 5V, CL = 150 pF 85 160 ns VCC = 10V, CL = 150 pF 40 80 ns MM80C98 V CC = 5V, CL = 150 pF 95 210 ns VCC = 10V, CL = 150 pF 45 110 ns t1H , t0H Delay from Disable Input to High Impedance RL = 10k, CL = 5 pF State, (from Logical “1” or Logical “0”) MM80C95 V CC = 5V 80 135 ns VCC = 10V 50 90 ns MM80C97 V CC = 5V 70 125 ns VCC = 10V 50 90 ns MM80C98 V CC = 5V 90 170 ns VCC = 10V 70 125 ns tH1 , tH0 Delay from Disable Input to Logical “1” Level RL = 10k, CL = 50 pF (from High Impedance State) MM80C95 V CC = 5V 120 200 ns VCC = 10V 50 90 ns MM80C96 V CC = 5V 130 225 ns VCC = 10V 60 110 ns MM80C98 V CC = 5V 120 200 ns VCC = 10V 50 90 ns C IN Input Capacitance Any Input (Note 5) 5.0 pF C OUT Output Capacitance 3-STATE Any Output (Note 5) 11 pF C PD Power Dissipation Capacitance (Note 6) 60 pF

5 www.fairchildsemi.com MM80C95 • MM80C97 • MM80C98 AC Test Circuits and Switching Time Waveforms (Continued) tH1 t0H and tH0 t0H tH0 Note: Delays measured with input tr, tf ≤ 20 ns. Typical Performance Characteristics Propagation Delay vs Load Capacitance Δtpd/pF vs Power Supply Voltage N-Channel Output Drive at 25°C P-Channel Output Drive at 25 °C

www.fairchildsemi.com 6 MM80C95 • MM80C97 • MM80C98 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM80C95 • MM80C97 • MM80C98 3-STATE Hex Buffers • 3-STATE Hex Inverters LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E