MM74C905 FAIRCHILD | Alldatasheet

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Technical content

Features

I Wide supply voltage range: 3.0V to 15V I Guaranteed noise margin: 1.0V I High noise immunity: 0.45 VCC (typ) I Low power TTL compatibility: Fan out of 2 driving 74L I Provision for register extension or truncation I Operates in START/STOP or continuous conversion mode I Drive ladder switches directly. For 10 bits or less with 50k/100k R/2R ladder network Ordering Code: Connection Diagram Pin Assignments for DIP Order Number Package Number Package Description MM74C905N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide

www.fairchildsemi.com 2 MM74C905 Truth Table H = HIGH Level L = LOW Level X = Don’t Care NC = No Change Time Inputs Outputs tn DS E D0 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CC

0 XL LX X X XXXXXXXXXXX

1D 1 1 H LX L H HHHHHHHHHHH 2D 1 0 H L D 1 1 D 1 1L HHHHHHHHHHH

3 D 9 H L D 1 0 D 1 1 D 1 0 LHHHHHHHHHH

4 D 8 H L D 9 D 1 1 D 1 0 D 9 LHHHHHHHHH

5 D 7 H L D 8 D 1 1 D 1 0 D 9 D 8 LHHHHHHHH

6 D 6 H L D 7 D 1 1 D 1 0 D 9 D 8 D 7 LHHHHHHH

7 D 5 H L D 6 D 1 1 D 1 0 D 9 D 8 D 7 D 6 LHHHHHH

8 D 4 H L D 5 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 LHHHHH

9 D 3 H L D 4 D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 LHHHH

10 D2 H L D3 D11 D10 D9 D8 D7 D6 D5 D4 D3 L H H H

11 D1 H L D2 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 L H H

12 D0 H L D1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 L H

1 3 X H L D 0 D 1 1D 1 0D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 L

14 X X L X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 L

X X H X H N C N CN CN CN CN CN CN CN CN CN CN C

3 www.fairchildsemi.com MM74C905 Absolute Maximum Ratings(Note 1) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise noted Voltage at Any Pin −0.3V to VCC +0.3V Operating Temperature Range (TA) −40°C to +85°C Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3.0V to 15V Absolute Maximum VCC 16V Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5.0V 3.5 V VCC = 10V 8.0 V VIN(0) Logical “0” Input Voltage V CC = 5.0V 1.5 V VCC = 10V 2.0 V VOUT(1) Logical “1” Output Voltage V CC = 5.0V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 V VOUT(0) Logical “0” Output Voltage V CC = 5.0V, IO = 10 µA0 . 5 V VCC = 10V, IO = 10 µA1 . 0 V IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.05 300 µA CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 V VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage V CC = 4.75V, IO = −360 µA2 . 4 V VOUT(0) Logical “0” Output Voltage V CC = 4.75V, IO = 360 µA0 . 4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) ISOURCE Output Source Current V CC = 5.0V, VOUT = 0V −1.75 −3.3 mA (P-Channel) T A = 25°C ISOURCE Output Source Current V CC = 10V, VOUT = 0V −8.0 −15 mA (P-Channel) T A = 25°C ISINK Output Sink Current V CC = 5.0V, VOUT = VCC 1.75 3.6 mA (N-Channel) T A = 25°C ISINK Output Sink Current V CC = 10V, VOUT = VCC (N-Channel) T A = 25°C8 . 0 1 6 m A VCC = 10V ±5% R SOURCE Q11 –Q0 Outputs V OUT = VCC − 0.3V 150 350 Ω TA = 25°C R SINK Q11 –Q0 Outputs V CC = 10V ±5% VOUT = 0.3V 80 230 Ω TA = 25°C

www.fairchildsemi.com 4 MM74C905 TA = 25°C, CL = 50 pF, unless otherwise specified Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note— AN-90. Typical Performance Characteristics R SINK vs Temperature These points are guaranteed by automatic testing. R SOURCE vs Temperature These points are guaranteed by automatic testing. Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay Time from V CC = 5.0V 200 350 ns Clock Input to Outputs V CC = 10V 80 150 ns (Q0–Q11) (tpd(Q)) tpd Propagation Delay Time from V CC = 5.0V 180 325 ns Clock Input to D0 (tpd(D0))V CC = 10V 70 125 ns tpd Propagation Delay Time from V CC = 5.0V 190 350 ns Register Enable (E) to Output V CC = 10V 75 150 ns (Q11) (tpd(E)) tpd Propagation Delay Time from V CC = 5.0V 190 350 ns Clock to CC (tpd(CC))V CC = 10V 75 0.50 ns tS Data Input Set-Up Time V CC = 5.0V 80 ns VCC = 10V 30 ns tS Start Input Set-Up Time V CC = 5.0V 80 ns VCC = 10V 30 ns tW Minimum Clock Pulse Width V CC = 5.0V 250 125 ns VCC = 10V 100 50 ns tr, tf Maximum Clock Rise and Fall Time VCC = 5.0V 15 µs VCC = 10V 5.0 µs fMAX Maximum Clock Frequency V CC = 5.0V 2.0 4.0 MHz VCC = 10V 5.0 10 MHz C CK Clock Input Capacitance Clock Input (Note 3) 10 pF C IN Input Capacitance Any other Input (Note 3) 5 pF C PD Power Dissipation Capacitance (Note 4) 100 pF

5 www.fairchildsemi.com MM74C905 Timing Diagram

www.fairchildsemi.com 6 MM74C905 Switching Time Waveforms USER NOTES FOR A/D CONVERSION The register can be used with either current switches that require a low voltage level to turn the switch ON or current switches that require a high voltage level to turn the switch ON. If current switches are used which turn ON with a low logic level, the resulting digit output from the register is active low. That is, a logic “1” is represented as a low volt- age level. If current switches are used which turn ON with a high logic level, the resulting digit output is active high. A logic “1” is represented as a high voltage level. For a maximum error of ±½ LSB, the comparator must be biased. If current switches that require a high voltage level to turn ON are used, the comparator should be biased +½ LSB and if the current switches require a low logic level to turn ON, then the comparator must be biased −½ LSB. The register can be used to perform 2's complement con- version by offsetting the comparator one half full range +½ LSB and using the complement of the MSB Q11 as the sign bit. If the register is truncated and operated in the continuous conversion mode, a lock-up condition may occur on power- ON. This situation can be overcome by making the START input the “OR ” function of CC and the appropriate register output. The register, by suitable selection of register ladder net- work, can be used to perform either binary or BCD conver- sion. The register outputs can drive the 10 bits or less with 50k/ 100k R/2R ladder network directly for V CC = 10V or higher. In order to drive the 12-bit 50k/100k ladder network and have the ±½ LSB resolution, the MM74C902 or MM74C904 is used as buffers, three buffers for MSB (Q11), two buffers for Q10, and one buffer for Q9.

7 www.fairchildsemi.com MM74C905 Typical Applications 12-Bit Successive Approximation A-to-D Converter, Operating in Continuous 8–Bit Truncated Mode 12-Bit Successive Approximation A-to-D Converter, Operating in Continuous Mode, Drives the 50k/100k Ladder Network Directly Definition of Terms CP: Register clock input. CC: Conversion complete— this output remains at VOUT(1) during a conversion and goes to VOUT(0) when conversion is complete. D: Serial data input— connected to comparator output in A- to-D applications. E: Register enable — this input is used to expand the length of the register. When E is at VIN(1) Q11 is forced to VOUT(1) and inhibits conversion. When not used for expan- sion E must be connected to VIN(0) (GND). Q11: True register MSB output. Q 11: Complement of register MSB output. Qi (i = 0 to 11): Register outputs. S: Start input— holding start input at VIN(0) for at least one clock period will initiate a conversion by setting MSB (Q11) at VOUT(0) and all other output (Q10–Q0) at VOUT(1). If set- up time requirements are met, a conversion may be initi- ated by holding start input at VIN(0) for less than one clock period. DO: Serial data output— D input delayed by one clock period.

www.fairchildsemi.com 8 MM74C905 12-Bit Successive Approximation Register Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide Package Number N24A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com