MM74C901

MM74C901 FAIRCHILD | Alldatasheet

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■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: 1.0V ■ High noise immunity: 0.45 VCC (typ.) ■ TTL compatibility: Fan out of 2 driving standard TTL Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC MM74C901 Top View MM74C902 Top View Logic Diagrams MM74C901 CMOS to TTL Inverting Buffer MM74C902 CMOS to TTL Buffer Order Number Package Number Package Description MM74C901M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C901N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide MM74C902M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C902N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide

www.fairchildsemi.com 2 MM74C901 • MM74C902 Absolute Maximum Ratings(Note 1) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise noted Voltage at Any Pin −0.3V to VCC + 0.3V Voltage at Any Input Pin MM74C901 −0.3V to +15V MM74C902 −0.3V to +15V Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Operating Temperature Range (T MM74C901, MM74C902, −40°C to +85°C Operating VCC Range 3.0V to 15V Absolute Maximum VCC 18V Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS V IN(1) Logical “1” Input Voltage V CC = 5.0V 3.5 V V CC = 10V 8.0 V V IN(0) Logical “0” Input Voltage V CC = 5.0V 1.5 V V CC = 10V 2.0 V V OUT(1) Logical “1” Output Voltage V CC = 5.0V, IO = −10 µA4 . 5 V V CC = 10V, IO = −10 µA9 . 0 V V OUT(0) Logical “0” Output Voltage V CC = 5.0V 0.5 V V CC = 10V 1.0 V I IN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 µA I IN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA I CC Supply Current V CC = 15V 0.05 15 µA TTL TO CMOS V IN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 V V IN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V CMOS TO TTL V IN(1) Logical “1” Input Voltage MM74C901 V CC = 4.75V 4.25 V MM74C902 V CC = 4.75V V CC − 1.5 V V IN(0) Logical “0” Input Voltage MM74C901 V CC = 4.75V 1.0 V MM74C902 V CC = 4.75V 1.5 V V OUT(1) Logical “1” Output Voltage V CC = 4.75V, IO = −800 µA2 . 4 V V OUT(0) Logical “0” Output Voltage MM74C901 V CC = 4.75V, IO = 2.6 mA 0.4 V MM74C902 V CC = 4.75V, IO = 3.2 mA 0.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) (MM74C901) I SOURCE Output Source Current V CC = 5.0V, VOUT = 0V −5.0 mA (P-Channel) T A = 25°C, VIN = 0V I SOURCE Output Source Current V CC = 10V, VOUT = 0V −20 mA (P-Channel) T A = 25°C, VIN = 0V I SINK Output Sink Current V CC = 5.0V, VOUT = VCC 9.0 mA (N-Channel) T A = 25°C, VIN = VCC I SINK Output Sink Current V CC = 5.0V, VOUT = 0.4V 3.8 mA (N-Channel) T A = 25°C, VIN = VCC (MM74C902)

3 www.fairchildsemi.com MM74C901 • MM74C902 TA = 25°C, CL = 50 pF , unless otherwise noted Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. Typical Application CMOS to TTL or CMOS at a Lower VCC Note: VCC1 = VCC2 Symbol Parameter Conditions Min Typ Max Units I SOURCE Output Source Current V CC = 5.0V, VOUT = 0V −5.0 mA (P-Channel) T A = 25°C, VIN = VCC I SOURCE Output Source Current V CC = 10V, VOUT = 0V −20 mA (P-Channel) T A = 25°C, VIN = VCC I SINK Output Sink Current V CC = 5.0V, VOUT = VCC 9.0 mA (N-Channel) T A = 25°C, VIN = 0V I SINK Output Sink Current V CC = 5.0V, VOUT = 0.4V 3.8 mA (N-Channel) T A = 25°C, VIN = 0V Symbol Parameter Conditions Min Typ Max Units MM74C901 t pd1 Propagation Delay Time V CC = 5.0V 38 70 ns to a Logical “1” V CC = 10V 22 30 ns t pd0 Propagation Delay Time V CC = 5.0V 21 35 ns to a Logical “0” V CC = 10V 13 20 ns C IN Input Capacitance Any Input (Note 3) 14 pF C PD Power Dissipation Capacity Per Buffer (Note 4) 30 pF MM74C902 t pd1 Propagation Delay Time V CC = 5.0V 57 90 ns to a Logical “1” V CC = 10V 27 40 ns t pd0 Propagation Delay Time V CC = 5.0V 54 90 ns to a Logical “0” V CC = 10V 25 40 ns C IN Input Capacitance Any Input (Note 3) 5.0 pF C PD Power Dissipation Capacity Per Buffer (Note 4) 50 pF

www.fairchildsemi.com 4 MM74C901 • MM74C902 AC Test Circuit and Switching Time Waveforms Note: Delays measured with input tr, tf = 20 ns. CMOS to CMOS Typical Performance Characteristics Typical Propagation Delay to a Logical “0” for the MM74C901 Typical Propagation Delay to a Logical “1” for the MM74C901 Typical Propagation Delay to a Logical “0” for the MM74C902 Typical Propagation Delay to a Logical “1” for the MM74C902

5 www.fairchildsemi.com MM74C901 • MM74C902 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-120, 0.150” Narrow Package Number M14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL Buffer LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A