MM74C90

MM54C90 TI1 | Alldatasheet

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Technical content

MM54C90,MM54C93,MM74C90,MM74C93 MM54C90 MM74C90 4-Bit Decade Counter MM54C93 MM74C93 4-Bit Binary Counter Literature Number: SNOS340A

MM54C90/MM74C90 4-Bit Decade Counter MM54C93/MM74C93 4-Bit Binary Counter February 1988 MM54C90/MM74C90 4-Bit Decade Counter MM54C93/MM74C93 4-Bit Binary Counter General Description The MM54C90/MM74C90 decade counter and the MM54C93/MM74C93 binary counter and complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. The 4-bit decade counter can reset to zero or preset to nine by applying ap- propriate logic level on the R 01,R 02,R 91 and R 92 inputs. Also, a separate flip-flop on the A-bit enables the user to operate it as a divide-by-2, 5 or 10 frequency counter. The 4-bit binary counter can be reset to zero by applying high logic level on inputs R 01 and R 02, and a separate flip-flop on the A-bit enables the user to operate it as a divide-by-2, -8, or -16 divider. Counting occurs on the negative going edge of the input pulse. All inputs are protected against static discharge damage.

Features

Y Wide supply voltage range 3V to 15V Y Guaranteed noise margin 1V Y High noise immunity 0.45 V CC (typ.) Y Low power Fan out of 2 TTL compatiblity driving 74L Y The MM54C93/MM74C93 follows the MM54L93/ MM74L93 Pinout Connection and Logic Diagrams MM54C90/MM74C90 Dual-In-Line Package TL/F/5889–2 Top View MM54C93/MM74C93 Dual-In-Line Package TL/F/5889–4 Top View Order Number MM54C90 or MM74C93 M54C90/MM74C90 TL/F/5889–1 MM54C93/MM74C93 TL/F/5889–3 C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Obsolete

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin (Note 1) b0.3V to V CC a0.3V Operating Temperature Range (T A) MM54C90, MM54C93 b55§Ct o a125§C MM74C90, MM74C93 b40§Ct o a85§C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3V to 15V Absolute Maximum V CC 18V Storage Temperature Range (T S) b65§Ct o a150§C Lead Temperature (T L) (Soldering, 10 seconds) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5V 3.5 V VCC e 10V 8.0 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5V, I O eb 10 mA 4.5 V VCC e 10V, I O eb 10 mA 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5V, I O ea 10 mA 0.5 V VCC e 10V, I O ea 10 mA 1.0 V IIN(1) Logical ‘‘1’’ Input Current V CC e 15V, V IN e 15V 0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V CC e 15V, V IN e 0V b1.0 b0.005 mA ICC Supply Current VCC e 15V 0.05 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage MM54C90, MM54C93 V CC e 4.5V VCCb1.5 V MM74C90, MM74C93 V CC e 4.75V VCCb1.5 V VIN(0) Logical ‘‘0’’ Input Voltage MM54C90, MM54C93 V CC e 4.5V 0.8 V MM74C90, MM74C93 V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage MM54C90, MM54C93 V CC e 4.5V, I O eb 360 mA 2.4 V MM74C90, MM74C93 V CC e 4.75V, I O eb 360 mA 2.4 V VOUT(0) Logical ‘‘0’’ Output Voltage MM54C90, MM54C93 V CC e 4.5V, I O eb 360 mA 0.4 V MM74C90, MM74C93 V CC e 4.75V, I O eb 360 mA 0.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC e 5V, V OUT e 0V b1.75 b3.3 mA(P-Channel) TA e 25§C ISOURCE Output Source Current V CC e 10V, V OUT e 0V b8.0 b15 mA(P-Channel) TA e 25§C ISINK Output Sink Current VCC e 5V, V OUT e VCC 1.75 3.6 mA(N-Channel) TA e 25§C ISINK Output Sink Current VCC e 10V, V OUT e VCC 8.0 16 mA(N-Channel) TA e 25§C Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’, they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Symbol Parameter Conditions Min Typ Max Units tpd0,t pd1 Propagation Delay Time VCC e 5V 200 400 ns from A IN to Q A VCC e 10 80 150 ns tpd0,t pd1 Propagation Delay Time from VCC e 5V 450 850 ns AIN to Q B (MM54C93/MM74C93) V CC e 10V 160 300 ns tpd0,t pd1 Propagation Delay Time from VCC e 5V 450 800 ns AIN to Q B (MM54C90/MM74C90) V CC e 10V 160 300 ns Obsolete

Symbol Parameter Conditions Min Typ Max Units tpd0,t pd1 Propagation Delay Time VCC e 5V 500 1050 ns from A IN to Q C (MM54C93/MM74C93) V CC e 10 200 400 ns tpd0,t pd1 Propagation Delay Time from VCC e 5V 500 1000 ns AIN to Q C (MM54C93/MM74C93) VCC e 10V 200 400 ns tpd0,t pd1 Propagation Delay Time from VCC e 5V 600 1200 ns AIN to Q D (MM54C93/MM74C93) VCC e 10V 250 500 ns tpd0,t pd1 Propagation Delay Time from VCC e 5V 450 800 ns AIN to Q D (MM54C90/MM74C90) VCC e 10V 160 300 ns tpd0,t pd1 Propagation Delay Time from VCC e 5V 150 300 ns R01 or R 02 to Q A,Q B,Q C or Q D VCC e 10V 75 150 ns (MM54C93/MM74C93) tpd0,t pd1 Propagation Delay Time from VCC e 5V 200 400 ns R01 or R 02 to Q A,Q B,Q C or Q D VCC e 10V 75 150 ns (MM54C90/MM74C90) tpd0,t pd1 Propagation Delay Time from VCC e 5V 250 500 ns R91 or R 92 to Q A or Q D VCC e 10V 100 200 ns (MM54C90/MM74C90) tPW Min. R 01 or R 02 Pulse Width VCC e 5V 600 250 ns (MM54C93/MM74C93) VCC e 10V 30 125 ns tPW Min. R 01 or R 02 Pulse Width VCC e 5V 600 250 ns (MM54C90/MM74C90) VCC e 10V 300 125 ns tPW Min. R 91 or R 92 Pulse Width VCC e 5V 500 200 ns (MM54C90/MM74C90) VCC e 10V 250 100 ns tr,t f Maximum Clock Rise VCC e 10V 15 ms and Fall Time V CC e 10V 5 ms tW Minimum Clock Pulse Width VCC e 5V 250 100 ns VCC e 10V 100 50 ns fMAX Maximum Clock Frequency VCC e 5V 2 MHz VCC e 10V 5 MHz CIN Input Capacitance Any Input (Note 2) 5 pF CPD Power Dissipation Capacitance Per Package (Note 3) 45 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’, they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application noteÐ AN-90. AC Test Circuits MM54C90/MM74C90 TL/F/5889–5 Clock rise and fall time t r e tf e 20 ns MM54C93/MM74C93 TL/F/5889–6 Clock rise and fall time t r e tf e 20 ns Obsolete

TL/F/5889–7 Note 1: MM54C90, MM74C90 and MM54C93, MM74C93 are solid line waveforms. Dashed line waveforms are for MM54C90/MM74C90 only. Truth Table MM54C90/MM74C90 4-Bit Decade Counter BCD Count Sequence Count Output QD QC QB QA 0L L L L 1L L L H 2L L H L 3L L H H 4L H L L 5L H L H 6L H H L 7L H H H 8H L L L 9H L L H Output Q A is connected to Input B for BCD count. H e High Level L e Low Level X e Irrelevant Reset/Count Function Table Reset Inputs Output R01 R02 R91 R92 QD QC QB QA HHL XL L L L HHX LL L L L XXHH H L L H X L X L Count L X L X Count L X X L Count X L L X Count MM54C93/MM74C93 4-Bit Binary Counter Binary Count Sequence Count Output QD QC QB QA 0L L L L 1L L L H 2L L H L 3L L H H 4L H L L 5L H L H 6L H H L 7L H H H 8H L L L 9H L L H

10 H L H L

11 H L H H

12 H H L L

13 H H L H

14 H H H L

15 H H H H

Output Q A is connected to input B for binary count sequence. H e High Level L e Low Level X e Irrelevant Reset/Count Function Table Reset OutputInputs R01 R02 QD QC QB QA HHL L L L L X Count X L Count Obsolete

Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C90J, MM54C93J, MM74C90J or MM74C93J Obsolete

MM54C90/MM74C90 4-Bit Decade Counter MM54C93/MM74C93 4-Bit Binary Counter Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C90N, MM54C93N, MM74C90N or MM74C93N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Obsolete

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