MM74C90

MM74C90 FAIRCHILD | Alldatasheet

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I Wide supply voltage range: 3V to 15V I Guaranteed noise margin: 1V I High noise immunity: 0.45 VCC (typ.) I Low power compatibility: Fan out of 2 TTL driving 74L I The MM74C93 follows the MM74L93 Pinout Ordering Code: Connection Diagram Top View Logic Diagram Truth Table 4-Bit Binary Counter Binary Count Sequence Output QA is connected to input B for binary count sequence. H = HIGH Level L = LOW Level X = Irrelevant Order Number Package Number Package Description MM74C93N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Count Output Q D Q C Q B Q A

0 LLLL

8 HLLL

11 H L H H

12 H H L L

13 H H L H

www.fairchildsemi.com 2 MM74C93 Function Tables Reset/Count Function Table Reset/Count Function Table Reset Inputs Output R 01 R 02 R 91 R 92 Q D Q C Q B Q A H HLXLLLL H H XLLLLL XXHHHLLH X L X L Count LXLX C o u n t L X X L Count X L L X Count Reset Output Inputs R

01 R 02 Q D Q C Q B Q A

3 www.fairchildsemi.com MM74C93 Absolute Maximum Ratings(Note 1) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range”, they are not meant to imply that the devices should be oper- ated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Voltage at Any Pin (Note 1) −0.3V to VCC +0.3V Operating Temperature Range (TA) −55°C to +125°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range 3V to 15V Absolute Maximum VCC 18V Storage Temperature Range (TS) −65°C to +150°C Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5V 3.5 V VCC = 10V 8.0 VIN(0) Logical “0” Input Voltage V CC = 5V 1.5 V VCC = 10V 2.0 VOUT(1) Logical “1” Output Voltage V CC = 5V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 VOUT(0) Logical “0” Output Voltage V CC = 5V, IO = +10 µA0 . 5 V VCC = 10V, IO = +10 µA1 . 0 IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.05 300 µA CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage MM74C90, MM74C93 V CC = 4.75V V CC −1.5 V VIN(0) Logical “0” Input Voltage MM74C90, MM74C93 V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage MM74C90, MM74C93 V CC = 4.75V, IO = −360 µA2 . 4 V VOUT(0) Logical “0” Output Voltage MM74C90, MM74C93 V CC = 4.75V, IO = −360 µA0 . 4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC = 5V, VOUT = 0V −1.75 −3.3 mA (P-Channel) T A = 25°C ISOURCE Output Source Current V CC = 10V, VOUT = 0V −8.0 −15 mA (P-Channel) T A = 25°C ISINK Output Sink Current V CC = 5V, VOUT = VCC 1.75 3.6 mA (N-Channel) T A = 25°C ISINK Output Sink Current V CC = 10V, VOUT = VCC 8.0 16 mA (N-Channel) T A = 25°C

www.fairchildsemi.com 4 MM74C93 TA = 25°C, CL = 50 pF, unless otherwise specified Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load ac power consumption of any CMOS device. For complete explanation see Family Characteristics application note— AN-90. Symbol Parameter Conditions Min Typ Max Units tpd0, tpd1 Propagation Delay Time V CC = 5V 200 400 ns from AIN to QA VCC = 10 80 150 tpd0, tpd1 Propagation Delay Time from V CC = 5V 450 850 ns AIN to QB (MM74C93) V CC = 10V 160 300 tpd0, tpd1 Propagation Delay Time from V CC = 5V 450 800 ns AIN to QB (MM74C90) V CC = 10V 160 300 tpd0, tpd1 Propagation Delay Time V CC = 5V 500 1050 ns from AIN to QC (MM74C93) V CC = 10 200 400 tpd0, tpd1 Propagation Delay Time from V CC = 5V 500 1000 ns AIN to QC (MM74C93) V CC = 10V 200 400 tpd0, tpd1 Propagation Delay Time from V CC = 5V 600 1200 ns AIN to QD (MM74C93) V CC = 10V 250 500 tpd0, tpd1 Propagation Delay Time from V CC = 5V 450 800 ns AIN to QD (MM74C90) V CC = 10V 160 300 tpd0, tpd1 Propagation Delay Time from V CC = 5V 150 300 ns R 01 or R02 to QA, QB, QC or QD VCC = 10V 75 150 (MM74C93) tpd0, tpd1 Propagation Delay Time from V CC = 5V 200 400 ns R 01 or R02 to QA, QB, QC or QD VCC = 10V 75 150 (MM74C90) tpd0, tpd1 Propagation Delay Time from V CC = 5V 250 500 ns R 91 or R92 to QA or QD VCC = 10V 100 200 (MM74C90) tPW Min. R01 or R02 Pulse Width V CC = 5V 600 250 ns (MM74C93) V CC = 10V 30 125 tPW Min. R01 or R02 Pulse Width V CC = 5V 600 250 ns (MM74C90) V CC = 10V 300 125 tPW Min. R91 or R92 Pulse Width V CC = 5V 500 200 ns (MM74C90) V CC = 10V 250 100 tr, tf Maximum Clock Rise V CC = 10V 15 µs and Fall Time V CC = 10V 5 tW Minimum Clock Pulse Width V CC = 5V 250 100 ns VCC = 10V 100 50 fMAX Maximum Clock Frequency V CC = 5V 2 MHz VCC = 10V 5 C IN Input Capacitance Any Input (Note 3) 5 pF C PD Power Dissipation Capacitance Per Package (Note 4) 45 pF

5 www.fairchildsemi.com MM74C93 AC Test Circuits Clock rise and fall time tr = tf = 20 ns Switching Time Waveforms MM74C90 and MM74C93 are solid line waveforms. Dashed line waveforms are for MM74C90 only.

www.fairchildsemi.com 6 MM74C93 4-Bit Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com