MM74C89N

MM54C89 NSC | Alldatasheet

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Y Wide supply voltage range 3.0V to 15V Y Guaranteed noise margin 1.0V Y High noise immunity 0.45 V CC (typ.) Y Low power fan out of 2 TTL compatibility driving 74L Y Low power consumption 100 nW/package (typ.) Y Fast access time 130 ns (typ.) at V CC e 10V Y TRI-STATE output Logic and Connection Diagrams TL/F/5888–1 Dual-In-Line Package TL/F/5888–2Top View Order Number MM54C89 or MM74C89 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at any Pin b0.3V to V CC a0.3V Operating Temperature Range MM54C89 b55§Ct o a125§C MM74C89 b40§Ct o a85§C Storage Temperature Range (T S) b65§Ct o a150§C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3.0V to 15V Absolute Maximum V CC 18V Lead Temperature (T L) (Soldering, 10 seconds) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5.0V 3.5 V VCC e 10V 8.0 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5.0V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5.0V, I O eb 10 mA 4.5 V VCC e 10V, I O eb 10 mA 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5.0V, I O ea 10 mA 0.5 V VCC e 10V, I O ea 10 mA 1.0 V IIN(1) Logical ‘‘1’’ Input Current V CC e 15V, V IN e 15V b0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V CC e 15V, V IN e 0V b1.0 b0.005 mA IOZ Output Current in High V CC e 15V, V e 15V 0.005 1.0 mA Impedance State V CC e 15V, V O e 0V b1.0 b0.005 mA ICC Supply Current V CC e 15V 0.05 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, V CC e 4.5V V CC b 1.5 V 74C, V CC e 4.75V V CC b 1.5 V VIN(0) Logical ‘‘0’’ Input Voltage 54C, V CC e 4.5V 0.8 V 74C, V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, V CC e 4.5V, I O eb 360 mA 2.4 V 74C, V CC e 4.75V, I O eb 360 mA 2.4 V VOUT(0) Logical ‘‘0’’ Output Voltage 54C, V CC e 4.5V, I O ea 360 mA 0.4 V 74C, V CC e 4.75V, I O ea 360 mA 0.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC e 5.0V, V OUT e 0V b1.75 b3.3 mA(P-Channel) T A e 25§C ISOURCE Output Source Current V CC e 10V, V OUT e 0V b8.0 b15 mA(P-Channel) T A e 25§C ISINK Output Sink Current V CC e 5.0V, V OUT e VCC 1.75 3.6 mA(N-Channel) T A e 25§C ISINK Output Sink Current V CC e 10V, V OUT e VCC 8.0 16 mA(N-Channel) T A e 25§C Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay from V CC e 5V 270 500 ns Memory Enable V CC e 10V 100 220 ns tACC Access Time from V CC e 5V 350 650 ns Address Input V CC e 10V 130 280 ns tSA Address Setup Time V CC e 5V 150 ns VCC e 10V 60 ns tHA Address Hold Time V CC e 5V 60 ns VCC e 10V 40 ns tME Memory Enable Pulse Width V CC e 5V 400 250 ns VCC e 10V 150 90 ns

Symbol Parameter Conditions Min Typ Max Units tSR Write Enable Setup V CC e 5V 0 ns Time for a Read V CC e 10V 0 ns tWS Write Enable Setup V CC e 5V t ME ns Time for a Write V CC e 10V t ME ns tWE Write Enable Pulse Width V CC e 5V, t WS e 0 300 160 ns VCC e 10V, t WS e 0 100 60 ns tHD Data Input Hold Time V CC e 5V 50 ns VCC e 10V 25 ns tSD Data Input Setup V CC e 5V 50 ns VCC e 10V 25 ns t1H,t 0H Propagation Delay from a Logical V CC e 5V, C L e 5 pF, R L e 10k 180 300 ns ‘‘1’’ or Logical ‘‘0’’ to the High V CC e 10V, C L e 5 pF, R L e 10k b85 120 ns Impedance State from Memory Enable t1H,t 0H Propagation Delay from a Logical V CC e 50V, C L e 5 pF, R L e 10k 180 300 ns ‘‘1’’ or Logical ‘‘0’’ to the High V CC e 10V, C L e 5 pF, R L e 10k 85 120 ns Impedance State from Write Enable CIN Input Capacity Any Input (Note 2) 5 pF COUT Output Capacity Any Output (Note 2) 6.5 pF CPD Power Dissipation Capacity (Note 3) 230 pF *AC Parameters are guaranteed by DC correlated testing. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note, AN-90. MM54C89 MM74C89 Parameter Conditions T A eb 55§Ct o a125§CT A eb 40§Ct o a85§C Units Min Max Min Max tPD VCC e 5V 700 600 ns VCC e 10V 310 265 ns VCC e 15V 250 210 ns tACC VCC e 5V 910 780 ns VCC e 10V 400 345 ns VCC e 15V 320 270 ns tSA VCC e 5V 210 180 ns VCC e 10V 90 80 ns VCC e 15V 70 60 ns tHA VCC e 5V 80 70 ns VCC e 10V 55 50 ns VCC e 15V 45 40 ns tME VCC e 5V 560 480 ns VCC e 10V 210 180 ns VCC e 15V 170 150 ns tWE VCC e 5V 420 360 ns VCC e 10V 140 120 ns VCC e 15V 110 100 ns tHD VCC e 5V 70 60 ns VCC e 10V 35 30 ns VCC e 15V 30 25 ns *AC Parameters are guaranteed by DC correlated testing.

Guaranteed across the specified temperature range, C L e 50 pF (Continued) MM54C89 MM74C89 Parameter Conditions T A eb 55§Ct o a125§CT A eb 40§Ct o a85§C Units Min Max Min Max tSD VCC e 5V 70 60 ns VCC e 10V 35 30 ns VCC e 15V 30 25 ns t1H,t 0H VCC e 5V 420 360 ns VCC e 10V, C L e 5 pF 170 145 ns VCC e 15V, R L e 10 k X 135 115 ns *AC Parameters are guaranteed by DC correlated testing. Truth Table ME WE Operation Condition of Outputs L L Write TRI-STATE L H Read Complement of Selected Word H L Inhibit, Storage TRI-STATE H H Inhibit, Storage TRI-STATE AC Test Circuits t0H TL/F/5888–4 t1H TL/F/5888–3 Switching Time Waveforms t0H TL/F/5888–5 t1H TL/F/5888–6 Read Cycle TL/F/5888–7 Write Cycle TL/F/5888–8

Switching Time Waveforms (Continued) Read Modify Write Cycle TL/F/5888–9 Note: tr e 60 ns tf e 10 ns

MM54C89/MM74C89 64-Bit TRI-STATE Random Access Read/Write Memory Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C89J or MM74C89J Molded Dual-In-Line Package (N) Order Number MM54C89N or MM74C89N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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