MM74C89N

MM74C89 FAIRCHILD | Alldatasheet

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Features

■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: 1.0V ■ High noise immunity: 0.45 VCC (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L ■ Low power consumption: 100 nW/package (typ.) ■ Fast access time: 130 ns (typ.) at VCC = 10V ■ 3-STATE output Note: The timing is different than the DM7489 in that a positive to negative transition of the memory enable must occur for the memory to be selected. Ordering Code: Connection Diagram Pin Assignments for DIP Top View Truth Table Order Number Package Number Package Description MM74C89N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide ME WE Operation Condition of Outputs LL W r i t e 3 - S T A T E L H Read Complement of Selected Word H L Inhibit, Storage 3-STATE H H Inhibit, Storage 3-STATE

www.fairchildsemi.com 2 MM74C89 Logic Diagram

3 www.fairchildsemi.com MM74C89 Absolute Maximum Ratings(Note 1) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Min/Max limits apply across temperature range, unless otherwise noted Voltage at any Pin −0.3V to VCC +0.3V Operating Temperature Range −40°C to +85°C Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3.0V to 15V Absolute Maximum VCC 18V Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5.0V 3.5 V VCC = 10V 8.0 V VIN(0) Logical “0” Input Voltage V CC = 5.0V 1.5 V VCC = 10V 2.0 V VOUT(1) Logical “1” Output Voltage V CC = 5.0V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 V VOUT(0) Logical “0” Output Voltage V CC = 5.0V, IO = +10 µA0 . 5 V VCC = 10V, IO = +10 µA1 . 0 V IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V −0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA IOZ Output Current in High V CC = 15V, V = 15V 0.005 1.0 µA Impedance State V CC = 15V, VO = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.05 300 µA CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 V VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage V CC = 4.75V, IO = −360 µA2 . 4 V VOUT(0) Logical “0” Output Voltage V CC = 4.75V, IO = +360 µA0 . 4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC = 5.0V, VOUT = 0V −1.75 −3.3 mA (P-Channel) T A = 25°C ISOURCE Output Source Current V CC = 10V, VOUT = 0V −8.0 −15 mA (P-Channel) T A = 25°C ISINK Output Sink Current V CC = 5.0V, VOUT = VCC 1.75 3.6 mA (N-Channel) T A = 25°C ISINK Output Sink Current V CC = 10V, VOUT = VCC 8.0 16 mA (N-Channel) T A = 25°C

www.fairchildsemi.com 4 MM74C89 TA = 25°C, CL = 50 pF , unless otherwise noted Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note, AN-90. Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay from V CC = 5V 270 500 ns Memory Enable V CC = 10V 100 220 ns tACC Access Time from V CC = 5V 350 650 ns Address Input V CC = 10V 130 280 ns tSA Address Setup Time V CC = 5V 150 ns VCC = 10V 60 ns tHA Address Hold Time V CC = 5V 60 ns VCC = 10V 40 ns tME Memory Enable Pulse Width V CC = 5V 400 250 ns VCC = 10V 150 90 ns tSR Write Enable Setup V CC = 5V 0 ns Time for a Read V CC = 10V 0 ns tWS Write Enable Setup V CC = 5V t ME ns Time for a Write V CC = 10V t ME ns tWE Write Enable Pulse Width V CC = 5V, tWS = 0 300 160 ns VCC = 10V, tWS = 0 100 60 ns tHD Data Input Hold Time V CC = 5V 50 ns VCC = 10V 25 ns tSD Data Input Setup V CC = 5V 50 ns VCC = 10V 25 ns t1H , t0H Propagation Delay from a Logical VCC = 5V, CL = 5 pF , RL = 10k 180 300 ns “1” or Logical “0” to the High V CC = 10V, CL = 5 pF , RL = 10k −85 120 ns Impedance State from Memory Enable t1H , t0H Propagation Delay from a Logical VCC = 50V, CL = 5 pF , RL = 10k 180 300 ns “1” or Logical “0” to the High V CC = 10V, CL = 5 pF , RL = 10k 85 120 ns Impedance State from Write Enable C IN Input Capacity Any Input (Note 3) 5 pF C OUT Output Capacity Any Output (Note 3) 6.5 pF C PD Power Dissipation Capacity (Note 4) 230 pF

5 www.fairchildsemi.com MM74C89 AC Test Circuits t0H t1H Switching Time Waveforms t0H t1H Read Cycle Write Cycle Read Modify Write Cycle tf = 10 ns tr = 60 ns

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C89 64-Bit 3-STATE Random Access Read/Write Memory LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E