MM74C85N

MM54C85 NSC | Alldatasheet

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Features

Y Wide supply voltage range 3.0V to 15V Y Guaranteed noise margin 1.0V Y High noise immunity 0.4 V CC (typ.) Y Low power fan out of 2 TTL compatibility driving 74L Y Expandable to ‘N’ stages Y Applicable to binary or BCD Y Low power pinout: 54L85/74L85 Logic Diagram TL/F/5886–1 C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin b0.3V to V CC a 0.3V Operating Temperature Range MM54C85 b55§Ct o a125§C MM74C85 b40§Ct o a85§C Storage Temperature Range b65§Ct o a150§C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3.0V to 15V VCC 18V Lead Temperature (Soldering, 10 seconds) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5.0V 3.5 V VCC e 10V 8.0 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5.0V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5.0V, I O eb 10 mA 4.5 V VCC e 10V, I O eb 10 mA 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5.0V, I O ea 10 mA 0.5 V VCC e 10V, I O ea 10 mA 1.0 V IIN(1) Logical ‘‘1’’ Input Current V CC e 15V, V IN e 15V 0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V CC e 15V, V IN e 0V b1.0 b0.005 mA ICC Supply Current V CC e 15V 0.05 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, V CC e 4.5V V CC b 1.5 V 74C, V CC e 4.75V V CC b 1.5 V VIN(0) Logical ‘‘0’’ Input Voltage 54C, V CC e 4.5V 0.8 V 74C, V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, V CC e 4.5V, I O eb 360 mA 2.4 V 74C, V CC e 4.75V, I O eb 360 mA 2.4 V VOUT(0) Logical ‘‘0’’ Output Voltage 54C, V CC e 4.5V, I O e 360 mA 0.4 V 74C, V CC e 4.75V, I O e 360 mA 0.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC e 5.0V, V OUT e 0V b1.75 b3.3 mA(P-Channel) T A e 25§C ISOURCE Output Source Current V CC e 10V, V OUT e 0V b8.0 b15 mA(P-Channel) T A e 25§C ISINK Output Sink Current V CC e 5.0V, V OUT e VCC 1.75 3.6 mA(N-Channel) T A e 25§C ISINK Output Sink Current V CC e 10V, V OUT e VCC 8.0 16 mA(N-Channel) T A e 25§C Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay from any A V CC e 50V 250 600 ns or B Data Input to any V CC e 10V 100 300 ns Data Output tpd Propagation Delay Time from V CC e 50V 200 500 ns any Cascade Input to V CC e 10V 100 250 ns any Output CIN Input Capacitance Any Inupt 5.0 pF CPD Power Dissipation Capacitance (Note 3) Per Package 45 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note, AN-90.

TL/F/5886–2 Connection Diagram Dual-In-Line Package TL/F/5886–3 Top View Order Number MM54C85 or MM74C85 Switching Time Waveforms TL/F/5886–4 Unused inputs must be tied to an appropriate logic level. Truth Table Comparing Inputs Cascading Inputs Outputs A3, B3 A2, B2 A1, B1 A0, B0 A l BA k BA e BA l BA k BA e B A3 l B3 X X X X X X H L L A3 k B3 X X X X X X L H L A3 e B3 A2 l B2 X X X X X H L L A3 e B3 A2 k B2 X X X X X L H L A3 e B3 A2 e B2 A1 l B1 X X X X H L L A3 e B3 A2 e B2 A1 k B1 X X X X L H L A3 e B3 A2 e B2 A1 e B1 A0 l B0 X X X H L L A3 e B3 A2 e B2 A1 e B1 A0 k B0 X X X L H L A3 e B3 A2 e B2 A1 e B1 A0 e B0 H L L H L L A3 e B3 A2 e B2 A1 e B1 A0 e B0 L H L L H L A3 e B3 A2 e B2 A1 e B1 A0 e B0 L L H L L H A3 e B3 A2 e B2 A1 e B1 A0 e B0 L H H L H H A3 e B3 A2 e B2 A1 e B1 A0 e B0 H L H H L H A3 e B3 A2 e B2 A1 e B1 A0 e B0 H H H H H H A3 e B3 A2 e B2 A1 e B1 A0 e B0 H H L H H L A3 e B3 A2 e B2 A1 e B1 A0 e B0 L L L L L L H e high level, L e low level, X e irrelevant

MM54C85/MM74C85 4-Bit Magnitude Comparator Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C85J or MM74C85J Molded Dual-In-Line Package (N) Order Number MM54C85N or MM74C85N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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