MM74C74 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I Supply voltage range: 3V to 15V I Tenth power TTL compatible: Drive 2 LPT2L loads I High noise immunity: 0.45 VCC (typ.) I Low power: 50 nW (typ.) I Medium speed operation: 10 MHz (typ.) with 10V supply

Applications

  • Automotive  Data terminals  Instrumentation  Medical electronics  Alarm system  Industrial electronics  Remote metering  Computers Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Note: A logic “0” on clear sets Q to logic “0”. A logic “0” on preset sets Q to logic “1”. Top View Truth Table Note 1: No change in output from previous state. Order Number Package Number Package Description MM74C74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74C74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Preset Clear Q n Q n 0000 0110 1001 11 Q n (Note 1) Q n (Note 1)

www.fairchildsemi.com 2 MM74C74 Logic Diagram

3 www.fairchildsemi.com MM74C74 Absolute Maximum Ratings(Note 2) Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise noted Voltage at Any Pin (Note 2) −0.3V to VCC +0.3V Operating Temperature Range −55°C to +125°C Storage Temperature Range −65°C to +150°C Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (Soldering, 10 seconds) 260 Operating VCC Range 3V to 15V VCC (Max) 18V Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5V 3.5 V VCC = 10V 80 VIN(0) Logical “0” Input Voltage V CC = 5V 1.5 V VCC = 10V 2.0 VOUT(1) Logical “1” Output Voltage V CC = 5V 4.5 V VCC = 10V 9.0 VOUT(0) Logical “0” Output Voltage V CC = 5V 0.5 V VCC = 10V 1.0 IIN(1) Logical “1” Input Current V CC = 15V 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V −1.0 µA ICC Supply Current V CC = 15V 0.05 60 µA CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage V CC = 4.75V, ID = −360 µA2 . 4 V VOUT(0) Logical “0” Output Voltage V CC = 4.75V, ID = 360 µA0 . 4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) ISOURCE Output Source Current V CC = 5V, VIN(0) = 0V −1.75 mA TA = 25°C, VOUT = 0V ISOURCE Output Source Current V CC = 10V, VIN(0) = 0V −8.0 mA TA = 25°C, VOUT = 0V ISINK Output Sink Current V CC = 5V, VIN(1) = 5V 1.75 mA TA = 25°C, VOUT = VCC ISINK Output Sink Current V CC = 10V, VIN(1) = 10V 8.0 mA TA = 25°C, VOUT = VCC

www.fairchildsemi.com 4 MM74C74 TA = 25°C, CL = 50 pF, unless otherwise noted Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Note 5: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note— AN-90. Typical Applications Ripple Counter (Divide by 2n) Shift Register 74C Compatibility Guaranteed Noise Margin as a Function of VCC Symbol Parameter Conditions Min Typ Max Units C IN Input Capacitance Any Input (Note 4) 5.0 pF tpd Propagation Delay Time to a V CC = 5V 180 300 ns Logical “0” tpd0 or Logical “1” VCC = 10V 70 110 tpd1 from Clock to Q or Q tpd Propagation Delay Time to a V CC = 5V 180 300 ns Logical “0” from Preset or Clear V CC = 10V 70 110 tpd Propagation Delay Time to a V CC = 5V 250 400 ns Logical “1” from Preset or Clear V CC = 10V 100 150 tS0, tS1 Time Prior to Clock Pulse that V CC = 5V 100 50 ns Data Must be Present tSETUP VCC = 10V 40 20 tH0 , tH1 Time after Clock Pulse that V CC = 5V −20 0 ns Data Must be Held V CC = 10V −8.0 0 tPW1 Minimum Clock Pulse V CC = 5V 100 250 ns Width (tWL = tWH )V CC = 10V 40 100 tPW2 Minimum Preset and V CC = 5V 100 160 ns Clear Pulse Width V CC = 10V 40 70 tr, tf Maximum Clock Rise V CC = 5V 15.0 µs and Fall Time V CC = 10V 5.0 fMAX Maximum Clock Frequency V CC = 5V 2.0 3.5 MHz VCC = 10V 5.0 8.0 C PD Power Dissipation Capacitance (Note 5) 40 pF

5 www.fairchildsemi.com MM74C74 Switching Time Waveform CMOS to CMOS tr = tf = 20 ns AC Test Circuit

www.fairchildsemi.com 6 MM74C74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A

7 www.fairchildsemi.com MM74C74 Dual D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com