MM54C74 NSC | Alldatasheet

Document overview

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Technical content

Features

Y Supply voltage range 3V to 15V Y Tenth power TTL compatible Drive 2 LPT 2L loads Y High noise immunity 0.45 V CC (typ.) Y Low power 50 nW (typ.) Y Medium speed operation 10 MHz (typ.) with 10V supply

Applications

TL/F/5885–1 Truth Table Preset Clear Q n Qn 00 0 0 01 1 0 10 0 1 11 *Q n *Qn *No change in output from previous state. Order Number MM54C74 or MM74C74 Connection Diagram Dual-In-Line Package TL/F/5885–2Top View Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’. A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin (Note 1) b0.3V to V CC a0.3V Operating Temperature Range MM54C74 b55§Ct o a125§C MM74C74 b40§Ct o a85§C Storage Temperature Range b65§Ct o a150§C Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (Soldering, 10 seconds) 260 Operating V CC Range 3V to 15V VCC(Max) 18V Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5V 3.5 V VCC e 10V 80 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5V 4.5 V VCC e 10V 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5V 0.5 V VCC e 10V 1.0 V IIN(1) Logical ‘‘1’’ Input Current V CC e 15V 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V CC e 15V b1.0 mA ICC Supply Current V CC e 15V 0.05 60 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, V CC e 4.5V VCCb1.574C, V CC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C, V CC e 4.75V 0.8 V74C, V CC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, V CC e 4.5V, I D eb 360 mA 2.4 V74C, V CC e 4.75V, I D eb 360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C, V CC e 4.5V, I D e 360 mA 0.4 V74C, V CC e 4.75V, I D e 360 mA OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) ISOURCE Output Source Current V CC e 5V, V IN(0) e 0V b1.75 mATA e 25§C, V OUT e 0V ISOURCE Output Source Current V CC e 10V, V IN(0) e 0V b8.0 mATA e 25§C, V OUT e 0V ISINK Output Sink Current V CC e 5V, V IN(1) e 5V 1.75 mATA e 25§C, V OUT e VCC ISINK Output Sink Current V CC e 10V, V IN(1) e 10V 8.0 mATA e 25§C, V OUT e VCC Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

Symbol Parameter Conditions Min Typ Max Units CIN Input Capacitance Any Input (Note 2) 5.0 pF tpd Propagation Delay Time to a V CC e 5V 180 300 ns Logical ‘‘0’’ t pd0 or Logical ‘‘1’’ V CC e 10V 70 110 ns tpd1 from Clock to Q or Q tpd Propagation Delay Time to a V CC e 5V 180 300 ns Logical ‘‘0’’ from Preset or Clear V CC e 10V 70 110 ns tpd Propagation Delay Time to a V CC e 5V 250 400 ns Logical ‘‘1’’ from Preset or Clear V CC e 10V 100 150 ns tS0,t S1 Time Prior to Clock Pulse that V CC e 5V 100 50 ns Data Must be Present t SETUP VCC e 10V 40 20 ns tH0,t H1 Time after Clock Pulse that V CC e 5V b20 0 ns Data Must be Held V CC e 10V b8.0 0 ns tPW1 Minimum Clock Pulse V CC e 5V 100 250 ns Width (t WL e tWH)V CC e 10V 40 100 ns tPW2 Minimum Preset and V CC e 5V 100 160 ns Clear Pulse Width V CC e 10V 40 70 ns tr,t f Maximum Clock Rise V CC e 5V 15.0 ms and Fall Time V CC e 10V 5.0 ms fMAX Maximum Clock Frequency V CC e 5V 2.0 3.5 MHz VCC e 10V 5.0 8.0 MHz CPD Power Dissipation Capacitance (Note 3) 40 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application NoteÐAN-90. Switching Time Waveform CMOS to CMOS TL/F/5885–3 tr e tf e 20 ns

TL/F/5885–4 Typical Applications Ripple Counter (Divide by 2 n) TL/F/5885–5 Shift Register TL/F/5885–6 74C Compatibility TL/F/5885–7 Guaranteed Noise Margin as a Function of V CC TL/F/5885–8

Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C74J or MM74C74J

MM54C74/MM74C74 Dual D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Ceramic Dual-In-Line Package (J) Order Number MM54C74N or MM74C74N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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