MM74C374

MM54C373 NSC | Alldatasheet

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Y Wide supply voltage range 3V to 15V Y High noise immunity 0.45 V CC (typ.) Y Low power consumption Y TTL compatibility Fan out of 1 driving standard TTL Y Bus driving capability Y TRI-STATE outputs Y Eight storage elements in one package Y Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control inputs Y 20-pin dual-in-line package with 0.300 × centers takes half the board space of a 24-pin package Connection Diagrams MM54C373/MM74C373 Dual-In-Line Package TL/F/5906–1 Top View Order Number MM54C373 or MM74C373 MM54C374/MM74C374 Dual-In-Line Package TL/F/5906–2 Top View Order Number MM54C374 or MM74C374 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin b0.3V to V CC a 0.3V Operating Temperature Range (T A) MM54C373 b55§Ct o a125§C MM74C373 b40§Ct o a85§C Storage Temperature Range (T S) b65§Ct o a150§C Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3V to 15V Absolute Maximum V CC 18V Lead Temperature (T L) (Soldering, 10 seconds) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5V 3.5 V VCC e 10V 8.0 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5V, I O eb 10 mA 4.5 V VCC e 10V, I O eb 10 mA 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5V, I O e 10 mA 0.5 V VCC e 10V, I O e 10 mA 1.0 V IIN(1) Logical ‘‘1’’ Input Current V CC e 15V, V IN e 15V 0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V CC e 15V, V IN e 0V b1.0 b0.005 mA IOZ TRI-STATE Leakage Current V CC e 15V, V O e 15V 0.005 1.0 mA VCC e 15V, V O e 0V b1.0 b0.005 mA ICC Supply Current V CC e 15V 0.05 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C V CC e 4.5V V CC b 1.5 V 74C V CC e 4.75V V CC b 1.5 V VIN(0) Logical ‘‘0’’ Input Voltage 54C V CC e 4.5V 0.8 V 54C V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C V CC e 4.5V, I O eb 360 mAV CC b 0.4 V 74C V CC e 4.75V, I O eb 360 mAV CC b 0.4 V 54C V CC e 4.5V, I O eb 1.6 mA 2.4 V 74C V CC e 4.75V, I O eb 1.6 mA 2.4 V VOUT(0) Logical ‘‘0’’ Output Voltage 54C V CC e 4.5V, I O e 1.6 mA 0.4 V 74C V CC e 4.75V, I O e 1.6 mA 0.4 V OUTPUT DRIVE (Short Circuit Current) ISOURCE Output Source Current V CC e 5V, V OUT e 0V b12 b24 mATA e 25§C (Note 4) ISOURCE Output Source Current V CC e 10V, V OUT e 0V b24 b48 mATA e 25§C (Note 4) ISINK Output Sink Current V CC e 5V, V OUT e VCC 61 2 m A(N-Channel) T A e 25§C (Note 4) ISINK Output Sink Current V CC e 10V, V OUT e VCC 24 48 mA(N-Channel) T A e 25§C (Note 4) Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

MM54C373/MM74C373, T A e 25§C, C L e 50 pF, t r e tf e 20 ns, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units tpd0,t pd1 Propagation Delay, V CC e 5V, C L e 50 pF 165 330 ns LATCH ENABLE to Output V CC e 10V, C L e 50 pF 70 140 ns VCC e 5V, C L e 150 pF 195 390 ns VCC e 10V, C L e 150 pF 85 170 ns tpd0,t pd1 Propagation Delay Data LATCH ENABLE e VCC In to Output V CC e 5V, C L e 50 pF 155 310 ns VCC e 10V, C L e 50 pF 70 140 ns VCC e 5V, C L e 150 pF 185 370 ns VCC e 10V, C L e 150 pF 85 170 ns tSET-UP Minimum Set-Up Time Data In t HOLD e 0n s to CLOCK/LATCH ENABLE VCC e 5V 70 140 ns VCC e 10V 35 70 ns fMAX Maximum LATCH ENABLE Frequency V CC e 5V 3.5 6.7 MHz VCC e 10V 4.5 9.0 MHz tPWH Minimum LATCH ENABLE VCC 5V 75 150 ns Pulse Width V CC e 10V 55 110 ns tr,t f Maximum LATCH ENABLE VCC e 5V NA ms Rise and Fall Time V CC e 10V NA ms t1H,t 0H Propagation Delay OUTPUT R L e 10k, C L e 5p F DISABLE to High Impedance V CC e 5V 105 210 ns State (from a Logic Level) V CC e 10V 60 120 ns tH1,t H0 Propagation Delay OUTPUT R L e 10k, C L e 50 pF DISABLE to Logic Level V CC e 5V 105 210 ns (from High Impedance State) V CC e 10V 45 90 ns tTHL,t TLH Transition Time V CC e 5V, C L e 50 pF 65 130 ns VCC e 10V, C L e 50 pF 35 70 ns VCC e 5V, C L e 150 pF 110 220 ns VCC e 10V, C L e 150 pF 70 140 ns CLE Input Capacitance LE Input (Note 2) 7.5 10 pF COD Input Capacitance OUTPUT DISABLE 7.5 10 pFInput (Note 2) CIN Input Capacitance Any Other Input (Note 2) 5 7.5 pF COUT Output Capacitance High Impedance 10 15 pFState (Note 2) CPD Power Dissipation Capacitance Per Package (Note 3) 200 pF *AC Parameters are guaranteed by DC correlated testing.

MM54C374/MM74C374, T A e 25§C, C L e 50 pF, t r e tf e 20 ns, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units tpd0,t pd1 Propagation Delay, V CC e 5V, C L e 50 pF 150 300 ns CLOCK to Output V CC e 10V, C L e 50 pF 65 130 ns VCC e 5V, C L e 150 pF 180 360 ns VCC e 10V, C L e 150 pF 80 160 ns tSET-UP Minimum Set-Up Time Data In t HOLD e 0n s to CLOCK/LATCH ENABLE VCC e 5V 70 140 ns VCC e 10V 35 70 ns tPWH,t PWL Minimum CLOCK Pulse Width V CC e 5V 70 140 ns VCC e 10V 50 100 ns fMAX Maximum CLOCK Frequency V CC e 5V 3.5 7.0 MHz VCC e 10V 5 10 MHz t1H,t 0H Propagation Delay OUTPUT R L e 10k, C L e 50 pF DISABLE to High Impedance V CC e 5V 105 210 ns State (from a Logic Level) V CC e 10V 60 120 ns tH1,t H0 Propagation Delay OUTPUT R L e 10k, C L e 50 pF DISABLE to Logic Level V CC e 5V 105 210 ns (from High Impedance State) V CC e 10V 45 90 ns tTHL,t TLH Transition Time V CC e 5V, C L e 50 pF 65 130 ns VCC e 10V, C L e 50 pF 35 70 ns VCC e 5V, C L e 150 pF 110 220 ns VCC e 10V, C L e 150 pF 70 140 ns tr,t f Maximum CLOCK Rise V CC e 5V 15 l2000 ms and Fall Time V CC e 10V 5 l2000 ms CCLK Input Capacitance CLOCK Input (Note 2) 7.5 10 pF COD Input Capacitance OUTPUT DISABLE 7.5 10 pFInput (Note 2) CIN Input Capacitance Any Other Input (Note 2) 5 7.5 pF COUT Output Capacitance High Impedance 10 15 pFState (Note 2) CPD Power Dissipation Capacitance Per Package (Note 3) 250 pF *AC Parameters are guaranteed by DC correlated testing. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note AN-90. Note 4: These are peak output current capabilities. Continuous output current is rated at 12 mA max.

Typical Performance Characteristics TA e 25§C MM54C373/MM74C373 Propagation Delay, LATCH Capacitance ENABLE to Output vs Load MM54C373/MM74C373 Data In to Output Propagation Delay, vs Load Capacitance MM54C374/MM74C374 CLOCK to Output Propagation Delay, vs Load Capacitance TL/F/5906–3 MM54C374/MM74C374 MM54C373/MM74C373, Change in Propagation Delay per vs Power Supply Voltage pF of Load Capacitance ( DtPD/pF) Output Sink Current vs V OUT MM54C374/MM74C374 MM54C373/MM74C373, Source Current vs V CC b VOUT MM54C374/MM74C374 Output MM54C373/MM74C373, TL/F/5906–4 Truth Table MM54C373/MM74C373 Output LATCH DQDisable ENABLE LH H H LH L L LL X Q H X X Hi-Z MM54C374/MM74C374 Output Clock D QDisable L L HH L L LL LL X Q LH X Q H X X Hi-Z L e Low logic level H e High logic level X e Irrelevant L e Low to high logic level transition Q e Preexisting output level Hi-Z e High impedance output state

Data Bus Interfacing Element TL/F/5906–5 Simple, Latching, Octal, LED Indicator Driver with Blanking for Use as Data Display, Bus Monitor, mP Front Panel Display, Etc. TL/F/5906–6 Logic Diagrams MM54C373/MM74C373 (1 of 8 Latches) TL/F/5906–7 MM54C374/MM74C374 (1 of 8 Flip-Flops) TL/F/5906–8

TRI-STATE Test Circuits and Switching Time Waveforms t1H,t H1 t1H,C L e 5p F t H1,C L e 50 pF TL/F/5906–9 TL/F/5906–10 t0H,t H0 t0H,C L e 5p F t H0,C L e 50 pF TL/F/5906–11 TL/F/5906–12 Switching Time Waveforms MM54C373/MM74C373 TL/F/5906–13 Output Disable e GND MM54C374/MM74C374 TL/F/5906–14 Output Disable e GND

MM54C373/MM74C373 TRI-STATE Octal D-Type Latch MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C373J, MM54C374J, MM74C373J or MM74C374J Molded Dual-In-Line Package (N) Order Number MM54C373N, MM54C374N, MM74C373N or MM74C374N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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