MM74C373

MM74C373 FAIRCHILD | Alldatasheet

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Technical content

Features

I Wide supply voltage range: 3V to 15V I High noise immunity: 0.45 VCC (typ.) I Low power consumption I TTL compatibility: Fan out of 1driving standard TTL I Bus driving capability I 3-STATE outputs I Eight storage elements in one package I Single CLOCK/LATCH ENABLE and OUTPUT DIS- ABLE control inputs I 20-pin dual-in-line package with 0.300” centers takes half the board space of a 24-pin package Ordering Code: Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description MM74C373M (Note 1) M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74C373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74C374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2 MM74C373  MM74C374 Connection Diagrams MM74C373 Top View MM74C374 Top View Truth Tables MM74C373 L = LOW logic level H = HIGH logic level X = Irrelevant MM74C374 /c17 = LOW-to-HIGH logic level transition Q = Preexisting output level Hi-Z = High impedance output state Output LATCH DQ Disable ENABLE LHHH LHLL LLX Q H X X Hi-Z Output Clock D Q Disable L /c17 HH L /c17 LL LLX Q LHXQ H X X Hi-Z

3 www.fairchildsemi.com MM74C373  MM74C374 Block Diagrams MM74C373 (1 of 8 Latches) MM74C374 (1 of 8 Flip-Flops)

www.fairchildsemi.com 4 MM74C373  MM74C374 Absolute Maximum Ratings(Note 2) Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise noted Note 3: These are peak output current capabilities. Continuous output current is rated at 12 mA max. Voltage at Any Pin −0.3V to VCC + 0.3V Operating Temperature Range (TA) MM74C373 −55°C to +125°C Storage Temperature Range (TS) −65°C to +150°C Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range 3V to 15V Absolute Maximum VCC 18V Lead Temperature (TL) (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS V IN(1) Logical “1” Input Voltage V CC = 5V 3.5 V VCC = 10V 8.0 VIN(0) Logical “0” Input Voltage V CC = 5V 1.5 V VCC = 10V 2.0 VOUT(1) Logical “1” Output Voltage V CC = 5V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 VOUT(0) Logical “0” Output Voltage V CC = 5V, IO = 10 µA0 . 5 V VCC = 10V, IO = 10 µA1 . 0 IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA IOZ 3-STATE Leakage Current V CC = 15V, VO = 15V 0.005 1.0 µA VCC = 15V, VO = 0V −1.0 −0.005 ICC Supply Current V CC = 15V 0.05 300 µA CMOS/LPTTL INTERFACE V IN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 V VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage V CC = 4.75V, IO = −360 µAV CC − 0.4 V VCC = 4.75V, IO = −1.6 mA 2.4 VOUT(0) Logical “0” Output Voltage V CC = 4.75V, IO = 1.6 mA 0.4 V OUTPUT DRIVE (Short Circuit Current) I SOURCE Output Source Current V CC = 5V, VOUT = 0V −12 −24 mA TA = 25°C (Note 3) ISOURCE Output Source Current V CC = 10V, VOUT = 0V −24 −48 mA TA = 25°C (Note 3) ISINK Output Sink Current V CC = 5V, VOUT = VCC 61 2 m A (N-Channel) T A = 25°C (Note 3) ISINK Output Sink Current V CC = 10V, VOUT = VCC 24 48 mA (N-Channel) T A = 25°C (Note 3)

5 www.fairchildsemi.com MM74C373  MM74C374 MM74C373, T A = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Capacitance is guaranteed by periodic testing. Note 6: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. Symbol Parameter Conditions Min Typ Max Units tpd0, tpd1 Propagation Delay, V CC = 5V, CL = 50 pF 165 330 ns LATCH ENABLE to Output V CC = 10V, CL = 50 pF 70 140 VCC = 5V, CL = 150 pF 195 390 VCC = 10V, CL = 150 pF 85 170 tpd0, tpd1 Propagation Delay Data LATCH ENABLE = VCC In to Output V CC = 5V, CL = 50 pF 155 310 ns VCC = 10V, CL = 50 pF 70 140 VCC = 5V, CL = 150 pF 185 370 VCC = 10V, CL = 150 pF 85 170 tSET-UP Minimum Set-Up Time Data In t HOLD = 0 ns to CLOCK/LATCH ENABLE VCC = 5V 70 140 ns VCC = 10V 35 70 fMAX Maximum LATCH ENABLE VCC = 5V 3.5 6.7 MHz Frequency V CC = 10V 4.5 9.0 tPWH Minimum LATCH ENABLE VCC 5V 75 150 ns Pulse Width V CC = 10V 55 110 tr, tf Maximum LATCH ENABLE VCC = 5V NA µs Rise and Fall Time V CC = 10V NA t1H , t0H Propagation Delay OUTPUT R L = 10k, CL = 5 pF DISABLE to High Impedance V CC = 5V 105 210 ns State (from a Logic Level) V CC = 10V 60 120 tH1 , tH0 Propagation Delay OUTPUT R L = 10k, CL = 50 pF DISABLE to Logic Level V CC = 5V 105 210 ns (from High Impedance State) V CC = 10V 45 90 tTHL , tTLH Transition Time V CC = 5V, CL = 50 pF 65 130 ns VCC = 10V, CL = 50 pF 35 70 VCC = 5V, CL = 150 pF 110 220 VCC = 10V, CL = 150 pF 70 140 C LE Input Capacitance LE Input (Note 5) 7.5 10 pF C OD Input Capacitance OUTPUT DISABLE 7.5 10 pF Input (Note 5) C IN Input Capacitance Any Other Input (Note 5) 5 7.5 pF C OUT Output Capacitance High Impedance 10 15 pF State (Note 5) C PD Power Dissipation Capacitance Per Package (Note 6) 200 pF

www.fairchildsemi.com 6 MM74C373  MM74C374 MM74C374, T A = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted Note 7: AC Parameters are guaranteed by DC correlated testing. Note 8: Capacitance is guaranteed by periodic testing. Note 9: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. Symbol Parameter Conditions Min Typ Max Units tpd0, tpd1 Propagation Delay, V CC = 5V, CL = 50 pF 150 300 ns CLOCK to Output V CC = 10V, CL = 50 pF 65 130 VCC = 5V, CL = 150 pF 180 360 VCC = 10V, CL = 150 pF 80 160 tSET-UP Minimum Set-Up Time Data In t HOLD = 0 ns to CLOCK/LATCH ENABLE VCC = 5V 70 140 ns VCC = 10V 35 70 tPWH , tPWL Minimum CLOCK Pulse Width V CC = 5V 70 140 ns VCC = 10V 50 100 fMAX Maximum CLOCK Frequency V CC = 5V 3.5 7.0 MHz VCC = 10V 5 10 t1H , t0H Propagation Delay OUTPUT R L = 10k, CL = 50 pF DISABLE to High Impedance V CC = 5V 105 210 ns State (from a Logic Level) V CC = 10V 60 120 tH1 , tH0 Propagation Delay OUTPUT R L = 10k, CL = 50 pF DISABLE to Logic Level V CC = 5V 105 210 ns (from High Impedance State) V CC = 10V 45 90 tTHL , tTLH Transition Time V CC = 5V, CL = 50 pF 65 130 ns VCC = 10V, CL = 50 pF 35 70 VCC = 5V, CL = 150 pF 110 220 VCC = 10V, CL = 150 pF 70 140 tr, tf Maximum CLOCK Rise V CC = 5V 15 >2000 µs and Fall Time V CC = 10V 5 >2000 C CLK Input Capacitance CLOCK Input (Note 8) 7.5 10 pF C OD Input Capacitance OUTPUT DISABLE 7.5 10 pF Input (Note 8) C IN Input Capacitance Any Other Input (Note 8) 5 7.5 pF C OUT Output Capacitance High Impedance 10 15 pF State (Note 8) C PD Power Dissipation Capacitance Per Package (Note 9) 250 pF

7 www.fairchildsemi.com MM74C373  MM74C374 Typical Performance Characteristics MM74C373 Propagation Delay, LATCH ENABLE to Output vs Load Capacitance MM74C373 Propagation Delay, Data In to Output vs Load Capacitance MM74C373 Propagation Delay, CLOCK to Output vs Load Capacitance MM74C373, MM74C374 Change in Propagation Delay per pF of Load Capacitance (∆tPD /pF) vs Power Supply Voltage MM74C373, MM74C374 Output Sink Current vs VOUT MM74C373, MM74C374 Source Current vs VCC − VOUT

www.fairchildsemi.com 8 MM74C373  MM74C374 Typical Applications Data Bus Interfacing Element Simple, Latching, Octal, LED Indicator Driver with Blanking for Use as Data Display, Bus Monitor, µP Front Panel Display, Etc. 3-STATE Test Circuits and Switching Time Waveforms t1H , tH1 t1H , CL = 5 pF tH1 , CL = 50 pF t0H , tH0 t0H , CL = 5 pF tH0 , CL = 50 pF

9 www.fairchildsemi.com MM74C373  MM74C374 Switching Time Waveforms MM74C373 Output Disable = GND MM74C374 Output Disable = GND

www.fairchildsemi.com 10 MM74C373  MM74C374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B

11 www.fairchildsemi.com MM74C373  MM74C374 3-STATE Octal D-Type Latch  3-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com