MM74C200N

MM54C200 TI1 | Alldatasheet

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MM54C200,MM74C200 MM54C200 MM74C200 256-Bit TRI-STATE Random Access Read/Write Memory Literature Number: SNOS329A

MM54C200/MM74C200 256-Bit TRI-STATE Random Access Read/Write Memory February 1988 MM54C200/MM74C200 256-Bit TRI-STATE É Random Access Read/Write Memory General Description The MM54C200/MM74C200 is a 256-bit random access read/write memory. Inputs consist of eight address lines and three chip enables. The eight binary address inputs are decoded internally to select each of the 256 locations. The internal address register, latches, and address information are on the positive to negative edge of CE 3. The TRI- STATE data output line, working in conjunction with CE 1 or CE2 inputs, provides for easy memory expansion. Address Operation: Address inputs must be stable t SA pri- or to the positive to negative transition of CE 3. It is therefore unnecessary to hold address information stable for more than t HA after the memory is enabled (positive to negative transition). Note: The timing is different from the DM74200 in that a positive to negative transition of the CE 3 must occur for the memory to be selected. Read Operation: The data is read out by selecting the proper address and bringing CE 3 low and WE high. Holding either CE 1,C E 2,o rC E 3 at a high level forces the output into TRI-STATE. When used in bus-organized sys- tems, CE 1,o rC E 2, a TRI-STATE control provides for fast access times by not totally disabling the chip. Write Operation: Data is written into the memory with CE 3 low and WE low. The state of CE 1 or CE 2 has no effect on the write cycle. The output assumes TRI-STATE with WE low.

Features

Y Wide supply voltage range 3V to 15V Y Guaranteed noise margin 1V Y High noise immunity 0.45 V CC (typ.) Y TTL compatibility Fan out of 1 driving standard TTL Y Low power 500 nW (typ.) Y Internal address register Logic and Connection Diagrams TL/F/5903–1 Dual-In-Line Package TL/F/5903–2 Top View Order Number MM54C200 or MM74C200 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Obsolete

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin b0.3V to V CCa0.3V Operating Temperature Range (T A) MM54C200 b55§Ct o a125§C MM74C200 b40§Ct o a85§C Storage Temperature Range (T S) b65§Ct o a150§C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3V to 15V Absolute Maximum V CC 18V Lead Temperature (T L) (Soldering, 10 seconds) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5V 3.5 V VCC e 10V 8 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5V 1.5 V VCC e 10V 2 V VOUT(1) Logical ‘‘1’’ Output Voltage V CCe5V, I Oeb10 mA 4.5 V VCCe10V, I Oeb10 mA9 V VOUT(0) Logical ‘‘0’’ Output Voltage V CCe5V, I Oea 10 mA 0.5 V VCCe10V, I Oea 10 mA1 V IIN(1) Logical ‘‘1’’ Input Current V CCe15V, V INe15V 0.005 1 mA IIN(0) Logical ‘‘0’’ Input Current V CCe15V, V INe0V b1 b0.005 mA ICC Supply Current VCC e 15V 0.1 600 mA CMOS/TTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C V CC e 4.5V VCCb1.5 V 74C V CC e 4.75V VCCb1.5 V VIN(0) Logical ‘‘0’’ Input Voltage 54C V CC e 4.5V 0.8 V 74C V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C V CCe4.5V, I Oeb1.6 mA 2.4 V 74C V CCe4.75V, I Oeb1.6 mA 2.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CCe5V, V OUTe0V b4 b6m A (P-Channel) TAe25§C b1.8 mA ISOURCE Output Source Current V CCe10V, V OUTe0V b16 b25 mA (P-Channel) T Ae25§C b1.5 mA ISINK Output Sink Current VCCe5V, V OUTeVCC 58 m A(N-Channel) TAe25§C ISINK Output Sink Current VCCe10V, V OUTeVCC 20 30 mA(N-Channel) T Ae25§C Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Obsolete

Symbol Parameter Conditions Min Typ Max Units tACC Access Time from Address VCC e 5V 450 900 ns VCC e 10V 200 400 ns tpd Propagation Delay from CE 3 VCC e 5V 360 700 ns VCC e 10V 120 300 ns tpCE1 Propagation Delay from CE 1 or CE 2 VCC e 5V 250 700 ns VCC e 10V 85 200 ns tSA Address Setup Time VCC e 5V 200 80 ns VCC e 10V 100 30 ns tHA Address Hold Time VCC e 5V 50 15 ns VCC e 10V 25 5.0 ns tWE Write Enable Pulse Width VCC e 5V 300 160 ns VCC e 10V 150 70 ns tCE CE3 Pulse Widths VCC e 5V 400 200 ns VCC e 10V 160 80 ns CIN Input Capacity Any Input (Note 2) 5.0 pF COUT Output Capacity in TRI-STATE (Note 2) 9.0 pF CPD Power Dissipation Capacity (Note 3) 400 pF MM54C200 MM74C200 Symbol Parameter Conditions T Aeb55§Ct o a125§CT Aeb40§Ct o a85§C Units Min Max Min Max tACC Access Time from Address V CC e 5V 1200 1100 ns VCC e 10V 520 480 ns tpd Propagation Delay from CE 3 VCC e 5V 950 850 ns VCC e 10V 400 360 ns tpdCE1 Propagation Delay from V CC e 5V 650 600 ns CE1 or CE 2 VCC e 10V 300 275 ns tSA Address Setup Time VCC e 5V 250 250 ns VCC e 10V 120 120 ns tHA Address Hold Time VCC e 5V 100 100 ns VCC e 10V 50 50 ns tWE Write Enable Pulse Width V CC e 5V 450 400 ns VCC e 10V 225 200 ns tCE Disable Pulse Width VCC e 5V 500 460 ns VCC e 10V 250 230 ns tHD Data Hold Time VCC e 5V 50 50 ns VCC e 10V 25 25 ns *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note, AN-90. Obsolete

Read and Write Cycles Using CE 3 (CE1 e CE2 e logic 0) TL/F/5903–3 Read and Write Cycles Using CE 3 and CE 1 (or CE 2) TL/F/5903–4 Note: Used for fast access time in bused systems. Obsolete

Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C200J or MM74C200J Obsolete

MM54C200/MM74C200 256-Bit TRI-STATE Random Access Read/Write Memory Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C200N or MM74C200N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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