MM74C193N

MM54C192 NSC | Alldatasheet

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Features

Y High noise margin 1V guaranteed Y Tenth power TTL compatible Drive 2 LPTTL loads Y Wide supply range 3V to 15V Y Carry and borrow outputs for N-bit cascading Y Asynchronous clear Y High noise immunity 0.45 V CC (typ.) Connection Diagram Dual-In-Line Package TL/F/5901–1 Top View Order Number MM54C192, MM74C192, MM54C193 or MM74C193 C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin b0.3V to V CC a 0.3V Operating Temperature Range (T A) MM54C154 b55§Ct o a125§C MM74C154 b40§Ct o a85§C Storage Temperature Range (T S) b65§Ct o a150§C Maximum V CC Voltage 18V Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3V to 15V Lead Temperature (T A) (Soldering, 10 sec.) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5V 3.5 V VCC e 10V 8.0 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5V, I O eb 10 mA 4.5 V VCC e 10V, I O eb 10 mA 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5V, I O e 10 mA 0.5 V VCC e 10V, I O e 10 mA 1.0 V IIN(1) Logical ‘‘1’’ Input Current V CC e 15V, V IN e 15V 0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V CC e 15V, V IN e 0V b1.0 b0.005 mA ICC Supply Current V CC e 15V 0.05 300 mA CMOS TO LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C V CC e 4.5V V CC b 1.5 V 74C V CC e 4.75V V CC b 1.5 V VIN(0) Logical ‘‘0’’ Input Voltage 54C V CC e 4.5V 0.8 V 74C V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C V CC e 4.5V, I O eb 100 mA 2.4 V 74C V CC e 4.75V, I O eb 100 mA 2.4 V VOUT(0) Logical ‘‘0’’ Output Voltage 54C V CC e 4.5V, I O e 360 mA 0.4 V 74C V CC e 4.75V, I O e 360 mA 0.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC e 5V, V IN(0) e 0V b1.75 mATA e 25§C, V OUT e 0V ISOURCE Output Source Current V CC e 10V, V IN(0) e 0V b8m ATA e 25§C, V OUT e 0V ISINK Output Sink Current V CC e 5V, V IN(1) e 5V 1.75 mATA e 25§C, V OUT e VCC ISINK Output Sink Current V CC e 10V, V IN(1) e 10V 8m ATA e 25§C, V OUT e VCC Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay Time to Q V CC e 5V 250 400 ns from Count Up or Down V CC e 10V 100 160 ns tpd Propagation Delay Time to Q V CC e 5V 120 200 ns Borrow from Count Down V CC e 10V 50 80 ns tpd Propagation Delay Time to V CC e 5V 120 200 ns Carry from Count Up V CC e 10V 50 80 ns tS Time Prior to Load that Data V CC e 5V 100 160 ns Must be Present V CC e 10V 30 50 ns tW Minimum Clear Pulse Width V CC e 5V 300 480 ns VCC e 10V 120 190 ns tW Minimum Load Pulse Width V CC e 5V 100 160 ns VCC e 10V 40 65 ns tpd0,t pd1 Propagation Delay Time to Q V CC e 5V 300 480 ns from Load V CC e 10V 120 190 ns tW Minimum Count Pulse Width V CC e 5V 120 200 ns VCC e 10V 35 80 ns fMAX Maximum Count Frequency V CC e 5V 2.5 4 MHz VCC e 10V 6 10 MHz tr,t f Count Rise and Fall Time V CC e 5V 15 ms VCC e 10V 5 ms CIN Input Capacitance (Note 2) 5 pF CPD Power Dissipation Capacitance (Note 3) 100 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics, Application Note AN-90. Cascading Packages TL/F/5901–2 Guaranteed Noise Margin as a Function of V CC TL/F/5901–3

TL/F/5901–4 Note 1: Clear ouptuts to zero. Note 2: Load (preset) to binary thirteen. Note 3: Count up to fourteen, fifteen, carry, zero, one and two. Note 4: Count down to one, zero, borrow, fifteen, fourteen, and thirteen. MM54C193/MM74C193 TL/F/5901–5 Note 1: Clear ouptuts to zero. Note 2: Load (preset) to BCD seven. Note 3: Count up to eight, nine, carry, zero, one, and two. Note 4: Count down to one, zero, borrow, nine, eight, and seven. Note A: Clear overrides load, data, and count inputs. Note B: When counting up, count down input must be high; when counting down, count-up input must be high.

MM54C192 Synchronous 4-Bit Up/Down Decade Counter TL/F/5901–6 MM54C193 Synchronous 4-Bit Up/Down Binary Counter TL/F/5901–7

MM54C192/MM74C192 Synchronous 4-Bit Up/Down Decade Counter MM54C193/MM74C193 Synchronous 4-Bit Up/Down Binary Counter Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C192J, MM74C192J, MM54C193J or MM74C193J Molded Dual-In-Line Package (N) Order Number MM54C192N, MM74C192N, MM54C193N or MM74C193N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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