MM74C192N

MM74C192 FAIRCHILD | Alldatasheet

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Technical content

Features

■ High noise margin: 1V guaranteed ■ Tenth power TTL compatible: Drive 2 LPTTL loads ■ Wide supply range: 3V to 15V ■ Carry and borrow outputs for N-bit cascading ■ Asynchronous clear ■ High noise immunity: 0.45 VCC (typ.) Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Top View Order Number Package Number Package Description MM74C192N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74C193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 MM74C192 • MM74C193 Absolute Maximum Ratings(Note 1) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The Electrical Characteristics table provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise noted Voltage at Any Pin −0.3V to VCC + 0.3V Operating Temperature Range (TA) −40°C to +85°C Storage Temperature Range (TS) −65°C to +150°C Maximum V CC Voltage 18V Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range 3V to 15V Lead Temperature (TA) (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5V 3.5 V VCC = 10V 8.0 V VIN(0) Logical “0” Input Voltage V CC = 5V 1.5 V VCC = 10V 2.0 V VOUT(1) Logical “1” Output Voltage V CC = 5V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 V VOUT(0) Logical “0” Output Voltage V CC = 5V, IO = 10 µA0 . 5 V VCC = 10V, IO = 10 µA1 . 0 V IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.05 300 µA CMOS TO LPTTL INTERFACE VIN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 V VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage V CC = 4.75V, IO = −100 µA2 . 4 V VOUT(0) Logical “0” Output Voltage V CC = 4.75V, IO = 360 µA0 . 4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC = 5V, VIN(0) = 0V −1.75 mA TA = 25°C, VOUT = 0V ISOURCE Output Source Current V CC = 10V, VIN(0) = 0V −8m A TA = 25°C, VOUT = 0V ISINK Output Sink Current V CC = 5V, VIN(1) = 5V 1.75 mA TA = 25°C, VOUT = VCC ISINK Output Sink Current V CC = 10V, VIN(1) = 10V 8 mA TA = 25°C, VOUT = VCC

3 www.fairchildsemi.com MM74C192 • MM74C193 TA = 25°C, CL = 50 pF, unless otherwise noted Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see Application Note AN-90. Cascading Packages Guaranteed Noise Margin as a Function of VCC Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay V CC = 5V 250 400 ns Time to Q from Count Up or Down V CC = 10V 100 160 ns tpd Propagation Delay V CC = 5V 120 200 ns Time to Q Borrow from Count Down VCC = 10V 50 80 ns tpd Propagation Delay V CC = 5V 120 200 ns Time to Carry from Count Up V CC = 10V 50 80 ns tS Time Prior to Load V CC = 5V 100 160 ns that Data Must be Present V CC = 10V 30 50 ns tW Minimum Clear Pulse Width V CC = 5V 300 480 ns VCC = 10V 120 190 ns tW Minimum Load Pulse Width V CC = 5V 100 160 ns VCC = 10V 40 65 ns tpd0 Propagation Delay V CC = 5V 300 480 ns tpd1 Time to Q from Load V CC = 10V 120 190 ns tW Minimum Count Pulse Width V CC = 5V 120 200 ns VCC = 10V 35 80 ns fMAX Maximum Count Frequency V CC = 5V 2.5 4 MHz VCC = 10V 6 10 MHz tr Count Rise and Fall Time V CC = 5V 15 µs tf VCC = 10V 5 µs C IN Input Capacitance (Note 3) 5 pF C PD Power Dissipation Capacitance (Note 4) 100 pF

www.fairchildsemi.com 4 MM74C192 • MM74C193 Timing Diagrams MM74C192 Note A: Clear outputs to zero. Note B: Load (preset) to binary thirteen. Note C: Count up to fourteen, fifteen, carry, zero, one and two. Note D: Count down to one, zero, borrow, fifteen, fourteen, and thirteen. MM74C193 Note A: Clear outputs to zero. Note B: Load (preset) to BCD seven. Note C: Count up to eight, nine, carry, zero, one, and two. Note D: Count down to one, zero, borrow, nine, eight, and seven. Note E: Clear overrides load, data, and count inputs. Note F: When counting up, count down input must be HIGH; when counting down, count-up input must be HIGH.

5 www.fairchildsemi.com MM74C192 • MM74C193 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A

www.fairchildsemi.com 6 MM74C192 • MM74C193 Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com